1 /* Copyright Statement:
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
10 * MediaTek Inc. (C) 2010. All rights reserved.
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
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27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
36 #include <linux/module.h>
37 #include <linux/moduleparam.h>
38 #include <linux/init.h>
39 #include <linux/spinlock.h>
40 #include <linux/timer.h>
41 #include <linux/ioport.h>
42 #include <linux/device.h>
43 #include <linux/platform_device.h>
44 #include <linux/interrupt.h>
45 #include <linux/delay.h>
46 #include <linux/blkdev.h>
47 #include <linux/slab.h>
48 #include <linux/mmc/host.h>
49 #include <linux/mmc/card.h>
50 #include <linux/mmc/core.h>
51 #include <linux/mmc/mmc.h>
52 #include <linux/mmc/sd.h>
53 #include <linux/mmc/sdio.h>
54 #include <linux/dma-mapping.h>
57 #include <linux/types.h>
58 #include <linux/kernel.h>
59 #include <linux/version.h>
63 //#define IRQ_SDC 14 //MT7620 /*FIXME*/
64 #ifdef CONFIG_SOC_MT7621
65 #define RALINK_SYSCTL_BASE 0xbe000000
66 #define RALINK_MSDC_BASE 0xbe130000
68 #define RALINK_SYSCTL_BASE 0xb0000000
69 #define RALINK_MSDC_BASE 0xb0130000
71 #define IRQ_SDC 22 /*FIXME*/
76 #include <asm/mach-ralink/ralink_regs.h>
78 #if 0 /* --- by chhung */
79 #include <mach/board.h>
80 #include <mach/mt6575_devs.h>
81 #include <mach/mt6575_typedefs.h>
82 #include <mach/mt6575_clock_manager.h>
83 #include <mach/mt6575_pm_ldo.h>
84 //#include <mach/mt6575_pll.h>
85 //#include <mach/mt6575_gpio.h>
86 //#include <mach/mt6575_gpt_sw.h>
88 // #include <mach/mt6575_gpt.h>
89 #endif /* end of --- */
91 #include "mt6575_sd.h"
98 #if 0 /* --- by chhung */
99 #define isb() __asm__ __volatile__ ("" : : : "memory")
100 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
101 : : "r" (0) : "memory")
102 #define dmb() __asm__ __volatile__ ("" : : : "memory")
103 #endif /* end of --- */
105 #define DRV_NAME "mtk-sd"
107 #define HOST_MAX_NUM (1) /* +/- by chhung */
109 #if defined(CONFIG_SOC_MT7620)
110 #define HOST_MAX_MCLK (48000000) /* +/- by chhung */
111 #elif defined(CONFIG_SOC_MT7621)
112 #define HOST_MAX_MCLK (50000000) /* +/- by chhung */
114 #define HOST_MIN_MCLK (260000)
116 #define HOST_MAX_BLKSZ (2048)
118 #define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
120 #define GPIO_PULL_DOWN (0)
121 #define GPIO_PULL_UP (1)
123 #if 0 /* --- by chhung */
124 #define MSDC_CLKSRC_REG (0xf100000C)
125 #define PDN_REG (0xF1000010)
126 #endif /* end of --- */
128 #define DEFAULT_DEBOUNCE (8) /* 8 cycles */
129 #define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
131 #define CMD_TIMEOUT (HZ / 10) /* 100ms */
132 #define DAT_TIMEOUT (HZ / 2 * 5) /* 500ms x5 */
134 #define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
136 #define MAX_GPD_NUM (1 + 1) /* one null gpd */
137 #define MAX_BD_NUM (1024)
138 #define MAX_BD_PER_GPD (MAX_BD_NUM)
140 #define MAX_HW_SGMTS (MAX_BD_NUM)
141 #define MAX_PHY_SGMTS (MAX_BD_NUM)
142 #define MAX_SGMT_SZ (MAX_DMA_CNT)
143 #define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
145 #ifdef MT6575_SD_DEBUG
146 static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
149 static int cd_active_low = 1;
151 //=================================
152 #define PERI_MSDC0_PDN (15)
153 //#define PERI_MSDC1_PDN (16)
154 //#define PERI_MSDC2_PDN (17)
155 //#define PERI_MSDC3_PDN (18)
157 #if 0 /* --- by chhung */
158 /* gate means clock power down */
159 static int g_clk_gate = 0;
160 #define msdc_gate_clock(id) \
162 g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
164 /* not like power down register. 1 means clock on. */
165 #define msdc_ungate_clock(id) \
167 g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
170 // do we need sync object or not
171 void msdc_clk_status(int *status)
173 *status = g_clk_gate;
175 #endif /* end of --- */
178 struct msdc_hw msdc0_hw = {
181 .flags = MSDC_CD_PIN_EN | MSDC_REMOVABLE,
182 // .flags = MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
187 static int msdc_rsp[] = {
199 /* For Inhanced DMA */
200 #define msdc_init_gpd_ex(_gpd, extlen, cmd, arg, blknum) \
202 ((struct gpd *)_gpd)->extlen = extlen; \
203 ((struct gpd *)_gpd)->cmd = cmd; \
204 ((struct gpd *)_gpd)->arg = arg; \
205 ((struct gpd *)_gpd)->blknum = blknum; \
208 #define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
209 #define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
210 #define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
211 #define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
212 #define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
213 #define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
215 #define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
216 #define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
218 #define msdc_retry(expr, retry, cnt) \
225 retry--; mdelay(1); cnt = backup; \
228 WARN_ON(retry == 0); \
231 static void msdc_reset_hw(struct msdc_host *host)
233 void __iomem *base = host->base;
235 sdr_set_bits(MSDC_CFG, MSDC_CFG_RST);
236 while (sdr_read32(MSDC_CFG) & MSDC_CFG_RST)
240 #define msdc_clr_int() \
242 volatile u32 val = sdr_read32(MSDC_INT); \
243 sdr_write32(MSDC_INT, val); \
246 #define msdc_clr_fifo() \
248 int retry = 3, cnt = 1000; \
249 sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
250 msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
253 #define msdc_irq_save(val) \
255 val = sdr_read32(MSDC_INTEN); \
256 sdr_clr_bits(MSDC_INTEN, val); \
259 #define msdc_irq_restore(val) \
261 sdr_set_bits(MSDC_INTEN, val); \
264 /* clock source for host: global */
265 #if defined(CONFIG_SOC_MT7620)
266 static u32 hclks[] = {48000000}; /* +/- by chhung */
267 #elif defined(CONFIG_SOC_MT7621)
268 static u32 hclks[] = {50000000}; /* +/- by chhung */
271 //============================================
272 // the power for msdc host controller: global
273 // always keep the VMC on.
274 //============================================
275 #define msdc_vcore_on(host) \
277 INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
278 (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
280 #define msdc_vcore_off(host) \
282 INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
283 (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
286 //====================================
287 // the vdd output for card: global
288 // always keep the VMCH on.
289 //====================================
290 #define msdc_vdd_on(host) \
292 (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
294 #define msdc_vdd_off(host) \
296 (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
299 #define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
300 #define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
302 #define sdc_send_cmd(cmd, arg) \
304 sdr_write32(SDC_ARG, (arg)); \
305 sdr_write32(SDC_CMD, (cmd)); \
308 // can modify to read h/w register.
309 //#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
310 #define is_card_present(h) (((struct msdc_host *)(h))->card_inserted)
314 #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
316 #define PHYSADDR(a) ((a) & 0x1fffffff)
319 static unsigned int msdc_do_command(struct msdc_host *host,
320 struct mmc_command *cmd,
322 unsigned long timeout);
324 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd);
326 #ifdef MT6575_SD_DEBUG
327 static void msdc_dump_card_status(struct msdc_host *host, u32 status)
329 /* N_MSG is currently a no-op */
331 static char *state[] = {
350 if (status & R1_OUT_OF_RANGE)
351 N_MSG(RSP, "[CARD_STATUS] Out of Range");
352 if (status & R1_ADDRESS_ERROR)
353 N_MSG(RSP, "[CARD_STATUS] Address Error");
354 if (status & R1_BLOCK_LEN_ERROR)
355 N_MSG(RSP, "[CARD_STATUS] Block Len Error");
356 if (status & R1_ERASE_SEQ_ERROR)
357 N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
358 if (status & R1_ERASE_PARAM)
359 N_MSG(RSP, "[CARD_STATUS] Erase Param");
360 if (status & R1_WP_VIOLATION)
361 N_MSG(RSP, "[CARD_STATUS] WP Violation");
362 if (status & R1_CARD_IS_LOCKED)
363 N_MSG(RSP, "[CARD_STATUS] Card is Locked");
364 if (status & R1_LOCK_UNLOCK_FAILED)
365 N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
366 if (status & R1_COM_CRC_ERROR)
367 N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
368 if (status & R1_ILLEGAL_COMMAND)
369 N_MSG(RSP, "[CARD_STATUS] Illegal Command");
370 if (status & R1_CARD_ECC_FAILED)
371 N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
372 if (status & R1_CC_ERROR)
373 N_MSG(RSP, "[CARD_STATUS] CC Error");
374 if (status & R1_ERROR)
375 N_MSG(RSP, "[CARD_STATUS] Error");
376 if (status & R1_UNDERRUN)
377 N_MSG(RSP, "[CARD_STATUS] Underrun");
378 if (status & R1_OVERRUN)
379 N_MSG(RSP, "[CARD_STATUS] Overrun");
380 if (status & R1_CID_CSD_OVERWRITE)
381 N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
382 if (status & R1_WP_ERASE_SKIP)
383 N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
384 if (status & R1_CARD_ECC_DISABLED)
385 N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
386 if (status & R1_ERASE_RESET)
387 N_MSG(RSP, "[CARD_STATUS] Erase Reset");
388 if (status & R1_READY_FOR_DATA)
389 N_MSG(RSP, "[CARD_STATUS] Ready for Data");
390 if (status & R1_SWITCH_ERROR)
391 N_MSG(RSP, "[CARD_STATUS] Switch error");
392 if (status & R1_APP_CMD)
393 N_MSG(RSP, "[CARD_STATUS] App Command");
395 N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
398 static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
401 N_MSG(RSP, "[OCR] Low Voltage Range");
402 if (resp & (1 << 15))
403 N_MSG(RSP, "[OCR] 2.7-2.8 volt");
404 if (resp & (1 << 16))
405 N_MSG(RSP, "[OCR] 2.8-2.9 volt");
406 if (resp & (1 << 17))
407 N_MSG(RSP, "[OCR] 2.9-3.0 volt");
408 if (resp & (1 << 18))
409 N_MSG(RSP, "[OCR] 3.0-3.1 volt");
410 if (resp & (1 << 19))
411 N_MSG(RSP, "[OCR] 3.1-3.2 volt");
412 if (resp & (1 << 20))
413 N_MSG(RSP, "[OCR] 3.2-3.3 volt");
414 if (resp & (1 << 21))
415 N_MSG(RSP, "[OCR] 3.3-3.4 volt");
416 if (resp & (1 << 22))
417 N_MSG(RSP, "[OCR] 3.4-3.5 volt");
418 if (resp & (1 << 23))
419 N_MSG(RSP, "[OCR] 3.5-3.6 volt");
420 if (resp & (1 << 24))
421 N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
422 if (resp & (1 << 30))
423 N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
424 if (resp & (1 << 31))
425 N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
427 N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
430 static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
432 u32 status = (((resp >> 15) & 0x1) << 23) |
433 (((resp >> 14) & 0x1) << 22) |
434 (((resp >> 13) & 0x1) << 19) |
437 N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
438 msdc_dump_card_status(host, status);
441 static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
443 u32 flags = (resp >> 8) & 0xFF;
445 char *state[] = {"DIS", "CMD", "TRN", "RFU"};
447 if (flags & (1 << 7))
448 N_MSG(RSP, "[IO] COM_CRC_ERR");
449 if (flags & (1 << 6))
450 N_MSG(RSP, "[IO] Illgal command");
451 if (flags & (1 << 3))
452 N_MSG(RSP, "[IO] Error");
453 if (flags & (1 << 2))
454 N_MSG(RSP, "[IO] RFU");
455 if (flags & (1 << 1))
456 N_MSG(RSP, "[IO] Function number error");
457 if (flags & (1 << 0))
458 N_MSG(RSP, "[IO] Out of range");
460 N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
464 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
466 void __iomem *base = host->base;
469 host->timeout_ns = ns;
470 host->timeout_clks = clks;
472 clk_ns = 1000000000UL / host->sclk;
473 timeout = ns / clk_ns + clks;
474 timeout = timeout >> 16; /* in 65536 sclk cycle unit */
475 timeout = timeout > 1 ? timeout - 1 : 0;
476 timeout = timeout > 255 ? 255 : timeout;
478 sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
480 N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
481 ns, clks, timeout + 1);
484 static void msdc_tasklet_card(struct work_struct *work)
486 struct msdc_host *host = (struct msdc_host *)container_of(work,
487 struct msdc_host, card_delaywork.work);
488 void __iomem *base = host->base;
493 spin_lock(&host->lock);
495 status = sdr_read32(MSDC_PS);
497 inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
499 inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
502 change = host->card_inserted ^ inserted;
503 host->card_inserted = inserted;
505 if (change && !host->suspend) {
507 host->mmc->f_max = HOST_MAX_MCLK; // work around
508 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
510 #else /* Make sure: handle the last interrupt */
511 host->card_inserted = inserted;
513 if (!host->suspend) {
514 host->mmc->f_max = HOST_MAX_MCLK;
515 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
518 IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
521 spin_unlock(&host->lock);
524 #if 0 /* --- by chhung */
526 static u8 clk_src_bit[4] = {
530 static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc)
533 void __iomem *base = host->base;
536 INIT_MSG("set clock source to <%d>", clksrc);
538 val = sdr_read32(MSDC_CLKSRC_REG);
539 if (sdr_read32(MSDC_ECO_VER) >= 4) {
540 val &= ~(0x3 << clk_src_bit[host->id]);
541 val |= clksrc << clk_src_bit[host->id];
543 val &= ~0x3; val |= clksrc;
545 sdr_write32(MSDC_CLKSRC_REG, val);
547 host->hclk = hclks[clksrc];
548 host->hw->clk_src = clksrc;
550 #endif /* end of --- */
552 static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
554 //struct msdc_hw *hw = host->hw;
555 void __iomem *base = host->base;
560 u32 hclk = host->hclk;
561 //u8 clksrc = hw->clk_src;
563 if (!hz) { // set mmc system clock to 0 ?
564 //ERR_MSG("set mclk to 0!!!");
569 msdc_irq_save(flags);
572 mode = 0x2; /* ddr mode and use divisor */
573 if (hz >= (hclk >> 2)) {
574 div = 1; /* mean div = 1/4 */
575 sclk = hclk >> 2; /* sclk = clk / 4 */
577 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
578 sclk = (hclk >> 2) / div;
580 } else if (hz >= hclk) { /* bug fix */
581 mode = 0x1; /* no divisor and divisor is ignored */
585 mode = 0x0; /* use divisor */
586 if (hz >= (hclk >> 1)) {
587 div = 0; /* mean div = 1/2 */
588 sclk = hclk >> 1; /* sclk = clk / 2 */
590 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
591 sclk = (hclk >> 2) / div;
595 /* set clock mode and divisor */
596 sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
597 sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
599 /* wait clock stable */
600 while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB))
605 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
607 INIT_MSG("================");
608 INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz / 1000, hclk / 1000, sclk / 1000);
609 INIT_MSG("================");
611 msdc_irq_restore(flags);
614 /* Fix me. when need to abort */
615 static void msdc_abort_data(struct msdc_host *host)
617 void __iomem *base = host->base;
618 struct mmc_command *stop = host->mrq->stop;
620 ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
626 // need to check FIFO count 0 ?
628 if (stop) { /* try to stop, but may not success */
629 ERR_MSG("stop when abort CMD<%d>", stop->opcode);
630 (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
633 //if (host->mclk >= 25000000) {
634 // msdc_set_mclk(host, 0, host->mclk >> 1);
638 #if 0 /* --- by chhung */
639 static void msdc_pin_config(struct msdc_host *host, int mode)
641 struct msdc_hw *hw = host->hw;
642 void __iomem *base = host->base;
643 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
646 if (hw->flags & MSDC_WP_PIN_EN) {
647 if (hw->config_gpio_pin) /* NULL */
648 hw->config_gpio_pin(MSDC_WP_PIN, pull);
652 case MSDC_PIN_PULL_UP:
653 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
654 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
655 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
656 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
657 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
658 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
660 case MSDC_PIN_PULL_DOWN:
661 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
662 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
663 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
664 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
665 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
666 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
668 case MSDC_PIN_PULL_NONE:
670 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
671 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
672 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
673 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
674 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
675 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
679 N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
680 mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
683 void msdc_pin_reset(struct msdc_host *host, int mode)
685 struct msdc_hw *hw = (struct msdc_hw *)host->hw;
686 void __iomem *base = host->base;
687 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
689 /* Config reset pin */
690 if (hw->flags & MSDC_RST_PIN_EN) {
691 if (hw->config_gpio_pin) /* NULL */
692 hw->config_gpio_pin(MSDC_RST_PIN, pull);
694 if (mode == MSDC_PIN_PULL_UP)
695 sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
697 sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
701 static void msdc_core_power(struct msdc_host *host, int on)
703 N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
704 on ? "on" : "off", "core", host->core_power, on);
706 if (on && host->core_power == 0) {
708 host->core_power = 1;
710 } else if (!on && host->core_power == 1) {
711 msdc_vcore_off(host);
712 host->core_power = 0;
717 static void msdc_host_power(struct msdc_host *host, int on)
719 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
722 //msdc_core_power(host, 1); // need do card detection.
723 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
725 msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
726 //msdc_core_power(host, 0);
730 static void msdc_card_power(struct msdc_host *host, int on)
732 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
735 msdc_pin_config(host, MSDC_PIN_PULL_UP);
736 //msdc_vdd_on(host); // need todo card detection.
739 //msdc_vdd_off(host);
740 msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
745 static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
747 N_MSG(CFG, "Set power mode(%d)", mode);
749 if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
750 msdc_host_power(host, 1);
751 msdc_card_power(host, 1);
752 } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
753 msdc_card_power(host, 0);
754 msdc_host_power(host, 0);
756 host->power_mode = mode;
758 #endif /* end of --- */
762 register as callback function of WIFI(combo_sdio_register_pm) .
763 can called by msdc_drv_suspend/resume too.
765 static void msdc_pm(pm_message_t state, void *data)
767 struct msdc_host *host = (struct msdc_host *)data;
768 int evt = state.event;
770 if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
771 INIT_MSG("USR_%s: suspend<%d> power<%d>",
772 evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
773 host->suspend, host->power_mode);
776 if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
777 if (host->suspend) /* already suspend */ /* default 0*/
780 /* for memory card. already power off by mmc */
781 if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
785 host->pm_state = state; /* default PMSG_RESUME */
787 } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
788 if (!host->suspend) {
789 //ERR_MSG("warning: already resume");
793 /* No PM resume when USR suspend */
794 if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
795 ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
800 host->pm_state = state;
806 /*--------------------------------------------------------------------------*/
807 /* mmc_host_ops members */
808 /*--------------------------------------------------------------------------*/
809 static unsigned int msdc_command_start(struct msdc_host *host,
810 struct mmc_command *cmd,
811 int tune, /* not used */
812 unsigned long timeout)
814 void __iomem *base = host->base;
815 u32 opcode = cmd->opcode;
817 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
818 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
819 MSDC_INT_ACMD19_DONE;
824 /* Protocol layer does not provide response type, but our hardware needs
825 * to know exact type, not just size!
827 if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND) {
829 } else if (opcode == MMC_SET_RELATIVE_ADDR) {
830 resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
831 } else if (opcode == MMC_FAST_IO) {
833 } else if (opcode == MMC_GO_IRQ_STATE) {
835 } else if (opcode == MMC_SELECT_CARD) {
836 resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
837 } else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED) {
838 resp = RESP_R1; /* SDIO workaround. */
839 } else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR)) {
842 switch (mmc_resp_type(cmd)) {
864 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
865 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
867 rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
869 if (opcode == MMC_READ_MULTIPLE_BLOCK) {
871 } else if (opcode == MMC_READ_SINGLE_BLOCK) {
873 } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
874 rawcmd |= ((2 << 11) | (1 << 13));
875 } else if (opcode == MMC_WRITE_BLOCK) {
876 rawcmd |= ((1 << 11) | (1 << 13));
877 } else if (opcode == SD_IO_RW_EXTENDED) {
878 if (cmd->data->flags & MMC_DATA_WRITE)
880 if (cmd->data->blocks > 1)
884 } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
886 } else if ((opcode == SD_APP_SEND_SCR) ||
887 (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
888 (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
889 (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
890 (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
892 } else if (opcode == MMC_STOP_TRANSMISSION) {
894 rawcmd &= ~(0x0FFF << 16);
897 N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode, rawcmd, cmd->arg);
899 tmo = jiffies + timeout;
901 if (opcode == MMC_SEND_STATUS) {
903 if (!sdc_is_cmd_busy())
906 if (time_after(jiffies, tmo)) {
907 ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
908 cmd->error = (unsigned int)-ETIMEDOUT;
917 if (time_after(jiffies, tmo)) {
918 ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
919 cmd->error = (unsigned int)-ETIMEDOUT;
926 //BUG_ON(in_interrupt());
928 host->cmd_rsp = resp;
930 init_completion(&host->cmd_done);
932 sdr_set_bits(MSDC_INTEN, wints);
933 sdc_send_cmd(rawcmd, cmd->arg);
939 static unsigned int msdc_command_resp(struct msdc_host *host,
940 struct mmc_command *cmd,
942 unsigned long timeout)
943 __must_hold(&host->lock)
945 void __iomem *base = host->base;
946 u32 opcode = cmd->opcode;
949 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
950 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
951 MSDC_INT_ACMD19_DONE;
953 resp = host->cmd_rsp;
955 BUG_ON(in_interrupt());
956 //init_completion(&host->cmd_done);
957 //sdr_set_bits(MSDC_INTEN, wints);
959 spin_unlock(&host->lock);
960 if (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) {
961 ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
962 cmd->error = (unsigned int)-ETIMEDOUT;
965 spin_lock(&host->lock);
967 sdr_clr_bits(MSDC_INTEN, wints);
971 #ifdef MT6575_SD_DEBUG
974 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
977 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
978 opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
979 cmd->resp[2], cmd->resp[3]);
981 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
982 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
983 opcode, cmd->error, resp, cmd->resp[0]);
984 if (cmd->error == 0) {
988 msdc_dump_card_status(host, cmd->resp[0]);
991 msdc_dump_ocr_reg(host, cmd->resp[0]);
994 msdc_dump_io_resp(host, cmd->resp[0]);
997 msdc_dump_rca_resp(host, cmd->resp[0]);
1005 /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
1010 /* memory card CRC */
1011 if (host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO)) {
1012 if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
1013 msdc_abort_data(host);
1015 /* do basic: reset*/
1016 msdc_reset_hw(host);
1020 cmd->error = msdc_tune_cmdrsp(host, cmd);
1024 /* if (resp == RESP_R1B) {
1025 while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
1027 /* CMD12 Error Handle */
1032 static unsigned int msdc_do_command(struct msdc_host *host,
1033 struct mmc_command *cmd,
1035 unsigned long timeout)
1037 if (msdc_command_start(host, cmd, tune, timeout))
1040 if (msdc_command_resp(host, cmd, tune, timeout))
1045 N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
1049 /* The abort condition when PIO read/write
1052 static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
1055 void __iomem *base = host->base;
1057 if (atomic_read(&host->abort))
1060 if (time_after(jiffies, tmo)) {
1061 data->error = (unsigned int)-ETIMEDOUT;
1062 ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
1067 msdc_reset_hw(host);
1070 ERR_MSG("msdc pio find abort");
1076 Need to add a timeout, or WDT timeout, system reboot.
1078 // pio mode data read/write
1079 static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
1081 struct scatterlist *sg = data->sg;
1082 void __iomem *base = host->base;
1083 u32 num = data->sg_len;
1087 u32 count, size = 0;
1088 u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1089 unsigned long tmo = jiffies + DAT_TIMEOUT;
1091 sdr_set_bits(MSDC_INTEN, wints);
1093 left = sg_dma_len(sg);
1096 if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
1097 count = MSDC_FIFO_THD >> 2;
1099 *ptr++ = msdc_fifo_read32();
1101 left -= MSDC_FIFO_THD;
1102 } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
1104 *ptr++ = msdc_fifo_read32();
1110 *u8ptr++ = msdc_fifo_read8();
1115 if (msdc_pio_abort(host, data, tmo))
1118 size += sg_dma_len(sg);
1119 sg = sg_next(sg); num--;
1122 data->bytes_xfered += size;
1123 N_MSG(FIO, " PIO Read<%d>bytes", size);
1125 sdr_clr_bits(MSDC_INTEN, wints);
1127 ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
1131 /* please make sure won't using PIO when size >= 512
1132 which means, memory card block read/write won't using pio
1133 then don't need to handle the CMD12 when data error.
1135 static int msdc_pio_write(struct msdc_host *host, struct mmc_data *data)
1137 void __iomem *base = host->base;
1138 struct scatterlist *sg = data->sg;
1139 u32 num = data->sg_len;
1143 u32 count, size = 0;
1144 u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1145 unsigned long tmo = jiffies + DAT_TIMEOUT;
1147 sdr_set_bits(MSDC_INTEN, wints);
1149 left = sg_dma_len(sg);
1153 if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1154 count = MSDC_FIFO_SZ >> 2;
1156 msdc_fifo_write32(*ptr); ptr++;
1158 left -= MSDC_FIFO_SZ;
1159 } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1161 msdc_fifo_write32(*ptr); ptr++;
1167 msdc_fifo_write8(*u8ptr); u8ptr++;
1172 if (msdc_pio_abort(host, data, tmo))
1175 size += sg_dma_len(sg);
1176 sg = sg_next(sg); num--;
1179 data->bytes_xfered += size;
1180 N_MSG(FIO, " PIO Write<%d>bytes", size);
1182 ERR_MSG("write pio data->error<%d>", data->error);
1184 sdr_clr_bits(MSDC_INTEN, wints);
1188 #if 0 /* --- by chhung */
1189 // DMA resume / start / stop
1190 static void msdc_dma_resume(struct msdc_host *host)
1192 void __iomem *base = host->base;
1194 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
1196 N_MSG(DMA, "DMA resume");
1198 #endif /* end of --- */
1200 static void msdc_dma_start(struct msdc_host *host)
1202 void __iomem *base = host->base;
1203 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1205 sdr_set_bits(MSDC_INTEN, wints);
1206 //dsb(); /* --- by chhung */
1207 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1209 N_MSG(DMA, "DMA start");
1212 static void msdc_dma_stop(struct msdc_host *host)
1214 void __iomem *base = host->base;
1216 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1218 N_MSG(DMA, "DMA status: 0x%.8x", sdr_read32(MSDC_DMA_CFG));
1219 //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
1221 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
1222 while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1225 //dsb(); /* --- by chhung */
1226 sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
1228 N_MSG(DMA, "DMA stop");
1232 static u8 msdc_dma_calcs(u8 *buf, u32 len)
1236 for (i = 0; i < len; i++)
1238 return 0xFF - (u8)sum;
1241 /* gpd bd setup + dma registers */
1242 static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
1244 void __iomem *base = host->base;
1245 //u32 i, j, num, bdlen, arg, xfersz;
1247 struct scatterlist *sg = dma->sg;
1251 switch (dma->mode) {
1252 case MSDC_MODE_DMA_BASIC:
1253 BUG_ON(host->xfer_size > 65535);
1254 BUG_ON(dma->sglen != 1);
1255 sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
1256 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
1257 //#if defined (CONFIG_RALINK_MT7620)
1258 if (ralink_soc == MT762X_SOC_MT7620A)
1259 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
1260 //#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1262 sdr_write32((void __iomem *)(RALINK_MSDC_BASE + 0xa8), sg_dma_len(sg));
1264 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
1266 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
1268 case MSDC_MODE_DMA_DESC:
1270 /* calculate the required number of gpd */
1271 num = (dma->sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
1279 gpd->hwo = 1; /* hw will clear it */
1281 gpd->chksum = 0; /* need to clear first. */
1282 gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16);
1285 for_each_sg(dma->sg, sg, dma->sglen, j) {
1288 bd[j].ptr = (void *)sg_dma_address(sg);
1289 bd[j].buflen = sg_dma_len(sg);
1291 if (j == dma->sglen - 1)
1292 bd[j].eol = 1; /* the last bd */
1296 bd[j].chksum = 0; /* checksume need to clear first */
1297 bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16);
1300 sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
1301 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
1303 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
1305 sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
1312 N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
1313 N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
1314 N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
1319 static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
1320 struct scatterlist *sg, unsigned int sglen)
1322 BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
1327 if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
1328 dma->mode = MSDC_MODE_DMA_BASIC;
1330 dma->mode = MSDC_MODE_DMA_DESC;
1332 N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen,
1335 msdc_dma_config(host, dma);
1338 /* set block number before send command */
1339 static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
1341 void __iomem *base = host->base;
1343 sdr_write32(SDC_BLK_NUM, blknum);
1346 static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq)
1347 __must_hold(&host->lock)
1349 struct msdc_host *host = mmc_priv(mmc);
1350 struct mmc_command *cmd;
1351 struct mmc_data *data;
1352 void __iomem *base = host->base;
1354 unsigned int left = 0;
1355 int dma = 0, read = 1, send_type = 0;
1360 BUG_ON(mmc == NULL);
1361 BUG_ON(mrq == NULL);
1364 atomic_set(&host->abort, 0);
1367 data = mrq->cmd->data;
1369 #if 0 /* --- by chhung */
1371 N_MSG(OPS, "enable clock!");
1372 msdc_ungate_clock(host->id);
1374 #endif /* end of --- */
1377 send_type = SND_CMD;
1378 if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
1381 BUG_ON(data->blksz > HOST_MAX_BLKSZ);
1382 send_type = SND_DAT;
1385 read = data->flags & MMC_DATA_READ ? 1 : 0;
1387 host->xfer_size = data->blocks * data->blksz;
1388 host->blksz = data->blksz;
1390 /* deside the transfer mode */
1391 if (drv_mode[host->id] == MODE_PIO)
1393 else if (drv_mode[host->id] == MODE_DMA)
1395 else if (drv_mode[host->id] == MODE_SIZE_DEP)
1396 host->dma_xfer = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
1397 dma = host->dma_xfer;
1400 if ((host->timeout_ns != data->timeout_ns) ||
1401 (host->timeout_clks != data->timeout_clks)) {
1402 msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
1406 msdc_set_blknum(host, data->blocks);
1407 //msdc_clr_fifo(); /* no need */
1410 msdc_dma_on(); /* enable DMA mode first!! */
1411 init_completion(&host->xfer_done);
1413 /* start the command first*/
1414 if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
1417 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg,
1419 mmc_get_dma_dir(data));
1420 msdc_dma_setup(host, &host->dma, data->sg,
1423 /* then wait command done */
1424 if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
1427 /* for read, the data coming too fast, then CRC error
1428 start DMA no business with CRC. */
1429 //init_completion(&host->xfer_done);
1430 msdc_dma_start(host);
1432 spin_unlock(&host->lock);
1433 if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
1434 ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
1435 ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
1436 ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
1437 ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
1438 ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
1439 data->error = (unsigned int)-ETIMEDOUT;
1441 msdc_reset_hw(host);
1445 spin_lock(&host->lock);
1446 msdc_dma_stop(host);
1448 /* Firstly: send command */
1449 if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
1452 /* Secondly: pio data phase */
1454 if (msdc_pio_read(host, data))
1457 if (msdc_pio_write(host, data))
1461 /* For write case: make sure contents in fifo flushed to device */
1464 left = msdc_txfifocnt();
1467 if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
1469 /* Fix me: what about if data error, when stop ? how to? */
1473 /* Fix me: read case: need to check CRC error */
1476 /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
1477 For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
1480 /* try not to wait xfer_comp interrupt.
1481 the next command will check SDC_BUSY.
1482 SDC_BUSY means xfer_comp assert
1487 /* Last: stop transfer */
1489 if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0)
1500 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1501 mmc_get_dma_dir(data));
1505 #if 0 // don't stop twice!
1506 if (host->hw->flags & MSDC_REMOVABLE && data->error) {
1507 msdc_abort_data(host);
1508 /* reset in IRQ, stop command has issued. -> No need */
1512 N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>", cmd->opcode, (dma ? "dma" : "pio"),
1513 (read ? "read " : "write"), data->blksz, data->blocks, data->error);
1516 #if 0 /* --- by chhung */
1519 if (send_type == SND_CMD) {
1520 if (cmd->opcode == MMC_SEND_STATUS) {
1521 if ((cmd->resp[0] & CARD_READY_FOR_DATA) || (CARD_CURRENT_STATE(cmd->resp[0]) != 7)) {
1522 N_MSG(OPS, "disable clock, CMD13 IDLE");
1523 msdc_gate_clock(host->id);
1526 N_MSG(OPS, "disable clock, CMD<%d>", cmd->opcode);
1527 msdc_gate_clock(host->id);
1531 N_MSG(OPS, "disable clock!!! Read CMD<%d>", cmd->opcode);
1532 msdc_gate_clock(host->id);
1537 msdc_gate_clock(host->id);
1539 #endif /* end of --- */
1541 if (mrq->cmd->error)
1542 host->error = 0x001;
1543 if (mrq->data && mrq->data->error)
1544 host->error |= 0x010;
1545 if (mrq->stop && mrq->stop->error)
1546 host->error |= 0x100;
1548 //if (host->error) ERR_MSG("host->error<%d>", host->error);
1553 static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
1555 struct mmc_command cmd;
1556 struct mmc_request mrq;
1559 memset(&cmd, 0, sizeof(struct mmc_command));
1560 cmd.opcode = MMC_APP_CMD;
1561 #if 0 /* bug: we meet mmc->card is null when ACMD6 */
1562 cmd.arg = mmc->card->rca << 16;
1564 cmd.arg = host->app_cmd_arg;
1566 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
1568 memset(&mrq, 0, sizeof(struct mmc_request));
1569 mrq.cmd = &cmd; cmd.mrq = &mrq;
1572 err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
1576 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd)
1579 void __iomem *base = host->base;
1580 u32 rsmpl, cur_rsmpl, orig_rsmpl;
1581 u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
1584 /* ==== don't support 3.0 now ====
1586 2: PAD_CMD_RESP_RXDLY[26:22]
1587 ==========================*/
1589 // save the previous tune result
1590 sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
1591 sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
1595 for (rsmpl = 0; rsmpl < 2; rsmpl++) {
1596 /* Lv1: R_SMPL[1] */
1597 cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
1602 sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
1604 if (host->app_cmd) {
1605 result = msdc_app_cmd(host->mmc, host);
1607 ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
1608 host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
1612 result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
1613 ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
1614 (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
1618 if (result != (unsigned int)(-EIO)) {
1619 ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
1624 if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
1625 msdc_abort_data(host);
1629 /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
1630 cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
1631 sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
1632 } while (++rrdly < 32);
1637 /* Support SD2.0 Only */
1638 static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
1640 struct msdc_host *host = mmc_priv(mmc);
1641 void __iomem *base = host->base;
1644 u32 rxdly, cur_rxdly0, cur_rxdly1;
1645 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1646 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1647 u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
1648 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1649 u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
1653 sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
1655 /* Tune Method 2. */
1656 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1660 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1661 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1666 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
1668 if (host->app_cmd) {
1669 result = msdc_app_cmd(host->mmc, host);
1671 ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
1675 result = msdc_do_request(mmc, mrq);
1677 sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG, dcrc); /* RO */
1679 dcrc &= ~SDC_DCRC_STS_NEG;
1680 ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
1681 (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
1682 sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
1684 /* Fix me: result is 0, but dcrc is still exist */
1685 if (result == 0 && dcrc == 0) {
1688 /* there is a case: command timeout, and data phase not processed */
1689 if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
1690 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1691 result, mrq->cmd->error, mrq->data->error);
1697 cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
1698 cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
1700 /* E1 ECO. YD: Reverse */
1701 if (sdr_read32(MSDC_ECO_VER) >= 4) {
1702 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1703 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1704 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1705 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1706 orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
1707 orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
1708 orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
1709 orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
1711 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1712 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1713 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1714 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1715 orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
1716 orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
1717 orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
1718 orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
1722 cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1723 cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1724 cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1725 cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1727 cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1728 cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1729 cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1730 cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1732 cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
1733 cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
1734 cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
1735 cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
1737 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1738 cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
1740 sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
1741 sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
1743 } while (++rxdly < 32);
1749 static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq)
1751 struct msdc_host *host = mmc_priv(mmc);
1752 void __iomem *base = host->base;
1754 u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
1755 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1756 u32 rxdly, cur_rxdly0;
1757 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1758 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1762 // MSDC_IOCON_DDR50CKD need to check. [Fix me]
1764 sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
1765 sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
1767 /* Tune Method 2. just DAT0 */
1768 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1769 cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
1771 /* E1 ECO. YD: Reverse */
1772 if (sdr_read32(MSDC_ECO_VER) >= 4) {
1773 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1774 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1775 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1776 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1778 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1779 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1780 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1781 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1788 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1789 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1794 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
1796 if (host->app_cmd) {
1797 result = msdc_app_cmd(host->mmc, host);
1799 ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
1803 result = msdc_do_request(mmc, mrq);
1805 ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
1806 result == 0 ? "PASS" : "FAIL",
1807 cur_dsmpl, cur_wrrdly, cur_rxdly0);
1812 /* there is a case: command timeout, and data phase not processed */
1813 if (mrq->data->error != (unsigned int)(-EIO)) {
1814 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1815 result, mrq->cmd->error, mrq->data->error);
1820 cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
1821 sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
1822 } while (++wrrdly < 32);
1824 cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
1825 cur_dat1 = orig_dat1;
1826 cur_dat2 = orig_dat2;
1827 cur_dat3 = orig_dat3;
1829 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1830 sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
1831 } while (++rxdly < 32);
1837 static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
1839 struct mmc_command cmd;
1840 struct mmc_request mrq;
1843 memset(&cmd, 0, sizeof(struct mmc_command));
1844 cmd.opcode = MMC_SEND_STATUS;
1846 cmd.arg = mmc->card->rca << 16;
1848 ERR_MSG("cmd13 mmc card is null");
1849 cmd.arg = host->app_cmd_arg;
1851 cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
1853 memset(&mrq, 0, sizeof(struct mmc_request));
1854 mrq.cmd = &cmd; cmd.mrq = &mrq;
1857 err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
1860 *status = cmd.resp[0];
1865 static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
1871 err = msdc_get_card_status(mmc, host, &status);
1875 ERR_MSG("cmd<13> resp<0x%x>", status);
1876 } while (R1_CURRENT_STATE(status) == 7);
1881 /* failed when msdc_do_request */
1882 static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
1884 struct msdc_host *host = mmc_priv(mmc);
1885 struct mmc_command *cmd;
1886 struct mmc_data *data;
1887 //u32 base = host->base;
1891 data = mrq->cmd->data;
1893 read = data->flags & MMC_DATA_READ ? 1 : 0;
1896 if (data->error == (unsigned int)(-EIO))
1897 ret = msdc_tune_bread(mmc, mrq);
1899 ret = msdc_check_busy(mmc, host);
1901 ERR_MSG("XXX cmd13 wait program done failed");
1905 /* Fix me: don't care card status? */
1906 ret = msdc_tune_bwrite(mmc, mrq);
1913 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1915 struct msdc_host *host = mmc_priv(mmc);
1917 //=== for sdio profile ===
1918 #if 0 /* --- by chhung */
1919 u32 old_H32, old_L32, new_H32, new_L32;
1920 u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
1921 #endif /* end of --- */
1924 ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
1928 if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
1929 ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
1930 mrq->cmd->error = (unsigned int)-ENOMEDIUM;
1933 mrq->done(mrq); // call done directly.
1935 mrq->cmd->retries = 0; // please don't retry.
1936 mmc_request_done(mmc, mrq);
1942 /* start to process */
1943 spin_lock(&host->lock);
1944 #if 0 /* --- by chhung */
1945 if (sdio_pro_enable) { //=== for sdio profile ===
1946 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53)
1947 GPT_GetCounter64(&old_L32, &old_H32);
1949 #endif /* end of --- */
1953 if (msdc_do_request(mmc, mrq)) {
1954 if (host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error)
1955 msdc_tune_request(mmc, mrq);
1958 /* ==== when request done, check if app_cmd ==== */
1959 if (mrq->cmd->opcode == MMC_APP_CMD) {
1961 host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
1964 //host->app_cmd_arg = 0;
1969 #if 0 /* --- by chhung */
1970 //=== for sdio profile ===
1971 if (sdio_pro_enable) {
1972 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
1973 GPT_GetCounter64(&new_L32, &new_H32);
1974 ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
1976 opcode = mrq->cmd->opcode;
1977 if (mrq->cmd->data) {
1978 sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
1979 bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0;
1981 bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
1984 if (!mrq->cmd->error)
1985 msdc_performance(opcode, sizes, bRx, ticks);
1988 #endif /* end of --- */
1989 spin_unlock(&host->lock);
1991 mmc_request_done(mmc, mrq);
1996 /* called by ops.set_ios */
1997 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1999 void __iomem *base = host->base;
2000 u32 val = sdr_read32(SDC_CFG);
2002 val &= ~SDC_CFG_BUSWIDTH;
2006 case MMC_BUS_WIDTH_1:
2008 val |= (MSDC_BUS_1BITS << 16);
2010 case MMC_BUS_WIDTH_4:
2011 val |= (MSDC_BUS_4BITS << 16);
2013 case MMC_BUS_WIDTH_8:
2014 val |= (MSDC_BUS_8BITS << 16);
2018 sdr_write32(SDC_CFG, val);
2020 N_MSG(CFG, "Bus Width = %d", width);
2024 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2026 struct msdc_host *host = mmc_priv(mmc);
2027 void __iomem *base = host->base;
2030 #ifdef MT6575_SD_DEBUG
2031 static char *vdd[] = {
2032 "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
2033 "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
2034 "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
2035 "3.40v", "3.50v", "3.60v"
2037 static char *power_mode[] = {
2040 static char *bus_mode[] = {
2041 "UNKNOWN", "OPENDRAIN", "PUSHPULL"
2043 static char *timing[] = {
2044 "LEGACY", "MMC_HS", "SD_HS"
2047 printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
2048 ios->clock / 1000, bus_mode[ios->bus_mode],
2049 (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
2050 power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
2053 msdc_set_buswidth(host, ios->bus_width);
2055 /* Power control ??? */
2056 switch (ios->power_mode) {
2059 // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
2062 host->power_mode = MMC_POWER_ON;
2069 if (host->mclk != ios->clock) {
2070 if (ios->clock > 25000000) {
2071 //if (!(host->hw->flags & MSDC_REMOVABLE)) {
2072 INIT_MSG("SD data latch edge<%d>", MSDC_SMPL_FALLING);
2073 sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL,
2075 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL,
2077 //} /* for tuning debug */
2078 } else { /* default value */
2079 sdr_write32(MSDC_IOCON, 0x00000000);
2080 // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
2081 sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
2082 sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
2083 // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
2084 sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
2086 msdc_set_mclk(host, ddr, ios->clock);
2091 static int msdc_ops_get_ro(struct mmc_host *mmc)
2093 struct msdc_host *host = mmc_priv(mmc);
2094 void __iomem *base = host->base;
2095 unsigned long flags;
2098 if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
2099 spin_lock_irqsave(&host->lock, flags);
2100 ro = (sdr_read32(MSDC_PS) >> 31);
2101 spin_unlock_irqrestore(&host->lock, flags);
2107 static int msdc_ops_get_cd(struct mmc_host *mmc)
2109 struct msdc_host *host = mmc_priv(mmc);
2110 void __iomem *base = host->base;
2111 unsigned long flags;
2114 /* for sdio, MSDC_REMOVABLE not set, always return 1 */
2115 if (!(host->hw->flags & MSDC_REMOVABLE)) {
2116 /* For sdio, read H/W always get<1>, but may timeout some times */
2118 host->card_inserted = 1;
2121 host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
2122 INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
2123 return host->card_inserted;
2127 /* MSDC_CD_PIN_EN set for card */
2128 if (host->hw->flags & MSDC_CD_PIN_EN) {
2129 spin_lock_irqsave(&host->lock, flags);
2131 present = host->card_inserted; /* why not read from H/W: Fix me*/
2135 present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
2137 present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0;
2138 host->card_inserted = present;
2140 spin_unlock_irqrestore(&host->lock, flags);
2142 present = 0; /* TODO? Check DAT3 pins for card detection */
2145 INIT_MSG("ops_get_cd return<%d>", present);
2149 /* ops.enable_sdio_irq */
2150 static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
2152 struct msdc_host *host = mmc_priv(mmc);
2153 struct msdc_hw *hw = host->hw;
2154 void __iomem *base = host->base;
2157 if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
2159 ERR_MSG("XXX "); /* so never enter here */
2160 tmp = sdr_read32(SDC_CFG);
2161 /* FIXME. Need to interrupt gap detection */
2163 tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2165 tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2166 sdr_write32(SDC_CFG, tmp);
2170 static struct mmc_host_ops mt_msdc_ops = {
2171 .request = msdc_ops_request,
2172 .set_ios = msdc_ops_set_ios,
2173 .get_ro = msdc_ops_get_ro,
2174 .get_cd = msdc_ops_get_cd,
2175 .enable_sdio_irq = msdc_ops_enable_sdio_irq,
2178 /*--------------------------------------------------------------------------*/
2179 /* interrupt handler */
2180 /*--------------------------------------------------------------------------*/
2181 static irqreturn_t msdc_irq(int irq, void *dev_id)
2183 struct msdc_host *host = (struct msdc_host *)dev_id;
2184 struct mmc_data *data = host->data;
2185 struct mmc_command *cmd = host->cmd;
2186 void __iomem *base = host->base;
2188 u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
2189 MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
2190 MSDC_INT_ACMD19_DONE;
2191 u32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO;
2193 u32 intsts = sdr_read32(MSDC_INT);
2194 u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
2196 sdr_write32(MSDC_INT, intsts); /* clear interrupts */
2197 /* MSG will cause fatal error */
2199 /* card change interrupt */
2200 if (intsts & MSDC_INT_CDSC) {
2201 if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
2203 IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
2204 schedule_delayed_work(&host->card_delaywork, HZ);
2205 /* tuning when plug card ? */
2208 /* sdio interrupt */
2209 if (intsts & MSDC_INT_SDIOIRQ) {
2210 IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
2211 //mmc_signal_sdio_irq(host->mmc);
2214 /* transfer complete interrupt */
2216 if (inten & MSDC_INT_XFER_COMPL) {
2217 data->bytes_xfered = host->xfer_size;
2218 complete(&host->xfer_done);
2221 if (intsts & datsts) {
2222 /* do basic reset, or stop command will sdc_busy */
2223 msdc_reset_hw(host);
2226 atomic_set(&host->abort, 1); /* For PIO mode exit */
2228 if (intsts & MSDC_INT_DATTMO) {
2229 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
2230 data->error = (unsigned int)-ETIMEDOUT;
2231 } else if (intsts & MSDC_INT_DATCRCERR) {
2232 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
2233 data->error = (unsigned int)-EIO;
2236 //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
2238 complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
2239 /* PIO mode can't do complete, because not init */
2243 /* command interrupts */
2244 if ((cmd != NULL) && (intsts & cmdsts)) {
2245 if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
2246 (intsts & MSDC_INT_ACMD19_DONE)) {
2247 u32 *rsp = &cmd->resp[0];
2249 switch (host->cmd_rsp) {
2253 *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
2254 *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
2256 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2257 if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE))
2258 *rsp = sdr_read32(SDC_ACMD_RESP);
2260 *rsp = sdr_read32(SDC_RESP0);
2263 } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
2264 if (intsts & MSDC_INT_ACMDCRCERR)
2265 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR", cmd->opcode);
2267 IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR", cmd->opcode);
2268 cmd->error = (unsigned int)-EIO;
2269 } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
2270 if (intsts & MSDC_INT_ACMDTMO)
2271 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO", cmd->opcode);
2273 IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO", cmd->opcode);
2274 cmd->error = (unsigned int)-ETIMEDOUT;
2275 msdc_reset_hw(host);
2279 complete(&host->cmd_done);
2282 /* mmc irq interrupts */
2283 if (intsts & MSDC_INT_MMCIRQ)
2284 printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
2286 #ifdef MT6575_SD_DEBUG
2288 /* msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;*/
2289 N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
2296 int_reg->atocmd19done);
2297 N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
2304 N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
2310 int_reg->dmaqempty);
2317 /*--------------------------------------------------------------------------*/
2318 /* platform_driver members */
2319 /*--------------------------------------------------------------------------*/
2320 /* called by msdc_drv_probe/remove */
2321 static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
2323 struct msdc_hw *hw = host->hw;
2324 void __iomem *base = host->base;
2326 /* for sdio, not set */
2327 if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
2328 /* Pull down card detection pin since it is not avaiable */
2330 if (hw->config_gpio_pin)
2331 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
2333 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2334 sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2335 sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
2339 N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
2342 /* card detection circuit relies on the core power so that the core power
2343 * shouldn't be turned off. Here adds a reference count to keep
2344 * the core power alive.
2346 //msdc_vcore_on(host); //did in msdc_init_hw()
2348 if (hw->config_gpio_pin) /* NULL */
2349 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
2351 sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
2352 sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
2353 sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2354 sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
2356 if (hw->config_gpio_pin) /* NULL */
2357 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
2359 sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
2360 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2361 sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2363 /* Here decreases a reference count to core power since card
2364 * detection circuit is shutdown.
2366 //msdc_vcore_off(host);
2370 /* called by msdc_drv_probe */
2371 static void msdc_init_hw(struct msdc_host *host)
2373 void __iomem *base = host->base;
2374 struct msdc_hw *hw = host->hw;
2376 #ifdef MT6575_SD_DEBUG
2377 msdc_reg[host->id] = (struct msdc_regs *)host->base;
2381 #if 0 /* --- by chhung */
2382 msdc_vcore_on(host);
2383 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2384 msdc_select_clksrc(host, hw->clk_src);
2385 enable_clock(PERI_MSDC0_PDN + host->id, "SD");
2387 #endif /* end of --- */
2388 /* Configure to MMC/SD mode */
2389 sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
2392 msdc_reset_hw(host);
2395 /* Disable card detection */
2396 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2398 /* Disable and clear all interrupts */
2399 sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
2400 sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
2403 /* reset tuning parameter */
2404 sdr_write32(MSDC_PAD_CTL0, 0x00090000);
2405 sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
2406 sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
2407 // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
2408 sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
2409 // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
2410 sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
2411 sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
2412 sdr_write32(MSDC_IOCON, 0x00000000);
2413 #if 0 // use MT7620 default value: 0x403c004f
2414 sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
2417 if (sdr_read32(MSDC_ECO_VER) >= 4) {
2418 if (host->id == 1) {
2419 sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
2420 sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
2422 /* internal clock: latch read data */
2423 sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
2428 /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
2429 pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
2430 set when kernel driver wants to use SDIO bus interrupt */
2431 /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
2432 sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
2434 /* disable detect SDIO device interupt function */
2435 sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
2437 /* eneable SMT for glitch filter */
2438 sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
2439 sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
2440 sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
2443 /* set clk, cmd, dat pad driving */
2444 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
2445 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
2446 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4);
2447 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4);
2448 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4);
2449 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4);
2451 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
2452 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
2453 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
2454 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
2455 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
2456 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
2459 /* set sampling edge */
2461 /* write crc timeout detection */
2462 sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
2464 /* Configure to default data timeout */
2465 sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
2467 msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
2469 N_MSG(FUC, "init hardware done!");
2472 /* called by msdc_drv_remove */
2473 static void msdc_deinit_hw(struct msdc_host *host)
2475 void __iomem *base = host->base;
2477 /* Disable and clear all interrupts */
2478 sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
2479 sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
2481 /* Disable card detection */
2482 msdc_enable_cd_irq(host, 0);
2483 // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
2486 /* init gpd and bd list in msdc_drv_probe */
2487 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2489 struct gpd *gpd = dma->gpd;
2490 struct bd *bd = dma->bd;
2493 /* we just support one gpd, but gpd->next must be set for desc
2494 * DMA. That's why we alloc 2 gpd structurs.
2497 memset(gpd, 0, sizeof(struct gpd) * 2);
2499 gpd->bdp = 1; /* hwo, cs, bd pointer */
2500 gpd->ptr = (void *)dma->bd_addr; /* physical address */
2501 gpd->next = (void *)((u32)dma->gpd_addr + sizeof(struct gpd));
2503 memset(bd, 0, sizeof(struct bd) * MAX_BD_NUM);
2504 for (i = 0; i < (MAX_BD_NUM - 1); i++)
2505 bd[i].next = (void *)(dma->bd_addr + sizeof(*bd) * (i + 1));
2508 static int msdc_drv_probe(struct platform_device *pdev)
2510 struct resource *res;
2512 struct mmc_host *mmc;
2513 struct msdc_host *host;
2519 if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en"))
2520 msdc0_hw.flags |= MSDC_WP_PIN_EN;
2522 /* Allocate MMC host for this device */
2523 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2527 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2528 base = devm_ioremap_resource(&pdev->dev, res);
2530 ret = PTR_ERR(base);
2534 /* Set host parameters to mmc */
2535 mmc->ops = &mt_msdc_ops;
2536 mmc->f_min = HOST_MIN_MCLK;
2537 mmc->f_max = HOST_MAX_MCLK;
2538 mmc->ocr_avail = MSDC_OCR_AVAIL;
2540 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
2542 //TODO: read this as bus-width from dt (via mmc_of_parse)
2543 mmc->caps |= MMC_CAP_4_BIT_DATA;
2545 if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
2546 mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
2548 cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
2550 if (of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll"))
2551 mmc->caps |= MMC_CAP_NEEDS_POLL;
2553 /* MMC core transfer sizes tunable parameters */
2554 mmc->max_segs = MAX_HW_SGMTS;
2556 mmc->max_seg_size = MAX_SGMT_SZ;
2557 mmc->max_blk_size = HOST_MAX_BLKSZ;
2558 mmc->max_req_size = MAX_REQ_SZ;
2559 mmc->max_blk_count = mmc->max_req_size;
2561 host = mmc_priv(mmc);
2564 host->id = pdev->id;
2565 if (host->id < 0 || host->id >= 4)
2569 host->irq = platform_get_irq(pdev, 0);
2570 if (host->irq < 0) {
2576 host->mclk = 0; /* mclk: the request clock of mmc sub-system */
2577 host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
2578 host->sclk = 0; /* sclk: the really clock after divition */
2579 host->pm_state = PMSG_RESUME;
2581 host->core_clkon = 0;
2582 host->card_clkon = 0;
2583 host->core_power = 0;
2584 host->power_mode = MMC_POWER_OFF;
2585 // host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
2586 host->timeout_ns = 0;
2587 host->timeout_clks = DEFAULT_DTOC * 65536;
2590 //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
2592 mmc_dev(mmc)->dma_mask = NULL;
2594 /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
2595 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2596 MAX_GPD_NUM * sizeof(struct gpd),
2597 &host->dma.gpd_addr, GFP_KERNEL);
2598 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2599 MAX_BD_NUM * sizeof(struct bd),
2600 &host->dma.bd_addr, GFP_KERNEL);
2601 if (!host->dma.gpd || !host->dma.bd) {
2605 msdc_init_gpd_bd(host, &host->dma);
2607 INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
2608 spin_lock_init(&host->lock);
2611 /* TODO check weather flags 0 is correct, the mtk-sd driver uses
2612 * IRQF_TRIGGER_LOW | IRQF_ONESHOT for flags
2614 * for flags 0 the trigger polarity is determined by the
2615 * device tree, but not the oneshot flag, but maybe it is also
2616 * not needed because the soc could be oneshot safe.
2618 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 0, pdev->name,
2623 platform_set_drvdata(pdev, mmc);
2625 ret = mmc_add_host(mmc);
2629 /* Config card detection pin and enable interrupts */
2630 if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
2631 msdc_enable_cd_irq(host, 1);
2633 msdc_enable_cd_irq(host, 0);
2639 platform_set_drvdata(pdev, NULL);
2640 msdc_deinit_hw(host);
2641 cancel_delayed_work_sync(&host->card_delaywork);
2645 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2646 host->dma.gpd, host->dma.gpd_addr);
2648 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2649 host->dma.bd, host->dma.bd_addr);
2656 /* 4 device share one driver, using "drvdata" to show difference */
2657 static int msdc_drv_remove(struct platform_device *pdev)
2659 struct mmc_host *mmc;
2660 struct msdc_host *host;
2662 mmc = platform_get_drvdata(pdev);
2665 host = mmc_priv(mmc);
2668 ERR_MSG("removed !!!");
2670 platform_set_drvdata(pdev, NULL);
2671 mmc_remove_host(host->mmc);
2672 msdc_deinit_hw(host);
2674 cancel_delayed_work_sync(&host->card_delaywork);
2676 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2677 host->dma.gpd, host->dma.gpd_addr);
2678 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2679 host->dma.bd, host->dma.bd_addr);
2681 mmc_free_host(host->mmc);
2686 /* Fix me: Power Flow */
2689 static void msdc_drv_pm(struct platform_device *pdev, pm_message_t state)
2691 struct mmc_host *mmc = platform_get_drvdata(pdev);
2693 struct msdc_host *host = mmc_priv(mmc);
2694 msdc_pm(state, (void *)host);
2698 static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
2700 if (state.event == PM_EVENT_SUSPEND)
2701 msdc_drv_pm(pdev, state);
2705 static int msdc_drv_resume(struct platform_device *pdev)
2707 struct pm_message state;
2709 state.event = PM_EVENT_RESUME;
2710 msdc_drv_pm(pdev, state);
2715 static const struct of_device_id mt7620_sdhci_match[] = {
2716 { .compatible = "ralink,mt7620-sdhci" },
2719 MODULE_DEVICE_TABLE(of, mt7620_sdhci_match);
2721 static struct platform_driver mt_msdc_driver = {
2722 .probe = msdc_drv_probe,
2723 .remove = msdc_drv_remove,
2725 .suspend = msdc_drv_suspend,
2726 .resume = msdc_drv_resume,
2730 .of_match_table = mt7620_sdhci_match,
2734 /*--------------------------------------------------------------------------*/
2735 /* module init/exit */
2736 /*--------------------------------------------------------------------------*/
2737 static int __init mt_msdc_init(void)
2742 // Set the pins for sdxc to sdxc mode
2743 //FIXME: this should be done by pinctl and not by the sd driver
2744 reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18);
2745 sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60), reg);
2747 ret = platform_driver_register(&mt_msdc_driver);
2749 printk(KERN_ERR DRV_NAME ": Can't register driver");
2753 #if defined(MT6575_SD_DEBUG)
2754 msdc_debug_proc_init();
2759 static void __exit mt_msdc_exit(void)
2761 platform_driver_unregister(&mt_msdc_driver);
2764 module_init(mt_msdc_init);
2765 module_exit(mt_msdc_exit);
2766 MODULE_LICENSE("GPL");
2767 MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
2768 MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");