drivers/staging/mrst/drv/psb_intel_display.c

   1 /*
   2  * Copyright Â© 2006-2007 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  * Authors:
  18  *      Eric Anholt <eric@anholt.net>
  19  */
  20
  21 #include <linux/i2c.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include <drm/drmP.h>
  25 #include "psb_fb.h"
  26 #include "psb_drv.h"
  27 #include "psb_intel_drv.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_intel_display.h"
  30 #include "psb_page_flip.h"
  31 #include "psb_powermgmt.h"
  32 #include "mdfld_output.h"
  33
  34 static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  35                                 struct drm_framebuffer *old_fb);
  36 static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
  37                               struct drm_display_mode *mode,
  38                               struct drm_display_mode *adjusted_mode,
  39                               int x, int y,
  40                               struct drm_framebuffer *old_fb);
  41 static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode);
  42
  43 struct psb_intel_clock_t {
  44         /* given values */
  45         int n;
  46         int m1, m2;
  47         int p1, p2;
  48         /* derived values */
  49         int dot;
  50         int vco;
  51         int m;
  52         int p;
  53 };
  54
  55 struct psb_intel_range_t {
  56         int min, max;
  57 };
  58
  59 /**
  60  * Returns whether any output on the specified pipe is of the specified type
  61  */
  62 bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type)
  63 {
  64         struct drm_device *dev = crtc->dev;
  65         struct drm_mode_config *mode_config = &dev->mode_config;
  66         struct drm_connector *l_entry;
  67
  68         list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  69                 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
  70                         struct psb_intel_output *psb_intel_output =
  71                             to_psb_intel_output(l_entry);
  72                         if (psb_intel_output->type == type)
  73                                 return true;
  74                 }
  75         }
  76         return false;
  77 }
  78
  79 void psb_intel_wait_for_vblank(struct drm_device *dev)
  80 {
  81         /* Wait for 20ms, i.e. one cycle at 50hz. */
  82         mdelay(20);
  83 }
  84
  85 static void psb_intel_crtc_prepare(struct drm_crtc *crtc)
  86 {
  87         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  88         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  89 }
  90
  91 static void psb_intel_crtc_commit(struct drm_crtc *crtc)
  92 {
  93         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  94         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  95 }
  96
  97 void psb_intel_encoder_prepare(struct drm_encoder *encoder)
  98 {
  99         struct drm_encoder_helper_funcs *encoder_funcs =
 100             encoder->helper_private;
 101         /* lvds has its own version of prepare see psb_intel_lvds_prepare */
 102         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 103 }
 104
 105 void psb_intel_encoder_commit(struct drm_encoder *encoder)
 106 {
 107         struct drm_encoder_helper_funcs *encoder_funcs =
 108             encoder->helper_private;
 109         /* lvds has its own version of commit see psb_intel_lvds_commit */
 110         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 111 }
 112
 113 static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
 114                                   struct drm_display_mode *mode,
 115                                   struct drm_display_mode *adjusted_mode)
 116 {
 117         return true;
 118 }
 119
 120
 121 /**
 122  * Return the pipe currently connected to the panel fitter,
 123  * or -1 if the panel fitter is not present or not in use
 124  */
 125 int psb_intel_panel_fitter_pipe(struct drm_device *dev)
 126 {
 127         u32 pfit_control;
 128
 129         /* i830 doesn't have a panel fitter */
 130         if (IS_I830(dev))
 131                 return -1;
 132
 133         pfit_control = REG_READ(PFIT_CONTROL);
 134
 135         /* See if the panel fitter is in use */
 136         if ((pfit_control & PFIT_ENABLE) == 0)
 137                 return -1;
 138
 139         /* 965 can place panel fitter on either pipe */
 140         return (pfit_control >> 29) & 0x3;
 141 }
 142
 143 /** Loads the palette/gamma unit for the CRTC with the prepared values */
 144 void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
 145 {
 146         struct drm_device *dev = crtc->dev;
 147         struct drm_psb_private *dev_priv =
 148                                 (struct drm_psb_private *)dev->dev_private;
 149         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 150         int palreg;
 151         int i;
 152
 153         /* The clocks have to be on to load the palette. */
 154         if (!crtc->enabled)
 155                 return;
 156
 157         palreg = PSB_PALETTE(psb_intel_crtc->pipe);
 158
 159         if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
 160                 for (i = 0; i < 256; i++) {
 161                         REG_WRITE(palreg + 4 * i,
 162                                   ((psb_intel_crtc->lut_r[i] +
 163                                   psb_intel_crtc->lut_adj[i]) << 16) |
 164                                   ((psb_intel_crtc->lut_g[i] +
 165                                   psb_intel_crtc->lut_adj[i]) << 8) |
 166                                   (psb_intel_crtc->lut_b[i] +
 167                                   psb_intel_crtc->lut_adj[i]));
 168                 }
 169                 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 170         } else {
 171                 for (i = 0; i < 256; i++) {
 172                         dev_priv->pipe_regs[0].palette[i] =
 173                                   ((psb_intel_crtc->lut_r[i] +
 174                                   psb_intel_crtc->lut_adj[i]) << 16) |
 175                                   ((psb_intel_crtc->lut_g[i] +
 176                                   psb_intel_crtc->lut_adj[i]) << 8) |
 177                                   (psb_intel_crtc->lut_b[i] +
 178                                   psb_intel_crtc->lut_adj[i]);
 179                 }
 180
 181         }
 182 }
 183
 184 /**
 185  * Save HW states of giving crtc
 186  */
 187 static void psb_intel_crtc_save(struct drm_crtc *crtc)
 188 {
 189         struct drm_device *dev = crtc->dev;
 190         /* struct drm_psb_private *dev_priv =
 191                         (struct drm_psb_private *)dev->dev_private; */
 192         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 193         struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
 194         int pipe = psb_intel_crtc->pipe;
 195         int pipeA = (psb_intel_crtc->pipe == 0);
 196         uint32_t paletteReg;
 197         int i;
 198
 199         DRM_DEBUG("\n");
 200
 201         if (!crtc_state) {
 202                 DRM_DEBUG("No CRTC state found\n");
 203                 return;
 204         }
 205
 206         crtc_state->saveDSPCNTR = REG_READ(PSB_DSPCNTR(pipe));
 207         crtc_state->savePIPECONF = REG_READ(PSB_PIPECONF(pipe));
 208         crtc_state->savePIPESRC = REG_READ(PSB_PIPESRC(pipe));
 209         crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
 210         crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
 211         crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
 212         crtc_state->saveHTOTAL = REG_READ(PSB_HTOTAL(pipe));
 213         crtc_state->saveHBLANK = REG_READ(PSB_HBLANK(pipe));
 214         crtc_state->saveHSYNC = REG_READ(PSB_HSYNC(pipe));
 215         crtc_state->saveVTOTAL = REG_READ(PSB_VTOTAL(pipe));
 216         crtc_state->saveVBLANK = REG_READ(PSB_VBLANK(pipe));
 217         crtc_state->saveVSYNC = REG_READ(PSB_VSYNC(pipe));
 218         crtc_state->saveDSPSTRIDE = REG_READ(PSB_DSPSTRIDE(pipe));
 219
 220         /*NOTE: DSPSIZE DSPPOS only for psb*/
 221         crtc_state->saveDSPSIZE = REG_READ(PSB_DSPSIZE(pipe));
 222         crtc_state->saveDSPPOS = REG_READ(PSB_DSPPOS(pipe));
 223
 224         crtc_state->saveDSPBASE = REG_READ(PSB_DSPBASE(pipe));
 225
 226         DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
 227                         crtc_state->saveDSPCNTR,
 228                         crtc_state->savePIPECONF,
 229                         crtc_state->savePIPESRC,
 230                         crtc_state->saveFP0,
 231                         crtc_state->saveFP1,
 232                         crtc_state->saveDPLL,
 233                         crtc_state->saveHTOTAL,
 234                         crtc_state->saveHBLANK,
 235                         crtc_state->saveHSYNC,
 236                         crtc_state->saveVTOTAL,
 237                         crtc_state->saveVBLANK,
 238                         crtc_state->saveVSYNC,
 239                         crtc_state->saveDSPSTRIDE,
 240                         crtc_state->saveDSPSIZE,
 241                         crtc_state->saveDSPPOS,
 242                         crtc_state->saveDSPBASE
 243                 );
 244
 245         paletteReg = PSB_PALETTE(pipe);
 246         for (i = 0; i < 256; ++i)
 247                 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
 248 }
 249
 250 /**
 251  * Restore HW states of giving crtc
 252  */
 253 static void psb_intel_crtc_restore(struct drm_crtc *crtc)
 254 {
 255         struct drm_device *dev = crtc->dev;
 256         /* struct drm_psb_private * dev_priv =
 257                                 (struct drm_psb_private *)dev->dev_private; */
 258         struct psb_intel_crtc *psb_intel_crtc =  to_psb_intel_crtc(crtc);
 259         struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
 260         /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
 261         int pipe = psb_intel_crtc->pipe;
 262         int pipeA = (psb_intel_crtc->pipe == 0);
 263         uint32_t paletteReg;
 264         int i;
 265
 266         DRM_DEBUG("\n");
 267
 268         if (!crtc_state) {
 269                 DRM_DEBUG("No crtc state\n");
 270                 return;
 271         }
 272
 273         DRM_DEBUG(
 274                 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
 275                 REG_READ(PSB_DSPCNTR(pipe)),
 276                 REG_READ(PSB_PIPECONF(pipe)),
 277                 REG_READ(PSB_PIPESRC(pipe)),
 278                 REG_READ(pipeA ? FPA0 : FPB0),
 279                 REG_READ(pipeA ? FPA1 : FPB1),
 280                 REG_READ(pipeA ? DPLL_A : DPLL_B),
 281                 REG_READ(PSB_HTOTAL(pipe)),
 282                 REG_READ(PSB_HBLANK(pipe)),
 283                 REG_READ(PSB_HSYNC(pipe)),
 284                 REG_READ(PSB_VTOTAL(pipe)),
 285                 REG_READ(PSB_VBLANK(pipe)),
 286                 REG_READ(PSB_VSYNC(pipe)),
 287                 REG_READ(PSB_DSPSTRIDE(pipe)),
 288                 REG_READ(PSB_DSPSIZE(pipe)),
 289                 REG_READ(PSB_DSPPOS(pipe)),
 290                 REG_READ(PSB_DSPBASE(pipe))
 291                 );
 292
 293         DRM_DEBUG(
 294                 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
 295                 crtc_state->saveDSPCNTR,
 296                 crtc_state->savePIPECONF,
 297                 crtc_state->savePIPESRC,
 298                 crtc_state->saveFP0,
 299                 crtc_state->saveFP1,
 300                 crtc_state->saveDPLL,
 301                 crtc_state->saveHTOTAL,
 302                 crtc_state->saveHBLANK,
 303                 crtc_state->saveHSYNC,
 304                 crtc_state->saveVTOTAL,
 305                 crtc_state->saveVBLANK,
 306                 crtc_state->saveVSYNC,
 307                 crtc_state->saveDSPSTRIDE,
 308                 crtc_state->saveDSPSIZE,
 309                 crtc_state->saveDSPPOS,
 310                 crtc_state->saveDSPBASE
 311                 );
 312
 313         if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
 314                 REG_WRITE(pipeA ? DPLL_A : DPLL_B,
 315                         crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
 316                 REG_READ(pipeA ? DPLL_A : DPLL_B);
 317                 DRM_DEBUG("write dpll: %x\n",
 318                                 REG_READ(pipeA ? DPLL_A : DPLL_B));
 319                 udelay(150);
 320         }
 321
 322         REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
 323         REG_READ(pipeA ? FPA0 : FPB0);
 324
 325         REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
 326         REG_READ(pipeA ? FPA1 : FPB1);
 327
 328         REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
 329         REG_READ(pipeA ? DPLL_A : DPLL_B);
 330         udelay(150);
 331
 332         REG_WRITE(PSB_HTOTAL(pipe), crtc_state->saveHTOTAL);
 333         REG_WRITE(PSB_HBLANK(pipe), crtc_state->saveHBLANK);
 334         REG_WRITE(PSB_HSYNC(pipe), crtc_state->saveHSYNC);
 335         REG_WRITE(PSB_VTOTAL(pipe), crtc_state->saveVTOTAL);
 336         REG_WRITE(PSB_VBLANK(pipe), crtc_state->saveVBLANK);
 337         REG_WRITE(PSB_VSYNC(pipe), crtc_state->saveVSYNC);
 338         REG_WRITE(PSB_DSPSTRIDE(pipe), crtc_state->saveDSPSTRIDE);
 339
 340         REG_WRITE(PSB_DSPSIZE(pipe), crtc_state->saveDSPSIZE);
 341         REG_WRITE(PSB_DSPPOS(pipe), crtc_state->saveDSPPOS);
 342
 343         REG_WRITE(PSB_PIPESRC(pipe), crtc_state->savePIPESRC);
 344         REG_WRITE(PSB_DSPBASE(pipe), crtc_state->saveDSPBASE);
 345         REG_WRITE(PSB_PIPECONF(pipe), crtc_state->savePIPECONF);
 346
 347         psb_intel_wait_for_vblank(dev);
 348
 349         REG_WRITE(PSB_DSPCNTR(pipe), crtc_state->saveDSPCNTR);
 350         REG_WRITE(PSB_DSPBASE(pipe), crtc_state->saveDSPBASE);
 351
 352         psb_intel_wait_for_vblank(dev);
 353
 354         paletteReg = PSB_PALETTE(pipe);
 355         for (i = 0; i < 256; ++i)
 356                 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
 357 }
 358
 359 /* FIXME: Start using the start and size parameters */
 360 static void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 361                                 u16 *green, u16 *blue, uint32_t start,
 362                                 uint32_t size)
 363 {
 364         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 365         int i;
 366
 367         if (size != 256)
 368                 return;
 369
 370         for (i = 0; i < 256; i++) {
 371                 psb_intel_crtc->lut_r[i] = red[i] >> 8;
 372                 psb_intel_crtc->lut_g[i] = green[i] >> 8;
 373                 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
 374         }
 375
 376         psb_intel_crtc_load_lut(crtc);
 377 }
 378
 379 static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
 380 {
 381         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 382
 383         psb_page_flip_crtc_fini(psb_intel_crtc);
 384         kfree(psb_intel_crtc->crtc_state);
 385         drm_crtc_cleanup(crtc);
 386         kfree(psb_intel_crtc);
 387 }
 388
 389 static const struct drm_crtc_helper_funcs mdfld_helper_funcs;
 390 static const struct drm_crtc_funcs mdfld_intel_crtc_funcs;
 391
 392 /*
 393  * Set the default value of cursor control and base register
 394  * to zero. This is a workaround for h/w defect on oaktrail
 395  */
 396 static void psb_intel_cursor_init(struct drm_device *dev, int pipe)
 397 {
 398         uint32_t control;
 399         uint32_t base;
 400
 401         switch (pipe) {
 402         case 0:
 403                 control = CURACNTR;
 404                 base = CURABASE;
 405                 break;
 406         case 1:
 407                 control = CURBCNTR;
 408                 base = CURBBASE;
 409                 break;
 410         case 2:
 411                 control = CURCCNTR;
 412                 base = CURCBASE;
 413                 break;
 414         default:
 415                 return;
 416         }
 417
 418         REG_WRITE(control, 0);
 419         REG_WRITE(base, 0);
 420 }
 421
 422 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
 423                      struct psb_intel_mode_device *mode_dev)
 424 {
 425         struct drm_psb_private *dev_priv = dev->dev_private;
 426         struct psb_intel_crtc *psb_intel_crtc;
 427         int i;
 428         uint16_t *r_base, *g_base, *b_base;
 429
 430         PSB_DEBUG_ENTRY("\n");
 431
 432         /* We allocate a extra array of drm_connector pointers
 433          * for fbdev after the crtc */
 434         psb_intel_crtc =
 435             kzalloc(sizeof(struct psb_intel_crtc) +
 436                     (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
 437                     GFP_KERNEL);
 438         if (psb_intel_crtc == NULL)
 439                 return;
 440
 441         psb_intel_crtc->crtc_state =
 442                 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
 443         if (!psb_intel_crtc->crtc_state) {
 444                 DRM_INFO("Crtc state error: No memory\n");
 445                 kfree(psb_intel_crtc);
 446                 return;
 447         }
 448
 449         drm_crtc_init(dev, &psb_intel_crtc->base, &mdfld_intel_crtc_funcs);
 450
 451         drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256);
 452         psb_intel_crtc->pipe = pipe;
 453         psb_intel_crtc->plane = pipe;
 454
 455         r_base = psb_intel_crtc->base.gamma_store;
 456         g_base = r_base + 256;
 457         b_base = g_base + 256;
 458         for (i = 0; i < 256; i++) {
 459                 psb_intel_crtc->lut_r[i] = i;
 460                 psb_intel_crtc->lut_g[i] = i;
 461                 psb_intel_crtc->lut_b[i] = i;
 462                 r_base[i] = i << 8;
 463                 g_base[i] = i << 8;
 464                 b_base[i] = i << 8;
 465
 466                 psb_intel_crtc->lut_adj[i] = 0;
 467         }
 468
 469         psb_intel_crtc->mode_dev = mode_dev;
 470         psb_intel_crtc->cursor_addr = 0;
 471
 472         drm_crtc_helper_add(&psb_intel_crtc->base, &mdfld_helper_funcs);
 473
 474         /* Setup the array of drm_connector pointer array */
 475         psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;
 476         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
 477                dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL);
 478         dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] = &psb_intel_crtc->base;
 479         dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] = &psb_intel_crtc->base;
 480         psb_intel_crtc->mode_set.connectors =
 481             (struct drm_connector **) (psb_intel_crtc + 1);
 482         psb_intel_crtc->mode_set.num_connectors = 0;
 483
 484         psb_intel_cursor_init(dev, pipe);
 485
 486         psb_page_flip_crtc_init(psb_intel_crtc);
 487
 488         init_waitqueue_head(&psb_intel_crtc->vbl_wait);
 489 }
 490
 491 int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 492                                 struct drm_file *file_priv)
 493 {
 494         struct drm_psb_private *dev_priv = dev->dev_private;
 495         struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data;
 496         struct drm_mode_object *drmmode_obj;
 497         struct psb_intel_crtc *crtc;
 498
 499         if (!dev_priv) {
 500                 DRM_ERROR("called with no initialization\n");
 501                 return -EINVAL;
 502         }
 503
 504         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
 505                         DRM_MODE_OBJECT_CRTC);
 506
 507         if (!drmmode_obj) {
 508                 DRM_ERROR("no such CRTC id\n");
 509                 return -EINVAL;
 510         }
 511
 512         crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj));
 513         pipe_from_crtc_id->pipe = crtc->pipe;
 514
 515         return 0;
 516 }
 517
 518 int psb_intel_connector_clones(struct drm_device *dev, int type_mask)
 519 {
 520         int index_mask = 0;
 521         struct drm_connector *connector;
 522         int entry = 0;
 523
 524         list_for_each_entry(connector, &dev->mode_config.connector_list,
 525                             head) {
 526                 struct psb_intel_output *psb_intel_output =
 527                     to_psb_intel_output(connector);
 528                 if (type_mask & (1 << psb_intel_output->type))
 529                         index_mask |= (1 << entry);
 530                 entry++;
 531         }
 532         return index_mask;
 533 }
 534
 535 /* current intel driver doesn't take advantage of encoders
 536    always give back the encoder for the connector
 537 */
 538 struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector)
 539 {
 540         struct psb_intel_output *psb_intel_output =
 541                                         to_psb_intel_output(connector);
 542
 543         return &psb_intel_output->enc;
 544 }
 545
 546 struct mrst_limit_t {
 547         struct psb_intel_range_t dot, m, p1;
 548 };
 549
 550 struct mrst_clock_t {
 551         /* derived values */
 552         int dot;
 553         int m;
 554         int p1;
 555 };
 556
 557 #define COUNT_MAX 0x10000000
 558
 559 static const struct drm_crtc_helper_funcs mdfld_helper_funcs = {
 560         .dpms = mdfld_crtc_dpms,
 561         .mode_fixup = psb_intel_crtc_mode_fixup,
 562         .mode_set = mdfld_crtc_mode_set,
 563         .mode_set_base = mdfld__intel_pipe_set_base,
 564         .prepare = psb_intel_crtc_prepare,
 565         .commit = psb_intel_crtc_commit,
 566 };
 567
 568 #include "mdfld_dsi_dbi.h"
 569 #include "mdfld_dsi_dpi.h"
 570
 571 #ifdef CONFIG_MDFLD_DSI_DPU
 572 #include "mdfld_dsi_dbi_dpu.h"
 573 #endif
 574
 575 #include <linux/pm_runtime.h>
 576
 577 void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
 578 {
 579         int count, temp;
 580         u32 pipeconf_reg = PSB_PIPECONF(pipe);
 581
 582         /* FIXME JLIU7_PO */
 583         psb_intel_wait_for_vblank(dev);
 584         return;
 585
 586         /* Wait for for the pipe disable to take effect. */
 587         for (count = 0; count < COUNT_MAX; count++) {
 588                 temp = REG_READ(pipeconf_reg);
 589                 if ((temp & PIPEACONF_PIPE_STATE) == 0)
 590                         break;
 591         }
 592
 593         PSB_DEBUG_ENTRY("cout = %d. \n", count);
 594 }
 595
 596 void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)
 597 {
 598         int count, temp;
 599         u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
 600
 601         switch (pipe) {
 602         case 0:
 603                 break;
 604         case 1:
 605                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
 606                 break;
 607         case 2:
 608                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
 609                 break;
 610         default:
 611                 DRM_ERROR("Illegal Pipe Number. \n");
 612                 return;
 613         }
 614
 615         /* FIXME JLIU7_PO */
 616         psb_intel_wait_for_vblank(dev);
 617         return;
 618
 619         /* Wait for for the pipe enable to take effect. */
 620         for (count = 0; count < COUNT_MAX; count++) {
 621                 temp = REG_READ(pipeconf_reg);
 622                 if ((temp & PIPEACONF_PIPE_STATE) == 1)
 623                         break;
 624         }
 625
 626         PSB_DEBUG_ENTRY("cout = %d. \n", count);
 627 }
 628
 629
 630 static int mdfld_intel_crtc_cursor_set(struct drm_crtc *crtc,
 631                                  struct drm_file *file_priv,
 632                                  uint32_t handle,
 633                                  uint32_t width, uint32_t height)
 634 {
 635         struct drm_device *dev = crtc->dev;
 636         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 637         struct psb_intel_mode_device *mode_dev = psb_intel_crtc->mode_dev;
 638         int pipe = psb_intel_crtc->pipe;
 639         uint32_t control = CURACNTR;
 640         uint32_t base = CURABASE;
 641         uint32_t temp;
 642         size_t addr = 0;
 643         uint32_t page_offset;
 644         size_t size;
 645         void *bo;
 646         int ret;
 647
 648         DRM_DEBUG("\n");
 649
 650         switch (pipe) {
 651         case 0:
 652                 break;
 653         case 1:
 654                 control = CURBCNTR;
 655                 base = CURBBASE;
 656                 break;
 657         case 2:
 658                 control = CURCCNTR;
 659                 base = CURCBASE;
 660                 break;
 661         default:
 662                 DRM_ERROR("Illegal Pipe Number. \n");
 663                 return -EINVAL;
 664         }
 665
 666 #if 1 /* FIXME_JLIU7 can't enalbe cursorB/C HW issue. need to remove after HW fix */
 667         if (pipe != 0)
 668                 return 0;
 669 #endif
 670         /* if we want to turn of the cursor ignore width and height */
 671         if (!handle) {
 672                 DRM_DEBUG("cursor off\n");
 673                 /* turn off the cursor */
 674                 temp = 0;
 675                 temp |= CURSOR_MODE_DISABLE;
 676
 677                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
 678                         REG_WRITE(control, temp);
 679                         REG_WRITE(base, 0);
 680                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 681                 }
 682
 683                 /* unpin the old bo */
 684                 if (psb_intel_crtc->cursor_bo) {
 685                         mode_dev->bo_unpin_for_scanout(dev,
 686                                                        psb_intel_crtc->
 687                                                        cursor_bo);
 688                         mode_dev->bo_unref(dev, psb_intel_crtc->cursor_bo);
 689                         psb_intel_crtc->cursor_bo = NULL;
 690                 }
 691                 return 0;
 692         }
 693
 694         /* Currently we only support 64x64 cursors */
 695         if (width != 64 || height != 64) {
 696                 DRM_ERROR("we currently only support 64x64 cursors\n");
 697                 return -EINVAL;
 698         }
 699
 700         bo = mode_dev->bo_from_handle(dev, file_priv, handle);
 701         if (!bo)
 702                 return -ENOENT;
 703
 704         ret = mode_dev->bo_pin_for_scanout(dev, bo);
 705         if (ret)
 706                 goto unref_bo;
 707         size = mode_dev->bo_size(dev, bo);
 708         if (size < width * height * 4) {
 709                 DRM_ERROR("buffer is to small\n");
 710                 ret = -ENOMEM;
 711                 goto unpin_bo;
 712         }
 713
 714         /*insert this bo into gtt*/
 715 //        DRM_INFO("%s: map meminfo for hw cursor. handle %x, pipe = %d \n", __FUNCTION__, handle, pipe);
 716
 717         ret = psb_gtt_map_meminfo(dev, bo, &page_offset);
 718         if(ret) {
 719                 DRM_ERROR("Can not map meminfo to GTT. handle 0x%x\n", handle);
 720                 goto unpin_bo;
 721         }
 722
 723         addr = page_offset << PAGE_SHIFT;
 724
 725         psb_intel_crtc->cursor_addr = addr;
 726
 727         temp = 0;
 728         /* set the pipe for the cursor */
 729         temp |= (pipe << 28);
 730         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
 731
 732         if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
 733                 REG_WRITE(control, temp);
 734                 REG_WRITE(base, addr);
 735                 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 736         }
 737
 738         /* unpin the old bo */
 739         if (psb_intel_crtc->cursor_bo && psb_intel_crtc->cursor_bo != bo) {
 740                 mode_dev->bo_unpin_for_scanout(dev, psb_intel_crtc->cursor_bo);
 741                 mode_dev->bo_unref(dev, psb_intel_crtc->cursor_bo);
 742                 psb_intel_crtc->cursor_bo = bo;
 743         }
 744
 745         return 0;
 746
 747  unpin_bo:
 748         mode_dev->bo_unpin_for_scanout(dev, bo);
 749  unref_bo:
 750         mode_dev->bo_unref(dev, bo);
 751  out:
 752         return ret;
 753 }
 754
 755 static int mdfld_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 756 {
 757         struct drm_device *dev = crtc->dev;
 758 #ifndef CONFIG_MDFLD_DSI_DPU
 759         struct drm_psb_private * dev_priv = (struct drm_psb_private *)dev->dev_private;
 760 #else
 761         struct psb_drm_dpu_rect rect;
 762 #endif
 763         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 764         int pipe = psb_intel_crtc->pipe;
 765         uint32_t pos = CURAPOS;
 766         uint32_t base = CURABASE;
 767         uint32_t temp = 0;
 768         uint32_t addr;
 769
 770         switch (pipe) {
 771         case 0:
 772 #ifndef CONFIG_MDFLD_DSI_DPU
 773                 if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_0))
 774                         mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_0, 0, 0);
 775 #else /*CONFIG_MDFLD_DSI_DPU*/
 776                 rect.x = x;
 777                 rect.y = y;
 778
 779                 mdfld_dbi_dpu_report_damage(dev, MDFLD_CURSORA, &rect);
 780                 mdfld_dpu_exit_dsr(dev);
 781 #endif
 782                 break;
 783         case 1:
 784                 pos = CURBPOS;
 785                 base = CURBBASE;
 786                 break;
 787         case 2:
 788 #ifndef CONFIG_MDFLD_DSI_DPU
 789                 if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_2))
 790                         mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_2, 0, 0);
 791 #else /*CONFIG_MDFLD_DSI_DPU*/
 792                 mdfld_dbi_dpu_report_damage(dev, MDFLD_CURSORC, &rect);
 793                 mdfld_dpu_exit_dsr(dev);
 794 #endif
 795                 pos = CURCPOS;
 796                 base = CURCBASE;
 797                 break;
 798         default:
 799                 DRM_ERROR("Illegal Pipe Number. \n");
 800                 return -EINVAL;
 801         }
 802
 803 #if 1 /* FIXME_JLIU7 can't enalbe cursorB/C HW issue. need to remove after HW fix */
 804         if (pipe != 0)
 805                 return 0;
 806 #endif
 807         if (x < 0) {
 808                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
 809                 x = -x;
 810         }
 811         if (y < 0) {
 812                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
 813                 y = -y;
 814         }
 815
 816         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
 817         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
 818
 819         addr = psb_intel_crtc->cursor_addr;
 820
 821         if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) {
 822                 REG_WRITE(pos, temp);
 823                 REG_WRITE(base, addr);
 824                 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 825         }
 826
 827         return 0;
 828 }
 829
 830 static const struct drm_crtc_funcs mdfld_intel_crtc_funcs = {
 831         .save = psb_intel_crtc_save,
 832         .restore = psb_intel_crtc_restore,
 833         .cursor_set = mdfld_intel_crtc_cursor_set,
 834         .cursor_move = mdfld_intel_crtc_cursor_move,
 835         .gamma_set = psb_intel_crtc_gamma_set,
 836         .set_config = drm_crtc_helper_set_config,
 837         .destroy = psb_intel_crtc_destroy,
 838         .page_flip = psb_intel_crtc_page_flip,
 839 };
 840
 841 static struct drm_device globle_dev;
 842
 843 void mdfld__intel_plane_set_alpha(int enable)
 844 {
 845         struct drm_device *dev = &globle_dev;
 846         int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
 847         u32 dspcntr;
 848
 849         dspcntr = REG_READ(dspcntr_reg);
 850
 851         if (enable) {
 852                 dspcntr &= ~DISPPLANE_32BPP_NO_ALPHA;
 853                 dspcntr |= DISPPLANE_32BPP;
 854         } else {
 855                 dspcntr &= ~DISPPLANE_32BPP;
 856                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 857         }
 858
 859         REG_WRITE(dspcntr_reg, dspcntr);
 860 }
 861
 862 static int check_fb(const struct drm_framebuffer *fb)
 863 {
 864         if (!fb)
 865                 return 0;
 866
 867         switch (fb->bits_per_pixel) {
 868         case 8:
 869         case 16:
 870         case 24:
 871         case 32:
 872                 return 0;
 873         default:
 874                 DRM_ERROR("Unknown color depth\n");
 875                 return -EINVAL;
 876         }
 877 }
 878
 879 static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 880                                 struct drm_framebuffer *old_fb)
 881 {
 882         struct drm_device *dev = crtc->dev;
 883         /* struct drm_i915_master_private *master_priv; */
 884         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 885         struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
 886         int pipe = psb_intel_crtc->pipe;
 887         unsigned long Start, Offset;
 888         int dsplinoff = PSB_DSPLINOFF(PSB_PIPE_A);
 889         int dspsurf = PSB_DSPSURF(PSB_PIPE_A);
 890         int dspstride = PSB_DSPSTRIDE(PSB_PIPE_A);
 891         int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
 892         u32 dspcntr;
 893         int ret;
 894
 895         memcpy(&globle_dev, dev, sizeof(struct drm_device));
 896
 897         PSB_DEBUG_ENTRY("pipe = 0x%x. \n", pipe);
 898
 899         /* no fb bound */
 900         if (!crtc->fb) {
 901                 PSB_DEBUG_ENTRY("No FB bound\n");
 902                 return 0;
 903         }
 904
 905         ret = check_fb(crtc->fb);
 906         if (ret)
 907                 return ret;
 908
 909         switch (pipe) {
 910         case 0:
 911                 dsplinoff = PSB_DSPLINOFF(PSB_PIPE_A);
 912                 break;
 913         case 1:
 914                 dsplinoff = PSB_DSPLINOFF(PSB_PIPE_B);
 915                 dspsurf = PSB_DSPSURF(PSB_PIPE_B);
 916                 dspstride = PSB_DSPSTRIDE(PSB_PIPE_B);
 917                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
 918                 break;
 919         case 2:
 920                 dsplinoff = PSB_DSPLINOFF(PSB_PIPE_C);
 921                 dspsurf = PSB_DSPSURF(PSB_PIPE_C);
 922                 dspstride = PSB_DSPSTRIDE(PSB_PIPE_C);
 923                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
 924                 break;
 925         default:
 926                 DRM_ERROR("Illegal Pipe Number. \n");
 927                 return -EINVAL;
 928         }
 929
 930         if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
 931                 return 0;
 932
 933         Start = psbfb->offset;
 934         Offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
 935
 936         REG_WRITE(dspstride, crtc->fb->pitches[0]);
 937         dspcntr = REG_READ(dspcntr_reg);
 938         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 939
 940         switch (crtc->fb->bits_per_pixel) {
 941         case 8:
 942                 dspcntr |= DISPPLANE_8BPP;
 943                 break;
 944         case 16:
 945                 if (crtc->fb->depth == 15)
 946                         dspcntr |= DISPPLANE_15_16BPP;
 947                 else
 948                         dspcntr |= DISPPLANE_16BPP;
 949                 break;
 950         case 24:
 951         case 32:
 952                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 953                 break;
 954         }
 955         REG_WRITE(dspcntr_reg, dspcntr);
 956
 957         PSB_DEBUG_ENTRY("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 958
 959         REG_WRITE(dsplinoff, Offset);
 960         REG_READ(dsplinoff);
 961         REG_WRITE(dspsurf, Start);
 962         REG_READ(dspsurf);
 963
 964         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 965
 966         return 0;
 967 }
 968
 969 /**
 970  * Disable the pipe, plane and pll.
 971  *
 972  */
 973 void mdfld_disable_crtc (struct drm_device *dev, int pipe)
 974 {
 975         int dpll_reg = PSB_DSI_PLL_CTRL;
 976         int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
 977         int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
 978         int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
 979         u32 gen_fifo_stat_reg = GEN_FIFO_STAT_REG;
 980         u32 temp;
 981
 982         PSB_DEBUG_ENTRY("pipe = %d \n", pipe);
 983
 984         /**
 985          * NOTE: this path only works for TMD panel now. update it to
 986          * support all MIPI panels later.
 987          */
 988         if (pipe != 1 && (get_panel_type(dev, pipe) == TMD_6X10_VID))
 989                 return;
 990
 991         switch (pipe) {
 992         case 0:
 993                 break;
 994         case 1:
 995                 dpll_reg = PSB_DPLL_CTRL;
 996                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
 997                 dspbase_reg = PSB_DSPSURF(PSB_PIPE_B);
 998                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
 999                 break;
1000         case 2:
1001                 dpll_reg = PSB_DSI_PLL_CTRL;
1002                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
1003                 dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
1004                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
1005                 gen_fifo_stat_reg = GEN_FIFO_STAT_REG + MIPIC_REG_OFFSET;
1006                 break;
1007         default:
1008                 DRM_ERROR("Illegal Pipe Number. \n");
1009                 return;
1010         }
1011
1012         if (pipe != 1)
1013                 mdfld_dsi_gen_fifo_ready (dev, gen_fifo_stat_reg, HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
1014
1015         /* Disable display plane */
1016         temp = REG_READ(dspcntr_reg);
1017         if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1018                 REG_WRITE(dspcntr_reg,
1019                           temp & ~DISPLAY_PLANE_ENABLE);
1020                 /* Flush the plane changes */
1021                 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
1022                 REG_READ(dspbase_reg);
1023         }
1024
1025         /* FIXME_JLIU7 MDFLD_PO revisit */
1026         /* Wait for vblank for the disable to take effect */
1027 // MDFLD_PO_JLIU7               psb_intel_wait_for_vblank(dev);
1028
1029         /* Next, disable display pipes */
1030         temp = REG_READ(pipeconf_reg);
1031         if ((temp & PIPEACONF_ENABLE) != 0) {
1032                 temp &= ~PIPEACONF_ENABLE;
1033                 temp |= PIPECONF_PLANE_OFF | PIPECONF_CURSOR_OFF;
1034                 REG_WRITE(pipeconf_reg, temp);
1035                 REG_READ(pipeconf_reg);
1036
1037                 /* Wait for for the pipe disable to take effect. */
1038                 mdfldWaitForPipeDisable(dev, pipe);
1039         }
1040
1041         temp = REG_READ(dpll_reg);
1042         if (temp & DPLL_VCO_ENABLE) {
1043                 if (((pipe != 1) &&
1044                     !((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) |
1045                        REG_READ(PSB_PIPECONF(PSB_PIPE_C))) & PIPEACONF_ENABLE))
1046                                 || (pipe == 1)){
1047                         temp &= ~(DPLL_VCO_ENABLE);
1048                         REG_WRITE(dpll_reg, temp);
1049                         REG_READ(dpll_reg);
1050                         /* Wait for the clocks to turn off. */
1051                         /* FIXME_MDFLD PO may need more delay */
1052                         udelay(500);
1053
1054                         if (!(temp & MDFLD_PWR_GATE_EN)) {
1055                                 /* gating power of DPLL */
1056                                 REG_WRITE(dpll_reg, temp | MDFLD_PWR_GATE_EN);
1057                                 /* FIXME_MDFLD PO - change 500 to 1 after PO */
1058                                 udelay(5000);
1059                         }
1060                 }
1061         }
1062
1063 }
1064
1065 void mdfld_pipe_disabled(struct drm_device *dev, int pipe)
1066 {
1067         struct drm_psb_private *dev_priv = dev->dev_private;
1068         struct drm_crtc *crtc;
1069         int i;
1070
1071         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1072                 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1073
1074                 if (psb_intel_crtc->pipe == pipe) {
1075                         drm_flip_helper_clear(&psb_intel_crtc->flip_helper);
1076                         break;
1077                 }
1078         }
1079
1080         for (i = 0; i < ARRAY_SIZE(dev_priv->overlays); i++) {
1081                 if (!dev_priv->overlays[i])
1082                         continue;
1083                 mdfld_overlay_pipe_disabled(dev_priv->overlays[i], pipe);
1084         }
1085 }
1086
1087 /**
1088  * Sets the power management mode of the pipe and plane.
1089  *
1090  * This code should probably grow support for turning the cursor off and back
1091  * on appropriately at the same time as we're turning the pipe off/on.
1092  */
1093 static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
1094 {
1095         struct drm_device *dev = crtc->dev;
1096         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1097         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1098         int pipe = psb_intel_crtc->pipe;
1099         int dpll_reg = PSB_DSI_PLL_CTRL;
1100         int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
1101         int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
1102         int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
1103         u32 pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A);
1104         u32 gen_fifo_stat_reg = GEN_FIFO_STAT_REG;
1105         u32 pipeconf = dev_priv->pipeconf;
1106         u32 dspcntr = dev_priv->dspcntr;
1107         u32 mipi_enable_reg = MIPIA_DEVICE_READY_REG;
1108         u32 temp;
1109         bool enabled;
1110         int timeout = 0;
1111
1112         PSB_DEBUG_ENTRY("mode = %d, pipe = %d \n", mode, pipe);
1113
1114         /**
1115          * MIPI dpms
1116          * NOTE: this path only works for TMD panel now. update it to
1117          * support all MIPI panels later.
1118          */
1119         if (pipe != 1 && (get_panel_type(dev, pipe) == TMD_6X10_VID))
1120                 return;
1121
1122 /* FIXME_JLIU7 MDFLD_PO replaced w/ the following function */
1123 /* mdfld_dbi_dpms (struct drm_device *dev, int pipe, bool enabled) */
1124
1125         switch (pipe) {
1126         case 0:
1127                 break;
1128         case 1:
1129                 dpll_reg = DPLL_B;
1130                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
1131                 dspbase_reg = PSB_DSPBASE(PSB_PIPE_B);
1132                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
1133                 pipeconf = dev_priv->pipeconf1;
1134                 dspcntr = dev_priv->dspcntr1;
1135                 dpll_reg = PSB_DPLL_CTRL;
1136                 break;
1137         case 2:
1138                 dpll_reg = PSB_DSI_PLL_CTRL;
1139                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
1140                 dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
1141                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
1142                 pipestat_reg = PSB_PIPESTAT(PSB_PIPE_C);
1143                 pipeconf = dev_priv->pipeconf2;
1144                 dspcntr = dev_priv->dspcntr2;
1145                 gen_fifo_stat_reg = GEN_FIFO_STAT_REG + MIPIC_REG_OFFSET;
1146                 mipi_enable_reg = MIPIA_DEVICE_READY_REG + MIPIC_REG_OFFSET;
1147                 break;
1148         default:
1149                 DRM_ERROR("Illegal Pipe Number. \n");
1150                 return;
1151         }
1152
1153         if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
1154                 return;
1155
1156         /* XXX: When our outputs are all unaware of DPMS modes other than off
1157          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1158          */
1159         switch (mode) {
1160         case DRM_MODE_DPMS_ON:
1161         case DRM_MODE_DPMS_STANDBY:
1162         case DRM_MODE_DPMS_SUSPEND:
1163                 /* Enable the DPLL */
1164                 temp = REG_READ(dpll_reg);
1165
1166                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1167                         /* When ungating power of DPLL, needs to wait 0.5us before enable the VCO */
1168                         if (temp & MDFLD_PWR_GATE_EN) {
1169                                 temp &= ~MDFLD_PWR_GATE_EN;
1170                                 REG_WRITE(dpll_reg, temp);
1171                                 /* FIXME_MDFLD PO - change 500 to 1 after PO */
1172                                 udelay(500);
1173                         }
1174
1175                         REG_WRITE(dpll_reg, temp);
1176                         REG_READ(dpll_reg);
1177                         /* FIXME_MDFLD PO - change 500 to 1 after PO */
1178                         udelay(500);
1179
1180                         REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1181                         REG_READ(dpll_reg);
1182
1183                         /**
1184                          * wait for DSI PLL to lock
1185                          * NOTE: only need to poll status of pipe 0 and pipe 1,
1186                          * since both MIPI pipes share the same PLL.
1187                          */
1188                         while ((pipe != 2) && (timeout < 20000) && !(REG_READ(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) {
1189                                 udelay(150);
1190                                 timeout ++;
1191                         }
1192                 }
1193
1194                 /* Enable the plane */
1195                 temp = REG_READ(dspcntr_reg);
1196                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1197                         REG_WRITE(dspcntr_reg,
1198                                 temp | DISPLAY_PLANE_ENABLE);
1199                         /* Flush the plane changes */
1200                         REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
1201                 }
1202
1203                 /* Enable the pipe */
1204                 temp = REG_READ(pipeconf_reg);
1205                 if ((temp & PIPEACONF_ENABLE) == 0) {
1206                         REG_WRITE(pipeconf_reg, pipeconf);
1207
1208                         /* Wait for for the pipe enable to take effect. */
1209                         mdfldWaitForPipeEnable(dev, pipe);
1210                 }
1211
1212                 /*workaround for sighting 3741701 Random X blank display*/
1213                 /*perform w/a in video mode only on pipe A or C*/
1214                 if ((pipe == 0 || pipe == 2) &&
1215                         (is_panel_vid_or_cmd(dev) == MDFLD_DSI_ENCODER_DPI)) {
1216                         REG_WRITE(pipestat_reg, REG_READ(pipestat_reg));
1217                         msleep(100);
1218                         if(PIPE_VBLANK_STATUS & REG_READ(pipestat_reg)) {
1219                                 printk(KERN_ALERT "OK");
1220                         } else {
1221                                 printk(KERN_ALERT "STUCK!!!!");
1222                                 /*shutdown controller*/
1223                                 temp = REG_READ(dspcntr_reg);
1224                                 REG_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1225                                 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
1226                                 /*mdfld_dsi_dpi_shut_down(dev, pipe);*/
1227                                 REG_WRITE(0xb048, 1);
1228                                 msleep(100);
1229                                 temp = REG_READ(pipeconf_reg);
1230                                 temp &= ~PIPEACONF_ENABLE;
1231                                 REG_WRITE(pipeconf_reg, temp);
1232                                 msleep(100); /*wait for pipe disable*/
1233                         /*printk(KERN_ALERT "70008 is %x\n", REG_READ(0x70008));
1234                         printk(KERN_ALERT "b074 is %x\n", REG_READ(0xb074));*/
1235                                 REG_WRITE(mipi_enable_reg, 0);
1236                                 msleep(100);
1237                         printk(KERN_ALERT "70008 is %x\n", REG_READ(0x70008));
1238                         printk(KERN_ALERT "b074 is %x\n", REG_READ(0xb074));
1239                                 REG_WRITE(0xb004, REG_READ(0xb004));
1240                                 /* try to bring the controller back up again*/
1241                                 REG_WRITE(mipi_enable_reg, 1);
1242                                 temp = REG_READ(dspcntr_reg);
1243                                 REG_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1244                                 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
1245                                 /*mdfld_dsi_dpi_turn_on(dev, pipe);*/
1246                                 REG_WRITE(0xb048, 2);
1247                                 msleep(100);
1248                                 temp = REG_READ(pipeconf_reg);
1249                                 temp |= PIPEACONF_ENABLE;
1250                                 REG_WRITE(pipeconf_reg, temp);
1251                         }
1252                 }
1253
1254                 psb_intel_crtc_load_lut(crtc);
1255
1256                 /* Give the overlay scaler a chance to enable
1257                    if it's on this pipe */
1258                 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
1259
1260                 break;
1261         case DRM_MODE_DPMS_OFF:
1262                 /* Give the overlay scaler a chance to disable
1263                  * if it's on this pipe */
1264                 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
1265                 if (pipe != 1)
1266                         mdfld_dsi_gen_fifo_ready (dev, gen_fifo_stat_reg, HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
1267
1268                 /* Disable the VGA plane that we never use */
1269                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1270
1271                 /* Disable display plane */
1272                 temp = REG_READ(dspcntr_reg);
1273                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1274                         REG_WRITE(dspcntr_reg,
1275                                   temp & ~DISPLAY_PLANE_ENABLE);
1276                         /* Flush the plane changes */
1277                         REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
1278                         REG_READ(dspbase_reg);
1279                 }
1280
1281                 /* FIXME_JLIU7 MDFLD_PO revisit */
1282                 /* Wait for vblank for the disable to take effect */
1283 // MDFLD_PO_JLIU7               psb_intel_wait_for_vblank(dev);
1284
1285                 /* Next, disable display pipes */
1286                 temp = REG_READ(pipeconf_reg);
1287                 if ((temp & PIPEACONF_ENABLE) != 0) {
1288                         temp &= ~PIPEACONF_ENABLE;
1289                         temp |= PIPECONF_PLANE_OFF | PIPECONF_CURSOR_OFF;
1290                         REG_WRITE(pipeconf_reg, temp);
1291 //                      REG_WRITE(pipeconf_reg, 0);
1292                         REG_READ(pipeconf_reg);
1293
1294                         /* Wait for for the pipe disable to take effect. */
1295                         mdfldWaitForPipeDisable(dev, pipe);
1296                 }
1297
1298                 temp = REG_READ(dpll_reg);
1299                 if (temp & DPLL_VCO_ENABLE) {
1300                         if (((pipe != 1) &&
1301                              !((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) |
1302                                 REG_READ(PSB_PIPECONF(PSB_PIPE_C))) &
1303                                                 PIPEACONF_ENABLE)) ||
1304                             (pipe == 1)) {
1305                                 temp &= ~(DPLL_VCO_ENABLE);
1306                                 REG_WRITE(dpll_reg, temp);
1307                                 REG_READ(dpll_reg);
1308                                 /* Wait for the clocks to turn off. */
1309                                 /* FIXME_MDFLD PO may need more delay */
1310                                 udelay(500);
1311 #if 0 /* MDFLD_PO_JLIU7 */
1312                 if (!(temp & MDFLD_PWR_GATE_EN)) {
1313                         /* gating power of DPLL */
1314                         REG_WRITE(dpll_reg, temp | MDFLD_PWR_GATE_EN);
1315                         /* FIXME_MDFLD PO - change 500 to 1 after PO */
1316                         udelay(5000);
1317                 }
1318 #endif  /* MDFLD_PO_JLIU7 */
1319                         }
1320                 }
1321
1322                 mdfld_pipe_disabled(dev, pipe);
1323                 break;
1324         }
1325
1326         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1327
1328 #if 0                           /* JB: Add vblank support later */
1329         if (enabled)
1330                 dev_priv->vblank_pipe |= (1 << pipe);
1331         else
1332                 dev_priv->vblank_pipe &= ~(1 << pipe);
1333 #endif
1334
1335 #if 0                           /* JB: Add sarea support later */
1336         if (!dev->primary->master)
1337                 return;
1338
1339         master_priv = dev->primary->master->driver_priv;
1340         if (!master_priv->sarea_priv)
1341                 return;
1342
1343         switch (pipe) {
1344         case 0:
1345                 master_priv->sarea_priv->planeA_w =
1346                     enabled ? crtc->mode.hdisplay : 0;
1347                 master_priv->sarea_priv->planeA_h =
1348                     enabled ? crtc->mode.vdisplay : 0;
1349                 break;
1350         case 1:
1351                 master_priv->sarea_priv->planeB_w =
1352                     enabled ? crtc->mode.hdisplay : 0;
1353                 master_priv->sarea_priv->planeB_h =
1354                     enabled ? crtc->mode.vdisplay : 0;
1355                 break;
1356         default:
1357                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1358                 break;
1359         }
1360 #endif
1361
1362         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1363 }
1364
1365
1366 #define MDFLD_LIMT_DPLL_19          0
1367 #define MDFLD_LIMT_DPLL_25          1
1368 #define MDFLD_LIMT_DPLL_83          2
1369 #define MDFLD_LIMT_DPLL_100         3
1370 #define MDFLD_LIMT_DSIPLL_19        4
1371 #define MDFLD_LIMT_DSIPLL_25        5
1372 #define MDFLD_LIMT_DSIPLL_83        6
1373 #define MDFLD_LIMT_DSIPLL_100       7
1374
1375 #define MDFLD_DOT_MIN             19750  /* FIXME_MDFLD JLIU7 need to find out  min & max for MDFLD */
1376 #define MDFLD_DOT_MAX             120000
1377 #define MDFLD_DPLL_M_MIN_19         113
1378 #define MDFLD_DPLL_M_MAX_19         155
1379 #define MDFLD_DPLL_P1_MIN_19        2
1380 #define MDFLD_DPLL_P1_MAX_19        10
1381 #define MDFLD_DPLL_M_MIN_25         101
1382 #define MDFLD_DPLL_M_MAX_25         130
1383 #define MDFLD_DPLL_P1_MIN_25        2
1384 #define MDFLD_DPLL_P1_MAX_25        10
1385 #define MDFLD_DPLL_M_MIN_83         64
1386 #define MDFLD_DPLL_M_MAX_83         64
1387 #define MDFLD_DPLL_P1_MIN_83        2
1388 #define MDFLD_DPLL_P1_MAX_83        2
1389 #define MDFLD_DPLL_M_MIN_100        64
1390 #define MDFLD_DPLL_M_MAX_100        64
1391 #define MDFLD_DPLL_P1_MIN_100       2
1392 #define MDFLD_DPLL_P1_MAX_100       2
1393 #define MDFLD_DSIPLL_M_MIN_19       131
1394 #define MDFLD_DSIPLL_M_MAX_19       175
1395 #define MDFLD_DSIPLL_P1_MIN_19      3
1396 #define MDFLD_DSIPLL_P1_MAX_19      8
1397 #define MDFLD_DSIPLL_M_MIN_25       97
1398 #define MDFLD_DSIPLL_M_MAX_25       140
1399 #define MDFLD_DSIPLL_P1_MIN_25      3
1400 #define MDFLD_DSIPLL_P1_MAX_25      9
1401 #define MDFLD_DSIPLL_M_MIN_83       33
1402 #define MDFLD_DSIPLL_M_MAX_83       92
1403 #define MDFLD_DSIPLL_P1_MIN_83      2
1404 #define MDFLD_DSIPLL_P1_MAX_83      3
1405 #define MDFLD_DSIPLL_M_MIN_100      97
1406 #define MDFLD_DSIPLL_M_MAX_100      140
1407 #define MDFLD_DSIPLL_P1_MIN_100     3
1408 #define MDFLD_DSIPLL_P1_MAX_100     9
1409
1410 static const struct mrst_limit_t mdfld_limits[] = {
1411         {                       /* MDFLD_LIMT_DPLL_19 */
1412          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1413          .m = {.min = MDFLD_DPLL_M_MIN_19, .max = MDFLD_DPLL_M_MAX_19},
1414          .p1 = {.min = MDFLD_DPLL_P1_MIN_19, .max = MDFLD_DPLL_P1_MAX_19},
1415          },
1416         {                       /* MDFLD_LIMT_DPLL_25 */
1417          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1418          .m = {.min = MDFLD_DPLL_M_MIN_25, .max = MDFLD_DPLL_M_MAX_25},
1419          .p1 = {.min = MDFLD_DPLL_P1_MIN_25, .max = MDFLD_DPLL_P1_MAX_25},
1420          },
1421         {                       /* MDFLD_LIMT_DPLL_83 */
1422          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1423          .m = {.min = MDFLD_DPLL_M_MIN_83, .max = MDFLD_DPLL_M_MAX_83},
1424          .p1 = {.min = MDFLD_DPLL_P1_MIN_83, .max = MDFLD_DPLL_P1_MAX_83},
1425          },
1426         {                       /* MDFLD_LIMT_DPLL_100 */
1427          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1428          .m = {.min = MDFLD_DPLL_M_MIN_100, .max = MDFLD_DPLL_M_MAX_100},
1429          .p1 = {.min = MDFLD_DPLL_P1_MIN_100, .max = MDFLD_DPLL_P1_MAX_100},
1430          },
1431         {                       /* MDFLD_LIMT_DSIPLL_19 */
1432          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1433          .m = {.min = MDFLD_DSIPLL_M_MIN_19, .max = MDFLD_DSIPLL_M_MAX_19},
1434          .p1 = {.min = MDFLD_DSIPLL_P1_MIN_19, .max = MDFLD_DSIPLL_P1_MAX_19},
1435          },
1436         {                       /* MDFLD_LIMT_DSIPLL_25 */
1437          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1438          .m = {.min = MDFLD_DSIPLL_M_MIN_25, .max = MDFLD_DSIPLL_M_MAX_25},
1439          .p1 = {.min = MDFLD_DSIPLL_P1_MIN_25, .max = MDFLD_DSIPLL_P1_MAX_25},
1440          },
1441         {                       /* MDFLD_LIMT_DSIPLL_83 */
1442          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1443          .m = {.min = MDFLD_DSIPLL_M_MIN_83, .max = MDFLD_DSIPLL_M_MAX_83},
1444          .p1 = {.min = MDFLD_DSIPLL_P1_MIN_83, .max = MDFLD_DSIPLL_P1_MAX_83},
1445          },
1446         {                       /* MDFLD_LIMT_DSIPLL_100 */
1447          .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
1448          .m = {.min = MDFLD_DSIPLL_M_MIN_100, .max = MDFLD_DSIPLL_M_MAX_100},
1449          .p1 = {.min = MDFLD_DSIPLL_P1_MIN_100, .max = MDFLD_DSIPLL_P1_MAX_100},
1450          },
1451 };
1452
1453 #define MDFLD_M_MIN         21
1454 #define MDFLD_M_MAX         180
1455 static const u32 mdfld_m_converts[] = {
1456 /* M configuration table from 9-bit LFSR table */
1457         224, 368, 440, 220, 366, 439, 219, 365, 182, 347, /* 21 - 30 */
1458         173, 342, 171, 85, 298, 149, 74, 37, 18, 265,   /* 31 - 40 */
1459         388, 194, 353, 432, 216, 108, 310, 155, 333, 166, /* 41 - 50 */
1460         83, 41, 276, 138, 325, 162, 337, 168, 340, 170, /* 51 - 60 */
1461         341, 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 61 - 70 */
1462         461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
1463         106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */
1464         71, 35, 273, 136, 324, 418, 465, 488, 500, 506, /* 91 - 100 */
1465         253, 126, 63, 287, 399, 455, 483, 241, 376, 444, /* 101 - 110 */
1466         478, 495, 503, 251, 381, 446, 479, 239, 375, 443, /* 111 - 120 */
1467         477, 238, 119, 315, 157, 78, 295, 147, 329, 420, /* 121 - 130 */
1468         210, 105, 308, 154, 77, 38, 275, 137, 68, 290, /* 131 - 140 */
1469         145, 328, 164, 82, 297, 404, 458, 485, 498, 249, /* 141 - 150 */
1470         380, 190, 351, 431, 471, 235, 117, 314, 413, 206, /* 151 - 160 */
1471         103, 51, 25, 12, 262, 387, 193, 96, 48, 280, /* 161 - 170 */
1472         396, 198, 99, 305, 152, 76, 294, 403, 457, 228, /* 171 - 180 */
1473 };
1474
1475 static const struct mrst_limit_t *mdfld_limit(struct drm_crtc *crtc)
1476 {
1477         const struct mrst_limit_t *limit = NULL;
1478         struct drm_device *dev = crtc->dev;
1479         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1480
1481         if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)
1482             || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI2)) {
1483                 if ((dev_priv->ksel == KSEL_CRYSTAL_19) || (dev_priv->ksel == KSEL_BYPASS_19))
1484                         limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_19];
1485                 else if (dev_priv->ksel == KSEL_BYPASS_25)
1486                         limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_25];
1487                 else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166))
1488                         limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_83];
1489                 else if ((dev_priv->ksel == KSEL_BYPASS_83_100) &&
1490                          (dev_priv->core_freq == 100 || dev_priv->core_freq == 200))
1491                         limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_100];
1492         } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
1493                 if ((dev_priv->ksel == KSEL_CRYSTAL_19) || (dev_priv->ksel == KSEL_BYPASS_19))
1494                         limit = &mdfld_limits[MDFLD_LIMT_DPLL_19];
1495                 else if (dev_priv->ksel == KSEL_BYPASS_25)
1496                         limit = &mdfld_limits[MDFLD_LIMT_DPLL_25];
1497                 else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166))
1498                         limit = &mdfld_limits[MDFLD_LIMT_DPLL_83];
1499                 else if ((dev_priv->ksel == KSEL_BYPASS_83_100) &&
1500                          (dev_priv->core_freq == 100 || dev_priv->core_freq == 200))
1501                         limit = &mdfld_limits[MDFLD_LIMT_DPLL_100];
1502         } else {
1503                 limit = NULL;
1504                 PSB_DEBUG_ENTRY("mdfld_limit Wrong display type. \n");
1505         }
1506
1507         return limit;
1508 }
1509
1510 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1511 static void mdfld_clock(int refclk, struct mrst_clock_t *clock)
1512 {
1513         clock->dot = (refclk * clock->m) / clock->p1;
1514 }
1515
1516 /**
1517  * Returns a set of divisors for the desired target clock with the given refclk,
1518  * or FALSE.  Divisor values are the actual divisors for
1519  */
1520 static bool
1521 mdfldFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
1522                 struct mrst_clock_t *best_clock)
1523 {
1524         struct mrst_clock_t clock;
1525         const struct mrst_limit_t *limit = mdfld_limit(crtc);
1526         int err = target;
1527
1528         memset(best_clock, 0, sizeof(*best_clock));
1529
1530         PSB_DEBUG_ENTRY("mdfldFindBestPLL target = %d,"
1531                          "m_min = %d, m_max = %d, p_min = %d, p_max = %d. \n", target, limit->m.min, limit->m.max, limit->p1.min, limit->p1.max);
1532
1533         for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
1534                 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
1535                      clock.p1++) {
1536                         int this_err;
1537
1538                         mdfld_clock(refclk, &clock);
1539
1540                         this_err = abs(clock.dot - target);
1541                         if (this_err < err) {
1542                                 *best_clock = clock;
1543                                 err = this_err;
1544                         }
1545                 }
1546         }
1547         PSB_DEBUG_ENTRY("mdfldFindBestPLL target = %d,"
1548                          "m = %d, p = %d. \n", target, best_clock->m, best_clock->p1);
1549         PSB_DEBUG_ENTRY("mdfldFindBestPLL err = %d.\n", err);
1550
1551         return err != target;
1552 }
1553
1554 static int mdfld_crtc_dsi_pll_calc(struct drm_crtc *crtc,
1555                                 struct mdfld_dsi_config *dsi_config,
1556                                 struct drm_device *dev,
1557                                 u32 *out_dpll,
1558                                 u32 *out_fp,
1559                                 struct drm_display_mode *adjusted_mode)
1560 {
1561         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1562         struct mrst_clock_t clock;
1563         u32 dpll = 0, fp = 0;
1564         int refclk = 0;
1565         int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0, clk_tmp = 0;
1566         bool ok;
1567
1568         if ((dev_priv->ksel == KSEL_CRYSTAL_19) || (dev_priv->ksel == KSEL_BYPASS_19))
1569         {
1570                 refclk = 19200;
1571                 clk_n = 1, clk_p2 = 8;
1572         } else if (dev_priv->ksel == KSEL_BYPASS_25) {
1573                 refclk = 25000;
1574                 clk_n = 1, clk_p2 = 8;
1575         } else if (dev_priv->ksel == KSEL_CRYSTAL_38) {
1576                 refclk = 38400;
1577                 clk_n = 1, clk_p2 = 8;
1578         } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166)) {
1579                 refclk = 83000;
1580                 clk_n = 4, clk_p2 = 8;
1581         } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) &&
1582                    (dev_priv->core_freq == 100 || dev_priv->core_freq == 200)) {
1583                 refclk = 100000;
1584                 clk_n = 4, clk_p2 = 8;
1585         }else{
1586                 refclk = 19200;
1587                 clk_n = 1, clk_p2 = 8;
1588         }
1589
1590         dev_priv->bpp = 24;
1591         clk_byte = dev_priv->bpp / 8;
1592
1593         if (dsi_config->lane_count)
1594                 clk = adjusted_mode->clock / dsi_config->lane_count;
1595         else
1596                 clk = adjusted_mode->clock;
1597
1598         clk_tmp = clk * clk_n * clk_p2 * clk_byte;
1599
1600         PSB_DEBUG_ENTRY("ref_clk: %d, clk = %d, clk_n = %d, clk_p2 = %d. \n", refclk, clk, clk_n, clk_p2);
1601         PSB_DEBUG_ENTRY("adjusted_mode->clock = %d, clk_tmp = %d. \n", adjusted_mode->clock, clk_tmp);
1602
1603         ok = mdfldFindBestPLL(crtc, clk_tmp, refclk, &clock);
1604         dev_priv->tmds_clock_khz = clock.dot / (clk_n * clk_p2 * clk_byte);
1605
1606         if (!ok) {
1607                 DRM_ERROR
1608                     ("mdfldFindBestPLL fail in mdfld_crtc_mode_set. \n");
1609         } else {
1610                 m_conv = mdfld_m_converts[(clock.m - MDFLD_M_MIN)];
1611                 PSB_DEBUG_ENTRY("dot clock = %d,"
1612                          "m = %d, p1 = %d, m_conv = %d. \n", clock.dot, clock.m,
1613                          clock.p1, m_conv);
1614         }
1615
1616         dpll = 0x00000000;
1617         fp = (clk_n / 2) << 16;
1618         fp |= m_conv;
1619
1620         /* compute bitmask from p1 value */
1621         dpll |= (1 << (clock.p1 - 2)) << 17;
1622
1623         *(out_dpll) = dpll;
1624         *(out_fp) = fp;
1625
1626         PSB_DEBUG_ENTRY("dsi dpll = 0x%x  fp = 0x%x\n", dpll, fp);
1627         return 0;
1628 }
1629
1630 static int mdfld_crtc_dsi_mode_set(struct drm_crtc *crtc,
1631                                 struct mdfld_dsi_config *dsi_config,
1632                                 struct drm_display_mode *mode,
1633                                 struct drm_display_mode *adjusted_mode,
1634                                 int x, int y,
1635                                 struct drm_framebuffer *old_fb)
1636 {
1637         struct drm_device *dev;
1638         struct psb_intel_crtc *mdfld_dsi_crtc;
1639         struct psb_framebuffer *mdfld_fb;
1640         struct psb_intel_mode_device *mode_dev;
1641         struct mdfld_dsi_hw_context *ctx;
1642         struct drm_psb_private *dev_priv;
1643         int fb_bpp;
1644         int fb_pitch;
1645         int fb_depth;
1646         int hdelay;
1647         static int init_flag = 1;   /*bootstrap flag*/
1648
1649         if (!crtc || !crtc->fb) {
1650                 DRM_ERROR("Invalid CRTC\n");
1651                 return -EINVAL;
1652         }
1653
1654         if (!dsi_config) {
1655                 DRM_ERROR("Invalid DSI config\n");
1656                 return -EINVAL;
1657         }
1658
1659         mdfld_dsi_crtc = to_psb_intel_crtc(crtc);
1660         mdfld_fb = to_psb_fb(crtc->fb);
1661         mode_dev = mdfld_dsi_crtc->mode_dev;
1662         mode = adjusted_mode;
1663         ctx = &dsi_config->dsi_hw_context;
1664         fb_bpp = crtc->fb->bits_per_pixel;
1665         fb_pitch = crtc->fb->pitches[0];
1666         fb_depth = crtc->fb->depth;
1667         dev = crtc->dev;
1668         dev_priv = (struct drm_psb_private *)dev->dev_private;
1669
1670         mutex_lock(&dsi_config->context_lock);
1671
1672         ctx->vgacntr = 0x80000000;
1673
1674         /*setup pll*/
1675         mdfld_crtc_dsi_pll_calc(crtc, dsi_config, dev,
1676                                  &ctx->dpll,
1677                                  &ctx->fp,
1678                                  adjusted_mode);
1679
1680         /*set up pipe timings*/
1681         ctx->htotal = (mode->crtc_hdisplay - 1) |
1682                 ((mode->crtc_htotal - 1) << 16);
1683         ctx->hblank = (mode->crtc_hblank_start - 1) |
1684                 ((mode->crtc_hblank_end - 1) << 16);
1685         ctx->hsync = (mode->crtc_hsync_start - 1) |
1686                 ((mode->crtc_hsync_end - 1) << 16);
1687         ctx->vtotal = (mode->crtc_vdisplay - 1) |
1688                 ((mode->crtc_vtotal - 1) << 16);
1689         ctx->vblank = (mode->crtc_vblank_start - 1) |
1690                 ((mode->crtc_vblank_end - 1) << 16);
1691         ctx->vsync = (mode->crtc_vsync_start - 1) |
1692                 ((mode->crtc_vsync_end - 1) << 16);
1693
1694         /*pipe source*/
1695         ctx->pipesrc = ((mode->crtc_hdisplay - 1) << 16) |
1696                 (mode->crtc_vdisplay - 1);
1697
1698         /*setup dsp plane*/
1699         ctx->dsppos = 0;
1700         ctx->dspsize = ((mode->crtc_vdisplay - 1) << 16) | (mode->crtc_hdisplay - 1);
1701
1702         ctx->dspstride = fb_pitch;
1703         ctx->dspsurf = mdfld_fb->offset;
1704         ctx->dsplinoff = y * fb_pitch + x * (fb_bpp / 8);
1705
1706         if (init_flag == 1) {
1707                 printk(KERN_DEBUG"%s: ctx->dspsurf = 0x%x, ctx->dsplinoff = 0x%x\n",
1708                                 __func__, ctx->dsplinoff, ctx->dspsurf);
1709                 init_flag = 0;
1710         }
1711
1712         switch (fb_bpp) {
1713         case 8:
1714                 ctx->dspcntr = DISPPLANE_8BPP;
1715                 break;
1716         case 16:
1717                 if (fb_depth == 15)
1718                         ctx->dspcntr = DISPPLANE_15_16BPP;
1719                 else
1720                         ctx->dspcntr = DISPPLANE_16BPP;
1721                 break;
1722         case 24:
1723         case 32:
1724                 ctx->dspcntr = DISPPLANE_32BPP_NO_ALPHA;
1725                 break;
1726         default:
1727                 DRM_ERROR("Unknown color depth\n");
1728                 mutex_unlock(&dsi_config->context_lock);
1729                 return -EINVAL;
1730         }
1731
1732         if (dsi_config->pipe == 2)
1733                 ctx->dspcntr |= (0x2 << 24);
1734
1735         /*
1736          * Setup pipe configuration for different panels
1737          * The formula recommended from hw team is as below:
1738          * (htotal * 5ns * hdelay) >= 8000ns
1739          * hdelay is the count of delayed HBLANK scan lines
1740          * And the max hdelay is 4
1741          * by programming of PIPE(A/C) CONF bit 28:27:
1742          * 00 = 1 scan line, 01 = 2 scan line,
1743          * 02 = 3 scan line, 03 = 4 scan line
1744          */
1745         ctx->pipeconf &= ~(BIT27 | BIT28);
1746
1747         hdelay = 8000/mode->crtc_htotal/5;
1748         if (8000%(mode->crtc_htotal*5) > 0)
1749                 hdelay += 1;
1750
1751         if (hdelay > 4) {
1752                 DRM_ERROR("Do not support such panel setting yet\n");
1753                 hdelay = 4; /* Use the max hdelay instead*/
1754         }
1755
1756         ctx->pipeconf |= ((hdelay-1) << 27);
1757
1758         mutex_unlock(&dsi_config->context_lock);
1759         return 0;
1760 }
1761
1762 static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
1763                               struct drm_display_mode *mode,
1764                               struct drm_display_mode *adjusted_mode,
1765                               int x, int y,
1766                               struct drm_framebuffer *old_fb)
1767 {
1768         struct drm_device *dev = crtc->dev;
1769         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1770         DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
1771         int pipe = psb_intel_crtc->pipe;
1772         int fp_reg = PSB_DSI_PLL_DIV_M1;
1773         int dpll_reg = PSB_DSI_PLL_CTRL;
1774         int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
1775         int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
1776         int htot_reg = PSB_HTOTAL(PSB_PIPE_A);
1777         int hblank_reg = PSB_HBLANK(PSB_PIPE_A);
1778         int hsync_reg = PSB_HSYNC(PSB_PIPE_A);
1779         int vtot_reg = PSB_VTOTAL(PSB_PIPE_A);
1780         int vblank_reg = PSB_VBLANK(PSB_PIPE_A);
1781         int vsync_reg = PSB_VSYNC(PSB_PIPE_A);
1782         int dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A);
1783         int dsppos_reg = PSB_DSPPOS(PSB_PIPE_A);
1784         int pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A);
1785         u32 *pipeconf = &dev_priv->pipeconf;
1786         u32 *dspcntr = &dev_priv->dspcntr;
1787         int refclk = 0;
1788         int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0, clk_tmp = 0;
1789         struct mrst_clock_t clock;
1790         bool ok;
1791         u32 dpll = 0, fp = 0;
1792         bool is_crt = false, is_lvds = false, is_tv = false;
1793         bool is_mipi = false, is_mipi2 = false, is_hdmi = false;
1794         struct drm_mode_config *mode_config = &dev->mode_config;
1795         struct psb_intel_output *psb_intel_output = NULL;
1796         uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
1797         struct drm_encoder *encoder;
1798         struct drm_connector * connector;
1799         int timeout = 0;
1800         struct mdfld_dsi_config *dsi_config;
1801         int ret;
1802
1803         PSB_DEBUG_ENTRY("pipe = 0x%x\n", pipe);
1804
1805         ret = check_fb(crtc->fb);
1806         if (ret)
1807                 return ret;
1808
1809         /**
1810          * MIPI panel mode setting
1811          * NOTE: this path only works for TMD panel now. update it to
1812          * support all MIPI panels later.
1813          */
1814         if (pipe != 1 && ((get_panel_type(dev, pipe) == TMD_VID) ||
1815                 (get_panel_type(dev, pipe) == TMD_6X10_VID) ||
1816                 (get_panel_type(dev, pipe) == H8C7_VID) ||
1817                 (get_panel_type(dev, pipe) == GI_SONY_VID) ||
1818                 /* SC1 setting */
1819                 (get_panel_type(dev, pipe) == AUO_SC1_VID))) {
1820                 if (pipe == 0)
1821                         dsi_config = dev_priv->dsi_configs[0];
1822                 else if (pipe == 2)
1823                         dsi_config = dev_priv->dsi_configs[1];
1824                 else
1825                         return -EINVAL;
1826                 return mdfld_crtc_dsi_mode_set(crtc, dsi_config, mode,
1827                                 adjusted_mode, x, y, old_fb);
1828         }
1829
1830         if (pipe == 1) {
1831                 if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
1832                         return 0;
1833                 android_hdmi_crtc_mode_set(crtc, mode, adjusted_mode,
1834                         x, y, old_fb);
1835                 goto mrst_crtc_mode_set_exit;
1836         }
1837
1838         switch (pipe) {
1839         case 0:
1840                 break;
1841         case 1:
1842                 fp_reg = FPB0;
1843                 dpll_reg = DPLL_B;
1844                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
1845                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
1846                 htot_reg = PSB_HTOTAL(PSB_PIPE_B);
1847                 hblank_reg = PSB_HBLANK(PSB_PIPE_B);
1848                 hsync_reg = PSB_HSYNC(PSB_PIPE_B);
1849                 vtot_reg = PSB_VTOTAL(PSB_PIPE_B);
1850                 vblank_reg = PSB_VBLANK(PSB_PIPE_B);
1851                 vsync_reg = PSB_VSYNC(PSB_PIPE_B);
1852                 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B);
1853                 dsppos_reg = PSB_DSPPOS(PSB_PIPE_B);
1854                 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B);
1855                 pipeconf = &dev_priv->pipeconf1;
1856                 dspcntr = &dev_priv->dspcntr1;
1857                 fp_reg = PSB_DPLL_DIV0;
1858                 dpll_reg = PSB_DPLL_CTRL;
1859                 break;
1860         case 2:
1861                 dpll_reg = PSB_DSI_PLL_CTRL;
1862                 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
1863                 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
1864                 htot_reg = PSB_HTOTAL(PSB_PIPE_C);
1865                 hblank_reg = PSB_HBLANK(PSB_PIPE_C);
1866                 hsync_reg = PSB_HSYNC(PSB_PIPE_C);
1867                 vtot_reg = PSB_VTOTAL(PSB_PIPE_C);
1868                 vblank_reg = PSB_VBLANK(PSB_PIPE_C);
1869                 vsync_reg = PSB_VSYNC(PSB_PIPE_C);
1870                 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C);
1871                 dsppos_reg = PSB_DSPPOS(PSB_PIPE_C);
1872                 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C);
1873                 pipeconf = &dev_priv->pipeconf2;
1874                 dspcntr = &dev_priv->dspcntr2;
1875                 break;
1876         default:
1877                 DRM_ERROR("Illegal Pipe Number. \n");
1878                 return 0;
1879         }
1880
1881         PSB_DEBUG_ENTRY("adjusted_hdisplay = %d\n",
1882                  adjusted_mode->hdisplay);
1883         PSB_DEBUG_ENTRY("adjusted_vdisplay = %d\n",
1884                  adjusted_mode->vdisplay);
1885         PSB_DEBUG_ENTRY("adjusted_hsync_start = %d\n",
1886                  adjusted_mode->hsync_start);
1887         PSB_DEBUG_ENTRY("adjusted_hsync_end = %d\n",
1888                  adjusted_mode->hsync_end);
1889         PSB_DEBUG_ENTRY("adjusted_htotal = %d\n",
1890                  adjusted_mode->htotal);
1891         PSB_DEBUG_ENTRY("adjusted_vsync_start = %d\n",
1892                  adjusted_mode->vsync_start);
1893         PSB_DEBUG_ENTRY("adjusted_vsync_end = %d\n",
1894                  adjusted_mode->vsync_end);
1895         PSB_DEBUG_ENTRY("adjusted_vtotal = %d\n",
1896                  adjusted_mode->vtotal);
1897         PSB_DEBUG_ENTRY("adjusted_clock = %d\n",
1898                  adjusted_mode->clock);
1899         PSB_DEBUG_ENTRY("hdisplay = %d\n",
1900                  mode->hdisplay);
1901         PSB_DEBUG_ENTRY("vdisplay = %d\n",
1902                  mode->vdisplay);
1903
1904         if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true))
1905                 return 0;
1906
1907         memcpy(&psb_intel_crtc->saved_mode, mode, sizeof(struct drm_display_mode));
1908         memcpy(&psb_intel_crtc->saved_adjusted_mode, adjusted_mode, sizeof(struct drm_display_mode));
1909
1910         list_for_each_entry(connector, &mode_config->connector_list, head) {
1911                 if(!connector)
1912                         continue;
1913
1914                 encoder = connector->encoder;
1915
1916                 if(!encoder)
1917                         continue;
1918
1919                 if (encoder->crtc != crtc)
1920                         continue;
1921
1922                 psb_intel_output = to_psb_intel_output(connector);
1923
1924                 PSB_DEBUG_ENTRY("output->type = 0x%x \n", psb_intel_output->type);
1925
1926                 switch (psb_intel_output->type) {
1927                 case INTEL_OUTPUT_LVDS:
1928                         is_lvds = true;
1929                         break;
1930                 case INTEL_OUTPUT_TVOUT:
1931                         is_tv = true;
1932                         break;
1933                 case INTEL_OUTPUT_ANALOG:
1934                         is_crt = true;
1935                         break;
1936                 case INTEL_OUTPUT_MIPI:
1937                         is_mipi = true;
1938                         break;
1939                 case INTEL_OUTPUT_MIPI2:
1940                         is_mipi2 = true;
1941                         break;
1942                 case INTEL_OUTPUT_HDMI:
1943                         is_hdmi = true;
1944                         break;
1945                 }
1946         }
1947
1948         /* Disable the VGA plane that we never use */
1949         REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1950
1951         /* Disable the panel fitter if it was on our pipe */
1952         if (psb_intel_panel_fitter_pipe(dev) == pipe)
1953                 REG_WRITE(PFIT_CONTROL, 0);
1954
1955         /* pipesrc and dspsize control the size that is scaled from,
1956          * which should always be the user's requested size.
1957          */
1958         if (pipe == 1) {
1959                 /* FIXME: To make HDMI display with 864x480 (TPO), 480x864 (PYR) or 480x854 (TMD), set the sprite
1960                  * width/height and souce image size registers with the adjusted mode for pipe B. */
1961
1962                 /* The defined sprite rectangle must always be completely contained within the displayable
1963                  * area of the screen image (frame buffer). */
1964                 REG_WRITE(dspsize_reg, ((MIN(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16)
1965                                 | (MIN(mode->crtc_hdisplay, adjusted_mode->crtc_hdisplay) - 1));
1966                 /* Set the CRTC with encoder mode. */
1967                 REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16)
1968                                  | (mode->crtc_vdisplay - 1));
1969         } else {
1970                 REG_WRITE(dspsize_reg, ((mode->crtc_vdisplay - 1) << 16) | (mode->crtc_hdisplay - 1));
1971                 REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
1972         }
1973
1974         REG_WRITE(dsppos_reg, 0);
1975
1976         if (psb_intel_output)
1977                 drm_connector_property_get_value(&psb_intel_output->base,
1978                         dev->mode_config.scaling_mode_property, &scalingType);
1979
1980         if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
1981                 /*Moorestown doesn't have register support for centering so we need to
1982                   mess with the h/vblank and h/vsync start and ends to get centering*/
1983                 int offsetX = 0, offsetY = 0;
1984
1985                 offsetX = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
1986                 offsetY = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
1987
1988                 REG_WRITE(htot_reg, (mode->crtc_hdisplay - 1) |
1989                         ((adjusted_mode->crtc_htotal - 1) << 16));
1990                 REG_WRITE(vtot_reg, (mode->crtc_vdisplay - 1) |
1991                         ((adjusted_mode->crtc_vtotal - 1) << 16));
1992                 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - offsetX - 1) |
1993                         ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
1994                 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - offsetX - 1) |
1995                         ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
1996                 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - offsetY - 1) |
1997                         ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
1998                 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - offsetY - 1) |
1999                         ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
2000         } else {
2001                 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2002                         ((adjusted_mode->crtc_htotal - 1) << 16));
2003                 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2004                         ((adjusted_mode->crtc_vtotal - 1) << 16));
2005                 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2006                         ((adjusted_mode->crtc_hblank_end - 1) << 16));
2007                 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2008                         ((adjusted_mode->crtc_hsync_end - 1) << 16));
2009                 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2010                         ((adjusted_mode->crtc_vblank_end - 1) << 16));
2011                 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2012                         ((adjusted_mode->crtc_vsync_end - 1) << 16));
2013         }
2014
2015         /* Flush the plane changes */
2016         {
2017                 struct drm_crtc_helper_funcs *crtc_funcs =
2018                     crtc->helper_private;
2019                 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
2020         }
2021
2022         /* setup pipeconf */
2023         *pipeconf = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */
2024
2025         /* Set up the display plane register */
2026         *dspcntr = REG_READ(dspcntr_reg);
2027         *dspcntr |= pipe << DISPPLANE_SEL_PIPE_POS;
2028         *dspcntr |= DISPLAY_PLANE_ENABLE;
2029 /* MDFLD_PO_JLIU7       dspcntr |= DISPPLANE_BOTTOM; */
2030 /* MDFLD_PO_JLIU7       dspcntr |= DISPPLANE_GAMMA_ENABLE; */
2031
2032         if (is_mipi2)
2033         {
2034                 goto mrst_crtc_mode_set_exit;
2035         }
2036 /* FIXME JLIU7 Add MDFLD HDMI supports */
2037 /* FIXME_MDFLD JLIU7 DSIPLL clock *= 8? */
2038 /* FIXME_MDFLD JLIU7 need to revist for dual MIPI supports */
2039         clk = adjusted_mode->clock;
2040
2041         if (is_hdmi) {
2042                 if ((dev_priv->ksel == KSEL_CRYSTAL_19) || (dev_priv->ksel == KSEL_BYPASS_19))
2043                 {
2044                         refclk = 19200;
2045
2046                         if (is_mipi || is_mipi2)
2047                         {
2048                                 clk_n = 1, clk_p2 = 8;
2049                         } else if (is_hdmi) {
2050                                 clk_n = 1, clk_p2 = 10;
2051                         }
2052                 } else if (dev_priv->ksel == KSEL_BYPASS_25) {
2053                         refclk = 25000;
2054
2055                         if (is_mipi || is_mipi2)
2056                         {
2057                                 clk_n = 1, clk_p2 = 8;
2058                         } else if (is_hdmi) {
2059                                 clk_n = 1, clk_p2 = 10;
2060                         }
2061                 } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) && (dev_priv->core_freq == 166)) {
2062                         refclk = 83000;
2063
2064                         if (is_mipi || is_mipi2)
2065                         {
2066                                 clk_n = 4, clk_p2 = 8;
2067                         } else if (is_hdmi) {
2068                                 clk_n = 4, clk_p2 = 10;
2069                         }
2070                 } else if ((dev_priv->ksel == KSEL_BYPASS_83_100) &&
2071                            (dev_priv->core_freq == 100 || dev_priv->core_freq == 200)) {
2072                         refclk = 100000;
2073                         if (is_mipi || is_mipi2)
2074                         {
2075                                 clk_n = 4, clk_p2 = 8;
2076                         } else if (is_hdmi) {
2077                                 clk_n = 4, clk_p2 = 10;
2078                         }
2079                 }
2080
2081                 if (is_mipi)
2082                         clk_byte = dev_priv->bpp / 8;
2083                 else if (is_mipi2)
2084                         clk_byte = dev_priv->bpp2 / 8;
2085
2086                 clk_tmp = clk * clk_n * clk_p2 * clk_byte;
2087
2088                 PSB_DEBUG_ENTRY("clk = %d, clk_n = %d, clk_p2 = %d. \n", clk, clk_n, clk_p2);
2089                 PSB_DEBUG_ENTRY("adjusted_mode->clock = %d, clk_tmp = %d. \n", adjusted_mode->clock, clk_tmp);
2090
2091                 ok = mdfldFindBestPLL(crtc, clk_tmp, refclk, &clock);
2092                 dev_priv->tmds_clock_khz = clock.dot / (clk_n * clk_p2 * clk_byte);
2093
2094                 if (!ok) {
2095 #if 0                           /* FIXME JLIU7 */
2096                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
2097                         return;
2098 #endif                          /* FIXME JLIU7 */
2099                         DRM_ERROR
2100                             ("mdfldFindBestPLL fail in mdfld_crtc_mode_set. \n");
2101                 } else {
2102                         m_conv = mdfld_m_converts[(clock.m - MDFLD_M_MIN)];
2103
2104                         PSB_DEBUG_ENTRY("dot clock = %d,"
2105                                  "m = %d, p1 = %d, m_conv = %d. \n", clock.dot, clock.m,
2106                                  clock.p1, m_conv);
2107                 }
2108
2109                 dpll = REG_READ(dpll_reg);
2110
2111                 if (dpll & DPLL_VCO_ENABLE) {
2112                         dpll &= ~DPLL_VCO_ENABLE;
2113                         REG_WRITE(dpll_reg, dpll);
2114                         REG_READ(dpll_reg);
2115
2116                         /* FIXME jliu7 check the DPLL lock bit PIPEACONF[29] */
2117                         /* FIXME_MDFLD PO - change 500 to 1 after PO */
2118                         udelay(500);
2119
2120                         /* reset M1, N1 & P1 */
2121                         REG_WRITE(fp_reg, 0);
2122                         dpll &= ~MDFLD_P1_MASK;
2123                         REG_WRITE(dpll_reg, dpll);
2124                         /* FIXME_MDFLD PO - change 500 to 1 after PO */
2125                         udelay(500);
2126                 }
2127
2128                 /* When ungating power of DPLL, needs to wait 0.5us before enable the VCO */
2129                 if (dpll & MDFLD_PWR_GATE_EN) {
2130                         dpll &= ~MDFLD_PWR_GATE_EN;
2131                         REG_WRITE(dpll_reg, dpll);
2132                         /* FIXME_MDFLD PO - change 500 to 1 after PO */
2133                         udelay(500);
2134                 }
2135
2136                 dpll = 0;
2137
2138 #if 0 /* FIXME revisit later */
2139                 if ((dev_priv->ksel == KSEL_CRYSTAL_19) || (dev_priv->ksel == KSEL_BYPASS_19) || (dev_priv->ksel == KSEL_BYPASS_25)) {
2140                         dpll &= ~MDFLD_INPUT_REF_SEL;
2141                 } else if (dev_priv->ksel == KSEL_BYPASS_83_100) {
2142                         dpll |= MDFLD_INPUT_REF_SEL;
2143                 }
2144 #endif /* FIXME revisit later */
2145
2146                 if (is_hdmi)
2147                         dpll |= MDFLD_VCO_SEL;
2148
2149                 fp = (clk_n / 2) << 16;
2150                 fp |= m_conv;
2151
2152                 /* compute bitmask from p1 value */
2153                 dpll |= (1 << (clock.p1 - 2)) << 17;
2154
2155 #if 0 /* 1080p30 & 720p */
2156                 dpll = 0x00050000;
2157                 fp = 0x000001be;
2158 #endif
2159 #if 0 /* 480p */
2160                 dpll = 0x02010000;
2161                 fp = 0x000000d2;
2162 #endif
2163         } else {
2164 #if 0 /*DBI_TPO_480x864*/
2165                 dpll = 0x00020000;
2166                 fp = 0x00000156;
2167 #endif /* DBI_TPO_480x864 */ /* get from spec. */
2168
2169                 dpll = 0x00800000;
2170                 fp = 0x000000c1;
2171 }
2172
2173         REG_WRITE(fp_reg, fp);
2174         REG_WRITE(dpll_reg, dpll);
2175         /* FIXME_MDFLD PO - change 500 to 1 after PO */
2176         udelay(500);
2177
2178         dpll |= DPLL_VCO_ENABLE;
2179         REG_WRITE(dpll_reg, dpll);
2180         REG_READ(dpll_reg);
2181
2182         /* wait for DSI PLL to lock */
2183         while ((timeout < 20000) && !(REG_READ(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) {
2184                 udelay(150);
2185                 timeout ++;
2186         }
2187
2188         if (is_mipi)
2189                 goto mrst_crtc_mode_set_exit;
2190
2191         PSB_DEBUG_ENTRY("is_mipi = 0x%x \n", is_mipi);
2192
2193         REG_WRITE(pipeconf_reg, *pipeconf);
2194         REG_READ(pipeconf_reg);
2195
2196         /* Wait for for the pipe enable to take effect. */
2197 //FIXME_JLIU7 HDMI      mrstWaitForPipeEnable(dev);
2198
2199         REG_WRITE(dspcntr_reg, *dspcntr);
2200         psb_intel_wait_for_vblank(dev);
2201
2202 mrst_crtc_mode_set_exit:
2203
2204         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
2205
2206         return 0;
2207 }