drivers/staging/media/tegra-vde/tegra-vde.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * NVIDIA Tegra Video decoder driver
   4  *
   5  * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
   6  *
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/dma-buf.h>
  11 #include <linux/genalloc.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/miscdevice.h>
  15 #include <linux/module.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/reset.h>
  19 #include <linux/slab.h>
  20 #include <linux/uaccess.h>
  21
  22 #include <soc/tegra/pmc.h>
  23
  24 #include "uapi.h"
  25
  26 #define ICMDQUE_WR              0x00
  27 #define CMDQUE_CONTROL          0x08
  28 #define INTR_STATUS             0x18
  29 #define BSE_INT_ENB             0x40
  30 #define BSE_CONFIG              0x44
  31
  32 #define BSE_ICMDQUE_EMPTY       BIT(3)
  33 #define BSE_DMA_BUSY            BIT(23)
  34
  35 struct video_frame {
  36         struct dma_buf_attachment *y_dmabuf_attachment;
  37         struct dma_buf_attachment *cb_dmabuf_attachment;
  38         struct dma_buf_attachment *cr_dmabuf_attachment;
  39         struct dma_buf_attachment *aux_dmabuf_attachment;
  40         struct sg_table *y_sgt;
  41         struct sg_table *cb_sgt;
  42         struct sg_table *cr_sgt;
  43         struct sg_table *aux_sgt;
  44         dma_addr_t y_addr;
  45         dma_addr_t cb_addr;
  46         dma_addr_t cr_addr;
  47         dma_addr_t aux_addr;
  48         u32 frame_num;
  49         u32 flags;
  50 };
  51
  52 struct tegra_vde {
  53         void __iomem *sxe;
  54         void __iomem *bsev;
  55         void __iomem *mbe;
  56         void __iomem *ppe;
  57         void __iomem *mce;
  58         void __iomem *tfe;
  59         void __iomem *ppb;
  60         void __iomem *vdma;
  61         void __iomem *frameid;
  62         struct mutex lock;
  63         struct miscdevice miscdev;
  64         struct reset_control *rst;
  65         struct reset_control *rst_mc;
  66         struct gen_pool *iram_pool;
  67         struct completion decode_completion;
  68         struct clk *clk;
  69         dma_addr_t iram_lists_addr;
  70         u32 *iram;
  71 };
  72
  73 static __maybe_unused char const *
  74 tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base)
  75 {
  76         if (vde->sxe == base)
  77                 return "SXE";
  78
  79         if (vde->bsev == base)
  80                 return "BSEV";
  81
  82         if (vde->mbe == base)
  83                 return "MBE";
  84
  85         if (vde->ppe == base)
  86                 return "PPE";
  87
  88         if (vde->mce == base)
  89                 return "MCE";
  90
  91         if (vde->tfe == base)
  92                 return "TFE";
  93
  94         if (vde->ppb == base)
  95                 return "PPB";
  96
  97         if (vde->vdma == base)
  98                 return "VDMA";
  99
 100         if (vde->frameid == base)
 101                 return "FRAMEID";
 102
 103         return "???";
 104 }
 105
 106 #define CREATE_TRACE_POINTS
 107 #include "trace.h"
 108
 109 static void tegra_vde_writel(struct tegra_vde *vde,
 110                              u32 value, void __iomem *base, u32 offset)
 111 {
 112         trace_vde_writel(vde, base, offset, value);
 113
 114         writel_relaxed(value, base + offset);
 115 }
 116
 117 static u32 tegra_vde_readl(struct tegra_vde *vde,
 118                            void __iomem *base, u32 offset)
 119 {
 120         u32 value = readl_relaxed(base + offset);
 121
 122         trace_vde_readl(vde, base, offset, value);
 123
 124         return value;
 125 }
 126
 127 static void tegra_vde_set_bits(struct tegra_vde *vde,
 128                                u32 mask, void __iomem *base, u32 offset)
 129 {
 130         u32 value = tegra_vde_readl(vde, base, offset);
 131
 132         tegra_vde_writel(vde, value | mask, base, offset);
 133 }
 134
 135 static int tegra_vde_wait_mbe(struct tegra_vde *vde)
 136 {
 137         u32 tmp;
 138
 139         return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp,
 140                                           (tmp >= 0x10), 1, 100);
 141 }
 142
 143 static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde,
 144                                          unsigned int refs_nb,
 145                                          bool setup_refs)
 146 {
 147         u32 frame_idx_enb_mask = 0;
 148         u32 value;
 149         unsigned int frame_idx;
 150         unsigned int idx;
 151         int err;
 152
 153         tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80);
 154         tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80);
 155
 156         err = tegra_vde_wait_mbe(vde);
 157         if (err)
 158                 return err;
 159
 160         if (!setup_refs)
 161                 return 0;
 162
 163         for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) {
 164                 tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23),
 165                                  vde->mbe, 0x80);
 166                 tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23),
 167                                  vde->mbe, 0x80);
 168
 169                 frame_idx_enb_mask |= frame_idx << (6 * (idx % 4));
 170
 171                 if (idx % 4 == 3 || idx == refs_nb - 1) {
 172                         value = 0xC0000000;
 173                         value |= (idx >> 2) << 24;
 174                         value |= frame_idx_enb_mask;
 175
 176                         tegra_vde_writel(vde, value, vde->mbe, 0x80);
 177
 178                         err = tegra_vde_wait_mbe(vde);
 179                         if (err)
 180                                 return err;
 181
 182                         frame_idx_enb_mask = 0;
 183                 }
 184         }
 185
 186         return 0;
 187 }
 188
 189 static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val)
 190 {
 191         tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF),
 192                          vde->mbe, 0x80);
 193         tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16),
 194                          vde->mbe, 0x80);
 195 }
 196
 197 static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma)
 198 {
 199         struct device *dev = vde->miscdev.parent;
 200         u32 value;
 201         int err;
 202
 203         err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
 204                                          !(value & BIT(2)), 1, 100);
 205         if (err) {
 206                 dev_err(dev, "BSEV unknown bit timeout\n");
 207                 return err;
 208         }
 209
 210         err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
 211                                          (value & BSE_ICMDQUE_EMPTY), 1, 100);
 212         if (err) {
 213                 dev_err(dev, "BSEV ICMDQUE flush timeout\n");
 214                 return err;
 215         }
 216
 217         if (!wait_dma)
 218                 return 0;
 219
 220         err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value,
 221                                          !(value & BSE_DMA_BUSY), 1, 100);
 222         if (err) {
 223                 dev_err(dev, "BSEV DMA timeout\n");
 224                 return err;
 225         }
 226
 227         return 0;
 228 }
 229
 230 static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde,
 231                                             u32 value, bool wait_dma)
 232 {
 233         tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR);
 234
 235         return tegra_vde_wait_bsev(vde, wait_dma);
 236 }
 237
 238 static void tegra_vde_setup_frameid(struct tegra_vde *vde,
 239                                     struct video_frame *frame,
 240                                     unsigned int frameid,
 241                                     u32 mbs_width, u32 mbs_height)
 242 {
 243         u32 y_addr  = frame ? frame->y_addr  : 0x6CDEAD00;
 244         u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00;
 245         u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00;
 246         u32 value1 = frame ? ((mbs_width << 16) | mbs_height) : 0;
 247         u32 value2 = frame ? ((((mbs_width + 1) >> 1) << 6) | 1) : 0;
 248
 249         tegra_vde_writel(vde, y_addr  >> 8, vde->frameid, 0x000 + frameid * 4);
 250         tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4);
 251         tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4);
 252         tegra_vde_writel(vde, value1,       vde->frameid, 0x080 + frameid * 4);
 253         tegra_vde_writel(vde, value2,       vde->frameid, 0x280 + frameid * 4);
 254 }
 255
 256 static void tegra_setup_frameidx(struct tegra_vde *vde,
 257                                  struct video_frame *frames,
 258                                  unsigned int frames_nb,
 259                                  u32 mbs_width, u32 mbs_height)
 260 {
 261         unsigned int idx;
 262
 263         for (idx = 0; idx < frames_nb; idx++)
 264                 tegra_vde_setup_frameid(vde, &frames[idx], idx,
 265                                         mbs_width, mbs_height);
 266
 267         for (; idx < 17; idx++)
 268                 tegra_vde_setup_frameid(vde, NULL, idx, 0, 0);
 269 }
 270
 271 static void tegra_vde_setup_iram_entry(struct tegra_vde *vde,
 272                                        unsigned int table,
 273                                        unsigned int row,
 274                                        u32 value1, u32 value2)
 275 {
 276         u32 *iram_tables = vde->iram;
 277
 278         trace_vde_setup_iram_entry(table, row, value1, value2);
 279
 280         iram_tables[0x20 * table + row * 2] = value1;
 281         iram_tables[0x20 * table + row * 2 + 1] = value2;
 282 }
 283
 284 static void tegra_vde_setup_iram_tables(struct tegra_vde *vde,
 285                                         struct video_frame *dpb_frames,
 286                                         unsigned int ref_frames_nb,
 287                                         unsigned int with_earlier_poc_nb)
 288 {
 289         struct video_frame *frame;
 290         u32 value, aux_addr;
 291         int with_later_poc_nb;
 292         unsigned int i, k;
 293
 294         trace_vde_ref_l0(dpb_frames[0].frame_num);
 295
 296         for (i = 0; i < 16; i++) {
 297                 if (i < ref_frames_nb) {
 298                         frame = &dpb_frames[i + 1];
 299
 300                         aux_addr = frame->aux_addr;
 301
 302                         value  = (i + 1) << 26;
 303                         value |= !(frame->flags & FLAG_B_FRAME) << 25;
 304                         value |= 1 << 24;
 305                         value |= frame->frame_num;
 306                 } else {
 307                         aux_addr = 0x6ADEAD00;
 308                         value = 0;
 309                 }
 310
 311                 tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr);
 312                 tegra_vde_setup_iram_entry(vde, 1, i, value, aux_addr);
 313                 tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
 314                 tegra_vde_setup_iram_entry(vde, 3, i, value, aux_addr);
 315         }
 316
 317         if (!(dpb_frames[0].flags & FLAG_B_FRAME))
 318                 return;
 319
 320         if (with_earlier_poc_nb >= ref_frames_nb)
 321                 return;
 322
 323         with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb;
 324
 325         trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb);
 326
 327         for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) {
 328                 frame = &dpb_frames[k + 1];
 329
 330                 aux_addr = frame->aux_addr;
 331
 332                 value  = (k + 1) << 26;
 333                 value |= !(frame->flags & FLAG_B_FRAME) << 25;
 334                 value |= 1 << 24;
 335                 value |= frame->frame_num;
 336
 337                 tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
 338         }
 339
 340         for (k = 0; i < ref_frames_nb; i++, k++) {
 341                 frame = &dpb_frames[k + 1];
 342
 343                 aux_addr = frame->aux_addr;
 344
 345                 value  = (k + 1) << 26;
 346                 value |= !(frame->flags & FLAG_B_FRAME) << 25;
 347                 value |= 1 << 24;
 348                 value |= frame->frame_num;
 349
 350                 tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr);
 351         }
 352 }
 353
 354 static int tegra_vde_setup_hw_context(struct tegra_vde *vde,
 355                                       struct tegra_vde_h264_decoder_ctx *ctx,
 356                                       struct video_frame *dpb_frames,
 357                                       dma_addr_t bitstream_data_addr,
 358                                       size_t bitstream_data_size,
 359                                       unsigned int macroblocks_nb)
 360 {
 361         struct device *dev = vde->miscdev.parent;
 362         u32 value;
 363         int err;
 364
 365         tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0);
 366         tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL);
 367         tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50);
 368         tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0);
 369         tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14);
 370         tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28);
 371         tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08);
 372         tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00);
 373         tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04);
 374
 375         tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C);
 376         tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00);
 377         tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04);
 378         tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200);
 379         tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04);
 380         tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84);
 381         tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08);
 382         tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54);
 383         tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58);
 384         tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C);
 385         tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10);
 386         tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS);
 387         tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG);
 388         tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB);
 389         tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98);
 390         tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C);
 391
 392         memset(vde->iram + 128, 0, macroblocks_nb / 2);
 393
 394         tegra_setup_frameidx(vde, dpb_frames, ctx->dpb_frames_nb,
 395                              ctx->pic_width_in_mbs, ctx->pic_height_in_mbs);
 396
 397         tegra_vde_setup_iram_tables(vde, dpb_frames,
 398                                     ctx->dpb_frames_nb - 1,
 399                                     ctx->dpb_ref_frames_with_earlier_poc_nb);
 400
 401         /*
 402          * The IRAM mapping is write-combine, ensure that CPU buffers have
 403          * been flushed at this point.
 404          */
 405         wmb();
 406
 407         tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C);
 408         tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size,
 409                          vde->bsev, 0x54);
 410
 411         value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3;
 412
 413         tegra_vde_writel(vde, value, vde->bsev, 0x88);
 414
 415         err = tegra_vde_wait_bsev(vde, false);
 416         if (err)
 417                 return err;
 418
 419         err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false);
 420         if (err)
 421                 return err;
 422
 423         value = 0x01500000;
 424         value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF;
 425
 426         err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
 427         if (err)
 428                 return err;
 429
 430         err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false);
 431         if (err)
 432                 return err;
 433
 434         err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false);
 435         if (err)
 436                 return err;
 437
 438         value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF);
 439
 440         err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true);
 441         if (err)
 442                 return err;
 443
 444         value = 0x00800005;
 445         value |= ctx->pic_width_in_mbs << 11;
 446         value |= ctx->pic_height_in_mbs << 3;
 447
 448         tegra_vde_writel(vde, value, vde->sxe, 0x10);
 449
 450         value = !ctx->baseline_profile << 17;
 451         value |= ctx->level_idc << 13;
 452         value |= ctx->log2_max_pic_order_cnt_lsb << 7;
 453         value |= ctx->pic_order_cnt_type << 5;
 454         value |= ctx->log2_max_frame_num;
 455
 456         tegra_vde_writel(vde, value, vde->sxe, 0x40);
 457
 458         value = ctx->pic_init_qp << 25;
 459         value |= !!(ctx->deblocking_filter_control_present_flag) << 2;
 460         value |= !!ctx->pic_order_present_flag;
 461
 462         tegra_vde_writel(vde, value, vde->sxe, 0x44);
 463
 464         value = ctx->chroma_qp_index_offset;
 465         value |= ctx->num_ref_idx_l0_active_minus1 << 5;
 466         value |= ctx->num_ref_idx_l1_active_minus1 << 10;
 467         value |= !!ctx->constrained_intra_pred_flag << 15;
 468
 469         tegra_vde_writel(vde, value, vde->sxe, 0x48);
 470
 471         value = 0x0C000000;
 472         value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24;
 473
 474         tegra_vde_writel(vde, value, vde->sxe, 0x4C);
 475
 476         value = 0x03800000;
 477         value |= bitstream_data_size & GENMASK(19, 15);
 478
 479         tegra_vde_writel(vde, value, vde->sxe, 0x68);
 480
 481         tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C);
 482
 483         value = 0x10000005;
 484         value |= ctx->pic_width_in_mbs << 11;
 485         value |= ctx->pic_height_in_mbs << 3;
 486
 487         tegra_vde_writel(vde, value, vde->mbe, 0x80);
 488
 489         value = 0x26800000;
 490         value |= ctx->level_idc << 4;
 491         value |= !ctx->baseline_profile << 1;
 492         value |= !!ctx->direct_8x8_inference_flag;
 493
 494         tegra_vde_writel(vde, value, vde->mbe, 0x80);
 495
 496         tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80);
 497         tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80);
 498         tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80);
 499
 500         value = 0x20000000;
 501         value |= ctx->chroma_qp_index_offset << 8;
 502
 503         tegra_vde_writel(vde, value, vde->mbe, 0x80);
 504
 505         err = tegra_vde_setup_mbe_frame_idx(vde,
 506                                             ctx->dpb_frames_nb - 1,
 507                                             ctx->pic_order_cnt_type == 0);
 508         if (err) {
 509                 dev_err(dev, "MBE frames setup failed %d\n", err);
 510                 return err;
 511         }
 512
 513         tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC);
 514         tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00);
 515         tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00);
 516         tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00);
 517         tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr);
 518
 519         value = 0xFC000000;
 520         value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2;
 521
 522         if (!ctx->baseline_profile)
 523                 value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1;
 524
 525         tegra_vde_writel(vde, value, vde->mbe, 0x80);
 526
 527         err = tegra_vde_wait_mbe(vde);
 528         if (err) {
 529                 dev_err(dev, "MBE programming failed %d\n", err);
 530                 return err;
 531         }
 532
 533         return 0;
 534 }
 535
 536 static void tegra_vde_decode_frame(struct tegra_vde *vde,
 537                                    unsigned int macroblocks_nb)
 538 {
 539         reinit_completion(&vde->decode_completion);
 540
 541         tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C);
 542         tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1),
 543                          vde->sxe, 0x00);
 544 }
 545
 546 static void tegra_vde_detach_and_put_dmabuf(struct dma_buf_attachment *a,
 547                                             struct sg_table *sgt,
 548                                             enum dma_data_direction dma_dir)
 549 {
 550         struct dma_buf *dmabuf = a->dmabuf;
 551
 552         dma_buf_unmap_attachment(a, sgt, dma_dir);
 553         dma_buf_detach(dmabuf, a);
 554         dma_buf_put(dmabuf);
 555 }
 556
 557 static int tegra_vde_attach_dmabuf(struct device *dev,
 558                                    int fd,
 559                                    unsigned long offset,
 560                                    size_t min_size,
 561                                    size_t align_size,
 562                                    struct dma_buf_attachment **a,
 563                                    dma_addr_t *addr,
 564                                    struct sg_table **s,
 565                                    size_t *size,
 566                                    enum dma_data_direction dma_dir)
 567 {
 568         struct dma_buf_attachment *attachment;
 569         struct dma_buf *dmabuf;
 570         struct sg_table *sgt;
 571         int err;
 572
 573         dmabuf = dma_buf_get(fd);
 574         if (IS_ERR(dmabuf)) {
 575                 dev_err(dev, "Invalid dmabuf FD\n");
 576                 return PTR_ERR(dmabuf);
 577         }
 578
 579         if (dmabuf->size & (align_size - 1)) {
 580                 dev_err(dev, "Unaligned dmabuf 0x%zX, should be aligned to 0x%zX\n",
 581                         dmabuf->size, align_size);
 582                 return -EINVAL;
 583         }
 584
 585         if ((u64)offset + min_size > dmabuf->size) {
 586                 dev_err(dev, "Too small dmabuf size %zu @0x%lX, should be at least %zu\n",
 587                         dmabuf->size, offset, min_size);
 588                 return -EINVAL;
 589         }
 590
 591         attachment = dma_buf_attach(dmabuf, dev);
 592         if (IS_ERR(attachment)) {
 593                 dev_err(dev, "Failed to attach dmabuf\n");
 594                 err = PTR_ERR(attachment);
 595                 goto err_put;
 596         }
 597
 598         sgt = dma_buf_map_attachment(attachment, dma_dir);
 599         if (IS_ERR(sgt)) {
 600                 dev_err(dev, "Failed to get dmabufs sg_table\n");
 601                 err = PTR_ERR(sgt);
 602                 goto err_detach;
 603         }
 604
 605         if (sgt->nents != 1) {
 606                 dev_err(dev, "Sparse DMA region is unsupported\n");
 607                 err = -EINVAL;
 608                 goto err_unmap;
 609         }
 610
 611         *addr = sg_dma_address(sgt->sgl) + offset;
 612         *a = attachment;
 613         *s = sgt;
 614
 615         if (size)
 616                 *size = dmabuf->size - offset;
 617
 618         return 0;
 619
 620 err_unmap:
 621         dma_buf_unmap_attachment(attachment, sgt, dma_dir);
 622 err_detach:
 623         dma_buf_detach(dmabuf, attachment);
 624 err_put:
 625         dma_buf_put(dmabuf);
 626
 627         return err;
 628 }
 629
 630 static int tegra_vde_attach_dmabufs_to_frame(struct device *dev,
 631                                              struct video_frame *frame,
 632                                              struct tegra_vde_h264_frame *src,
 633                                              enum dma_data_direction dma_dir,
 634                                              bool baseline_profile,
 635                                              size_t lsize, size_t csize)
 636 {
 637         int err;
 638
 639         err = tegra_vde_attach_dmabuf(dev, src->y_fd,
 640                                       src->y_offset, lsize, SZ_256,
 641                                       &frame->y_dmabuf_attachment,
 642                                       &frame->y_addr,
 643                                       &frame->y_sgt,
 644                                       NULL, dma_dir);
 645         if (err)
 646                 return err;
 647
 648         err = tegra_vde_attach_dmabuf(dev, src->cb_fd,
 649                                       src->cb_offset, csize, SZ_256,
 650                                       &frame->cb_dmabuf_attachment,
 651                                       &frame->cb_addr,
 652                                       &frame->cb_sgt,
 653                                       NULL, dma_dir);
 654         if (err)
 655                 goto err_release_y;
 656
 657         err = tegra_vde_attach_dmabuf(dev, src->cr_fd,
 658                                       src->cr_offset, csize, SZ_256,
 659                                       &frame->cr_dmabuf_attachment,
 660                                       &frame->cr_addr,
 661                                       &frame->cr_sgt,
 662                                       NULL, dma_dir);
 663         if (err)
 664                 goto err_release_cb;
 665
 666         if (baseline_profile) {
 667                 frame->aux_addr = 0x64DEAD00;
 668                 return 0;
 669         }
 670
 671         err = tegra_vde_attach_dmabuf(dev, src->aux_fd,
 672                                       src->aux_offset, csize, SZ_256,
 673                                       &frame->aux_dmabuf_attachment,
 674                                       &frame->aux_addr,
 675                                       &frame->aux_sgt,
 676                                       NULL, dma_dir);
 677         if (err)
 678                 goto err_release_cr;
 679
 680         return 0;
 681
 682 err_release_cr:
 683         tegra_vde_detach_and_put_dmabuf(frame->cr_dmabuf_attachment,
 684                                         frame->cr_sgt, dma_dir);
 685 err_release_cb:
 686         tegra_vde_detach_and_put_dmabuf(frame->cb_dmabuf_attachment,
 687                                         frame->cb_sgt, dma_dir);
 688 err_release_y:
 689         tegra_vde_detach_and_put_dmabuf(frame->y_dmabuf_attachment,
 690                                         frame->y_sgt, dma_dir);
 691
 692         return err;
 693 }
 694
 695 static void tegra_vde_release_frame_dmabufs(struct video_frame *frame,
 696                                             enum dma_data_direction dma_dir,
 697                                             bool baseline_profile)
 698 {
 699         if (!baseline_profile)
 700                 tegra_vde_detach_and_put_dmabuf(frame->aux_dmabuf_attachment,
 701                                                 frame->aux_sgt, dma_dir);
 702
 703         tegra_vde_detach_and_put_dmabuf(frame->cr_dmabuf_attachment,
 704                                         frame->cr_sgt, dma_dir);
 705
 706         tegra_vde_detach_and_put_dmabuf(frame->cb_dmabuf_attachment,
 707                                         frame->cb_sgt, dma_dir);
 708
 709         tegra_vde_detach_and_put_dmabuf(frame->y_dmabuf_attachment,
 710                                         frame->y_sgt, dma_dir);
 711 }
 712
 713 static int tegra_vde_validate_frame(struct device *dev,
 714                                     struct tegra_vde_h264_frame *frame)
 715 {
 716         if (frame->frame_num > 0x7FFFFF) {
 717                 dev_err(dev, "Bad frame_num %u\n", frame->frame_num);
 718                 return -EINVAL;
 719         }
 720
 721         return 0;
 722 }
 723
 724 static int tegra_vde_validate_h264_ctx(struct device *dev,
 725                                        struct tegra_vde_h264_decoder_ctx *ctx)
 726 {
 727         if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) {
 728                 dev_err(dev, "Bad DPB size %u\n", ctx->dpb_frames_nb);
 729                 return -EINVAL;
 730         }
 731
 732         if (ctx->level_idc > 15) {
 733                 dev_err(dev, "Bad level value %u\n", ctx->level_idc);
 734                 return -EINVAL;
 735         }
 736
 737         if (ctx->pic_init_qp > 52) {
 738                 dev_err(dev, "Bad pic_init_qp value %u\n", ctx->pic_init_qp);
 739                 return -EINVAL;
 740         }
 741
 742         if (ctx->log2_max_pic_order_cnt_lsb > 16) {
 743                 dev_err(dev, "Bad log2_max_pic_order_cnt_lsb value %u\n",
 744                         ctx->log2_max_pic_order_cnt_lsb);
 745                 return -EINVAL;
 746         }
 747
 748         if (ctx->log2_max_frame_num > 16) {
 749                 dev_err(dev, "Bad log2_max_frame_num value %u\n",
 750                         ctx->log2_max_frame_num);
 751                 return -EINVAL;
 752         }
 753
 754         if (ctx->chroma_qp_index_offset > 31) {
 755                 dev_err(dev, "Bad chroma_qp_index_offset value %u\n",
 756                         ctx->chroma_qp_index_offset);
 757                 return -EINVAL;
 758         }
 759
 760         if (ctx->pic_order_cnt_type > 2) {
 761                 dev_err(dev, "Bad pic_order_cnt_type value %u\n",
 762                         ctx->pic_order_cnt_type);
 763                 return -EINVAL;
 764         }
 765
 766         if (ctx->num_ref_idx_l0_active_minus1 > 15) {
 767                 dev_err(dev, "Bad num_ref_idx_l0_active_minus1 value %u\n",
 768                         ctx->num_ref_idx_l0_active_minus1);
 769                 return -EINVAL;
 770         }
 771
 772         if (ctx->num_ref_idx_l1_active_minus1 > 15) {
 773                 dev_err(dev, "Bad num_ref_idx_l1_active_minus1 value %u\n",
 774                         ctx->num_ref_idx_l1_active_minus1);
 775                 return -EINVAL;
 776         }
 777
 778         if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) {
 779                 dev_err(dev, "Bad pic_width_in_mbs value %u\n",
 780                         ctx->pic_width_in_mbs);
 781                 return -EINVAL;
 782         }
 783
 784         if (!ctx->pic_height_in_mbs || ctx->pic_height_in_mbs > 127) {
 785                 dev_err(dev, "Bad pic_height_in_mbs value %u\n",
 786                         ctx->pic_height_in_mbs);
 787                 return -EINVAL;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static int tegra_vde_ioctl_decode_h264(struct tegra_vde *vde,
 794                                        unsigned long vaddr)
 795 {
 796         struct device *dev = vde->miscdev.parent;
 797         struct tegra_vde_h264_decoder_ctx ctx;
 798         struct tegra_vde_h264_frame frames[17];
 799         struct tegra_vde_h264_frame __user *frames_user;
 800         struct video_frame *dpb_frames;
 801         struct dma_buf_attachment *bitstream_data_dmabuf_attachment;
 802         struct sg_table *bitstream_sgt;
 803         enum dma_data_direction dma_dir;
 804         dma_addr_t bitstream_data_addr;
 805         dma_addr_t bsev_ptr;
 806         size_t lsize, csize;
 807         size_t bitstream_data_size;
 808         unsigned int macroblocks_nb;
 809         unsigned int read_bytes;
 810         unsigned int cstride;
 811         unsigned int i;
 812         long timeout;
 813         int ret, err;
 814
 815         if (copy_from_user(&ctx, (void __user *)vaddr, sizeof(ctx)))
 816                 return -EFAULT;
 817
 818         ret = tegra_vde_validate_h264_ctx(dev, &ctx);
 819         if (ret)
 820                 return ret;
 821
 822         ret = tegra_vde_attach_dmabuf(dev, ctx.bitstream_data_fd,
 823                                       ctx.bitstream_data_offset,
 824                                       SZ_16K, SZ_16K,
 825                                       &bitstream_data_dmabuf_attachment,
 826                                       &bitstream_data_addr,
 827                                       &bitstream_sgt,
 828                                       &bitstream_data_size,
 829                                       DMA_TO_DEVICE);
 830         if (ret)
 831                 return ret;
 832
 833         dpb_frames = kcalloc(ctx.dpb_frames_nb, sizeof(*dpb_frames),
 834                              GFP_KERNEL);
 835         if (!dpb_frames) {
 836                 ret = -ENOMEM;
 837                 goto release_bitstream_dmabuf;
 838         }
 839
 840         macroblocks_nb = ctx.pic_width_in_mbs * ctx.pic_height_in_mbs;
 841         frames_user = u64_to_user_ptr(ctx.dpb_frames_ptr);
 842
 843         if (copy_from_user(frames, frames_user,
 844                            ctx.dpb_frames_nb * sizeof(*frames))) {
 845                 ret = -EFAULT;
 846                 goto free_dpb_frames;
 847         }
 848
 849         cstride = ALIGN(ctx.pic_width_in_mbs * 8, 16);
 850         csize = cstride * ctx.pic_height_in_mbs * 8;
 851         lsize = macroblocks_nb * 256;
 852
 853         for (i = 0; i < ctx.dpb_frames_nb; i++) {
 854                 ret = tegra_vde_validate_frame(dev, &frames[i]);
 855                 if (ret)
 856                         goto release_dpb_frames;
 857
 858                 dpb_frames[i].flags = frames[i].flags;
 859                 dpb_frames[i].frame_num = frames[i].frame_num;
 860
 861                 dma_dir = (i == 0) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 862
 863                 ret = tegra_vde_attach_dmabufs_to_frame(dev, &dpb_frames[i],
 864                                                         &frames[i], dma_dir,
 865                                                         ctx.baseline_profile,
 866                                                         lsize, csize);
 867                 if (ret)
 868                         goto release_dpb_frames;
 869         }
 870
 871         ret = mutex_lock_interruptible(&vde->lock);
 872         if (ret)
 873                 goto release_dpb_frames;
 874
 875         ret = pm_runtime_get_sync(dev);
 876         if (ret < 0)
 877                 goto unlock;
 878
 879         /*
 880          * We rely on the VDE registers reset value, otherwise VDE
 881          * causes bus lockup.
 882          */
 883         ret = reset_control_assert(vde->rst_mc);
 884         if (ret) {
 885                 dev_err(dev, "DEC start: Failed to assert MC reset: %d\n",
 886                         ret);
 887                 goto put_runtime_pm;
 888         }
 889
 890         ret = reset_control_reset(vde->rst);
 891         if (ret) {
 892                 dev_err(dev, "DEC start: Failed to reset HW: %d\n", ret);
 893                 goto put_runtime_pm;
 894         }
 895
 896         ret = reset_control_deassert(vde->rst_mc);
 897         if (ret) {
 898                 dev_err(dev, "DEC start: Failed to deassert MC reset: %d\n",
 899                         ret);
 900                 goto put_runtime_pm;
 901         }
 902
 903         ret = tegra_vde_setup_hw_context(vde, &ctx, dpb_frames,
 904                                          bitstream_data_addr,
 905                                          bitstream_data_size,
 906                                          macroblocks_nb);
 907         if (ret)
 908                 goto put_runtime_pm;
 909
 910         tegra_vde_decode_frame(vde, macroblocks_nb);
 911
 912         timeout = wait_for_completion_interruptible_timeout(
 913                         &vde->decode_completion, msecs_to_jiffies(1000));
 914         if (timeout == 0) {
 915                 bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10);
 916                 macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF;
 917                 read_bytes = bsev_ptr ? bsev_ptr - bitstream_data_addr : 0;
 918
 919                 dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n",
 920                         read_bytes, macroblocks_nb);
 921
 922                 ret = -EIO;
 923         } else if (timeout < 0) {
 924                 ret = timeout;
 925         }
 926
 927         /*
 928          * At first reset memory client to avoid resetting VDE HW in the
 929          * middle of DMA which could result into memory corruption or hang
 930          * the whole system.
 931          */
 932         err = reset_control_assert(vde->rst_mc);
 933         if (err)
 934                 dev_err(dev, "DEC end: Failed to assert MC reset: %d\n", err);
 935
 936         err = reset_control_assert(vde->rst);
 937         if (err)
 938                 dev_err(dev, "DEC end: Failed to assert HW reset: %d\n", err);
 939
 940 put_runtime_pm:
 941         pm_runtime_mark_last_busy(dev);
 942         pm_runtime_put_autosuspend(dev);
 943
 944 unlock:
 945         mutex_unlock(&vde->lock);
 946
 947 release_dpb_frames:
 948         while (i--) {
 949                 dma_dir = (i == 0) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 950
 951                 tegra_vde_release_frame_dmabufs(&dpb_frames[i], dma_dir,
 952                                                 ctx.baseline_profile);
 953         }
 954
 955 free_dpb_frames:
 956         kfree(dpb_frames);
 957
 958 release_bitstream_dmabuf:
 959         tegra_vde_detach_and_put_dmabuf(bitstream_data_dmabuf_attachment,
 960                                         bitstream_sgt, DMA_TO_DEVICE);
 961
 962         return ret;
 963 }
 964
 965 static long tegra_vde_unlocked_ioctl(struct file *filp,
 966                                      unsigned int cmd, unsigned long arg)
 967 {
 968         struct miscdevice *miscdev = filp->private_data;
 969         struct tegra_vde *vde = container_of(miscdev, struct tegra_vde,
 970                                              miscdev);
 971
 972         switch (cmd) {
 973         case TEGRA_VDE_IOCTL_DECODE_H264:
 974                 return tegra_vde_ioctl_decode_h264(vde, arg);
 975         }
 976
 977         dev_err(miscdev->parent, "Invalid IOCTL command %u\n", cmd);
 978
 979         return -ENOTTY;
 980 }
 981
 982 static const struct file_operations tegra_vde_fops = {
 983         .owner          = THIS_MODULE,
 984         .unlocked_ioctl = tegra_vde_unlocked_ioctl,
 985 };
 986
 987 static irqreturn_t tegra_vde_isr(int irq, void *data)
 988 {
 989         struct tegra_vde *vde = data;
 990
 991         if (completion_done(&vde->decode_completion))
 992                 return IRQ_NONE;
 993
 994         tegra_vde_set_bits(vde, 0, vde->frameid, 0x208);
 995         complete(&vde->decode_completion);
 996
 997         return IRQ_HANDLED;
 998 }
 999
1000 static int tegra_vde_runtime_suspend(struct device *dev)
1001 {
1002         struct tegra_vde *vde = dev_get_drvdata(dev);
1003         int err;
1004
1005         err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC);
1006         if (err) {
1007                 dev_err(dev, "Failed to power down HW: %d\n", err);
1008                 return err;
1009         }
1010
1011         clk_disable_unprepare(vde->clk);
1012
1013         return 0;
1014 }
1015
1016 static int tegra_vde_runtime_resume(struct device *dev)
1017 {
1018         struct tegra_vde *vde = dev_get_drvdata(dev);
1019         int err;
1020
1021         err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC,
1022                                                 vde->clk, vde->rst);
1023         if (err) {
1024                 dev_err(dev, "Failed to power up HW : %d\n", err);
1025                 return err;
1026         }
1027
1028         return 0;
1029 }
1030
1031 static int tegra_vde_probe(struct platform_device *pdev)
1032 {
1033         struct device *dev = &pdev->dev;
1034         struct resource *regs;
1035         struct tegra_vde *vde;
1036         int irq, err;
1037
1038         vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL);
1039         if (!vde)
1040                 return -ENOMEM;
1041
1042         platform_set_drvdata(pdev, vde);
1043
1044         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sxe");
1045         if (!regs)
1046                 return -ENODEV;
1047
1048         vde->sxe = devm_ioremap_resource(dev, regs);
1049         if (IS_ERR(vde->sxe))
1050                 return PTR_ERR(vde->sxe);
1051
1052         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bsev");
1053         if (!regs)
1054                 return -ENODEV;
1055
1056         vde->bsev = devm_ioremap_resource(dev, regs);
1057         if (IS_ERR(vde->bsev))
1058                 return PTR_ERR(vde->bsev);
1059
1060         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbe");
1061         if (!regs)
1062                 return -ENODEV;
1063
1064         vde->mbe = devm_ioremap_resource(dev, regs);
1065         if (IS_ERR(vde->mbe))
1066                 return PTR_ERR(vde->mbe);
1067
1068         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe");
1069         if (!regs)
1070                 return -ENODEV;
1071
1072         vde->ppe = devm_ioremap_resource(dev, regs);
1073         if (IS_ERR(vde->ppe))
1074                 return PTR_ERR(vde->ppe);
1075
1076         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mce");
1077         if (!regs)
1078                 return -ENODEV;
1079
1080         vde->mce = devm_ioremap_resource(dev, regs);
1081         if (IS_ERR(vde->mce))
1082                 return PTR_ERR(vde->mce);
1083
1084         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tfe");
1085         if (!regs)
1086                 return -ENODEV;
1087
1088         vde->tfe = devm_ioremap_resource(dev, regs);
1089         if (IS_ERR(vde->tfe))
1090                 return PTR_ERR(vde->tfe);
1091
1092         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppb");
1093         if (!regs)
1094                 return -ENODEV;
1095
1096         vde->ppb = devm_ioremap_resource(dev, regs);
1097         if (IS_ERR(vde->ppb))
1098                 return PTR_ERR(vde->ppb);
1099
1100         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vdma");
1101         if (!regs)
1102                 return -ENODEV;
1103
1104         vde->vdma = devm_ioremap_resource(dev, regs);
1105         if (IS_ERR(vde->vdma))
1106                 return PTR_ERR(vde->vdma);
1107
1108         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "frameid");
1109         if (!regs)
1110                 return -ENODEV;
1111
1112         vde->frameid = devm_ioremap_resource(dev, regs);
1113         if (IS_ERR(vde->frameid))
1114                 return PTR_ERR(vde->frameid);
1115
1116         vde->clk = devm_clk_get(dev, NULL);
1117         if (IS_ERR(vde->clk)) {
1118                 err = PTR_ERR(vde->clk);
1119                 dev_err(dev, "Could not get VDE clk %d\n", err);
1120                 return err;
1121         }
1122
1123         vde->rst = devm_reset_control_get(dev, NULL);
1124         if (IS_ERR(vde->rst)) {
1125                 err = PTR_ERR(vde->rst);
1126                 dev_err(dev, "Could not get VDE reset %d\n", err);
1127                 return err;
1128         }
1129
1130         vde->rst_mc = devm_reset_control_get_optional(dev, "mc");
1131         if (IS_ERR(vde->rst_mc)) {
1132                 err = PTR_ERR(vde->rst_mc);
1133                 dev_err(dev, "Could not get MC reset %d\n", err);
1134                 return err;
1135         }
1136
1137         irq = platform_get_irq_byname(pdev, "sync-token");
1138         if (irq < 0)
1139                 return irq;
1140
1141         err = devm_request_irq(dev, irq, tegra_vde_isr, 0,
1142                                dev_name(dev), vde);
1143         if (err) {
1144                 dev_err(dev, "Could not request IRQ %d\n", err);
1145                 return err;
1146         }
1147
1148         vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0);
1149         if (!vde->iram_pool) {
1150                 dev_err(dev, "Could not get IRAM pool\n");
1151                 return -EPROBE_DEFER;
1152         }
1153
1154         vde->iram = gen_pool_dma_alloc(vde->iram_pool,
1155                                        gen_pool_size(vde->iram_pool),
1156                                        &vde->iram_lists_addr);
1157         if (!vde->iram) {
1158                 dev_err(dev, "Could not reserve IRAM\n");
1159                 return -ENOMEM;
1160         }
1161
1162         mutex_init(&vde->lock);
1163         init_completion(&vde->decode_completion);
1164
1165         vde->miscdev.minor = MISC_DYNAMIC_MINOR;
1166         vde->miscdev.name = "tegra_vde";
1167         vde->miscdev.fops = &tegra_vde_fops;
1168         vde->miscdev.parent = dev;
1169
1170         err = misc_register(&vde->miscdev);
1171         if (err) {
1172                 dev_err(dev, "Failed to register misc device: %d\n", err);
1173                 goto err_gen_free;
1174         }
1175
1176         pm_runtime_enable(dev);
1177         pm_runtime_use_autosuspend(dev);
1178         pm_runtime_set_autosuspend_delay(dev, 300);
1179
1180         if (!pm_runtime_enabled(dev)) {
1181                 err = tegra_vde_runtime_resume(dev);
1182                 if (err)
1183                         goto err_misc_unreg;
1184         }
1185
1186         return 0;
1187
1188 err_misc_unreg:
1189         misc_deregister(&vde->miscdev);
1190
1191 err_gen_free:
1192         gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
1193                       gen_pool_size(vde->iram_pool));
1194
1195         return err;
1196 }
1197
1198 static int tegra_vde_remove(struct platform_device *pdev)
1199 {
1200         struct tegra_vde *vde = platform_get_drvdata(pdev);
1201         struct device *dev = &pdev->dev;
1202         int err;
1203
1204         if (!pm_runtime_enabled(dev)) {
1205                 err = tegra_vde_runtime_suspend(dev);
1206                 if (err)
1207                         return err;
1208         }
1209
1210         pm_runtime_dont_use_autosuspend(dev);
1211         pm_runtime_disable(dev);
1212
1213         misc_deregister(&vde->miscdev);
1214
1215         gen_pool_free(vde->iram_pool, (unsigned long)vde->iram,
1216                       gen_pool_size(vde->iram_pool));
1217
1218         return 0;
1219 }
1220
1221 #ifdef CONFIG_PM_SLEEP
1222 static int tegra_vde_pm_suspend(struct device *dev)
1223 {
1224         struct tegra_vde *vde = dev_get_drvdata(dev);
1225         int err;
1226
1227         mutex_lock(&vde->lock);
1228
1229         err = pm_runtime_force_suspend(dev);
1230         if (err < 0)
1231                 return err;
1232
1233         return 0;
1234 }
1235
1236 static int tegra_vde_pm_resume(struct device *dev)
1237 {
1238         struct tegra_vde *vde = dev_get_drvdata(dev);
1239         int err;
1240
1241         err = pm_runtime_force_resume(dev);
1242         if (err < 0)
1243                 return err;
1244
1245         mutex_unlock(&vde->lock);
1246
1247         return 0;
1248 }
1249 #endif
1250
1251 static const struct dev_pm_ops tegra_vde_pm_ops = {
1252         SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend,
1253                            tegra_vde_runtime_resume,
1254                            NULL)
1255         SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend,
1256                                 tegra_vde_pm_resume)
1257 };
1258
1259 static const struct of_device_id tegra_vde_of_match[] = {
1260         { .compatible = "nvidia,tegra20-vde", },
1261         { },
1262 };
1263 MODULE_DEVICE_TABLE(of, tegra_vde_of_match);
1264
1265 static struct platform_driver tegra_vde_driver = {
1266         .probe          = tegra_vde_probe,
1267         .remove         = tegra_vde_remove,
1268         .driver         = {
1269                 .name           = "tegra-vde",
1270                 .of_match_table = tegra_vde_of_match,
1271                 .pm             = &tegra_vde_pm_ops,
1272         },
1273 };
1274 module_platform_driver(tegra_vde_driver);
1275
1276 MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver");
1277 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
1278 MODULE_LICENSE("GPL");