1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Raspberry Pi HEVC driver
5 * Copyright (C) 2020 Raspberry Pi (Trading) Ltd
7 * Based on the Cedrus VPU driver, that is:
9 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
10 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
11 * Copyright (C) 2018 Bootlin
17 struct rpivid_hw_irq_ent {
18 struct rpivid_hw_irq_ent *next;
19 rpivid_irq_callback cb;
23 /* Phase 1 Register offsets */
29 #define RPI_TILESTART 16
30 #define RPI_TILEEND 20
31 #define RPI_SLICESTART 24
38 #define RPI_CONTROL 52
40 #define RPI_VERSION 60
43 #define RPI_BFCONTROL 72
44 #define RPI_BFSTATUS 76
45 #define RPI_PUWBASE 80
46 #define RPI_PUWSTRIDE 84
47 #define RPI_COEFFWBASE 88
48 #define RPI_COEFFWSTRIDE 92
49 #define RPI_SLICECMDS 96
50 #define RPI_BEGINTILEEND 100
51 #define RPI_TRANSFER 104
52 #define RPI_CFBASE 108
54 #define RPI_CFSTATUS 116
56 /* Phase 2 Register offsets */
58 #define RPI_PURBASE 0x8000
59 #define RPI_PURSTRIDE 0x8004
60 #define RPI_COEFFRBASE 0x8008
61 #define RPI_COEFFRSTRIDE 0x800C
62 #define RPI_NUMROWS 0x8010
63 #define RPI_CONFIG2 0x8014
64 #define RPI_OUTYBASE 0x8018
65 #define RPI_OUTYSTRIDE 0x801C
66 #define RPI_OUTCBASE 0x8020
67 #define RPI_OUTCSTRIDE 0x8024
68 #define RPI_STATUS2 0x8028
69 #define RPI_FRAMESIZE 0x802C
70 #define RPI_MVBASE 0x8030
71 #define RPI_MVSTRIDE 0x8034
72 #define RPI_COLBASE 0x8038
73 #define RPI_COLSTRIDE 0x803C
74 #define RPI_CURRPOC 0x8040
77 * Write a general register value
78 * Order is unimportant
80 static inline void apb_write(const struct rpivid_dev * const dev,
81 const unsigned int offset, const u32 val)
83 writel_relaxed(val, dev->base_h265 + offset);
86 /* Write the final register value that actually starts the phase */
87 static inline void apb_write_final(const struct rpivid_dev * const dev,
88 const unsigned int offset, const u32 val)
90 writel(val, dev->base_h265 + offset);
93 static inline u32 apb_read(const struct rpivid_dev * const dev,
94 const unsigned int offset)
96 return readl(dev->base_h265 + offset);
99 static inline void irq_write(const struct rpivid_dev * const dev,
100 const unsigned int offset, const u32 val)
102 writel(val, dev->base_irq + offset);
105 static inline u32 irq_read(const struct rpivid_dev * const dev,
106 const unsigned int offset)
108 return readl(dev->base_irq + offset);
111 static inline void apb_write_vc_addr(const struct rpivid_dev * const dev,
112 const unsigned int offset,
115 apb_write(dev, offset, (u32)(a >> 6));
118 static inline void apb_write_vc_addr_final(const struct rpivid_dev * const dev,
119 const unsigned int offset,
122 apb_write_final(dev, offset, (u32)(a >> 6));
125 static inline void apb_write_vc_len(const struct rpivid_dev * const dev,
126 const unsigned int offset,
127 const unsigned int x)
129 apb_write(dev, offset, (x + 63) >> 6);
132 /* *ARG_IC_ICTRL - Interrupt control for ARGON Core*
133 * Offset (byte space) = 40'h2b10000
134 * Physical Address (byte space) = 40'h7eb10000
135 * Verilog Macro Address = `ARG_IC_REG_START + `ARGON_INTCTRL_ICTRL
136 * Reset Value = 32'b100x100x_100xxxxx_xxxxxxx0_x100x100
137 * Access = RW (32-bit only)
138 * Interrupt control logic for ARGON Core.
140 #define ARG_IC_ICTRL 0
142 /* acc=LWC ACTIVE1_INT FIELD ACCESS: LWC
145 * This is set and held when an hevc_active1 interrupt edge is detected
146 * The polarity of the edge is set by the ACTIVE1_EDGE field
147 * Write a 1 to this bit to clear down the latched interrupt
148 * The latched interrupt is only enabled out onto the interrupt line if
150 * Reset value is *0* decimal.
152 #define ARG_IC_ICTRL_ACTIVE1_INT_SET BIT(0)
154 /* ACTIVE1_EDGE Sets the polarity of the interrupt edge detection logic
155 * This logic detects edges of the hevc_active1 line from the argon core
156 * 0 = negedge, 1 = posedge
157 * Reset value is *0* decimal.
159 #define ARG_IC_ICTRL_ACTIVE1_EDGE_SET BIT(1)
161 /* ACTIVE1_EN Enables ACTIVE1_INT out onto the argon interrupt line.
162 * If this isn't set, the interrupt logic will work but no interrupt will be
163 * set to the interrupt controller
164 * Reset value is *1* decimal.
166 * [JC] The above appears to be a lie - if unset then b0 is never set
168 #define ARG_IC_ICTRL_ACTIVE1_EN_SET BIT(2)
170 /* acc=RO ACTIVE1_STATUS FIELD ACCESS: RO
172 * The current status of the hevc_active1 signal
174 #define ARG_IC_ICTRL_ACTIVE1_STATUS_SET BIT(3)
176 /* acc=LWC ACTIVE2_INT FIELD ACCESS: LWC
179 * This is set and held when an hevc_active2 interrupt edge is detected
180 * The polarity of the edge is set by the ACTIVE2_EDGE field
181 * Write a 1 to this bit to clear down the latched interrupt
182 * The latched interrupt is only enabled out onto the interrupt line if
184 * Reset value is *0* decimal.
186 #define ARG_IC_ICTRL_ACTIVE2_INT_SET BIT(4)
188 /* ACTIVE2_EDGE Sets the polarity of the interrupt edge detection logic
189 * This logic detects edges of the hevc_active2 line from the argon core
190 * 0 = negedge, 1 = posedge
191 * Reset value is *0* decimal.
193 #define ARG_IC_ICTRL_ACTIVE2_EDGE_SET BIT(5)
195 /* ACTIVE2_EN Enables ACTIVE2_INT out onto the argon interrupt line.
196 * If this isn't set, the interrupt logic will work but no interrupt will be
197 * set to the interrupt controller
198 * Reset value is *1* decimal.
200 #define ARG_IC_ICTRL_ACTIVE2_EN_SET BIT(6)
202 /* acc=RO ACTIVE2_STATUS FIELD ACCESS: RO
204 * The current status of the hevc_active2 signal
206 #define ARG_IC_ICTRL_ACTIVE2_STATUS_SET BIT(7)
208 /* TEST_INT Forces the argon int high for test purposes.
209 * Reset value is *0* decimal.
211 #define ARG_IC_ICTRL_TEST_INT BIT(8)
212 #define ARG_IC_ICTRL_SPARE BIT(9)
214 /* acc=RO VP9_INTERRUPT_STATUS FIELD ACCESS: RO
216 * The current status of the vp9_interrupt signal
218 #define ARG_IC_ICTRL_VP9_INTERRUPT_STATUS BIT(10)
220 /* AIO_INT_ENABLE 1 = Or the AIO int in with the Argon int so the VPU can see
222 * 0 = the AIO int is masked. (It should still be connected to the GIC though).
224 #define ARG_IC_ICTRL_AIO_INT_ENABLE BIT(20)
225 #define ARG_IC_ICTRL_H264_ACTIVE_INT BIT(21)
226 #define ARG_IC_ICTRL_H264_ACTIVE_EDGE BIT(22)
227 #define ARG_IC_ICTRL_H264_ACTIVE_EN BIT(23)
228 #define ARG_IC_ICTRL_H264_ACTIVE_STATUS BIT(24)
229 #define ARG_IC_ICTRL_H264_INTERRUPT_INT BIT(25)
230 #define ARG_IC_ICTRL_H264_INTERRUPT_EDGE BIT(26)
231 #define ARG_IC_ICTRL_H264_INTERRUPT_EN BIT(27)
233 /* acc=RO H264_INTERRUPT_STATUS FIELD ACCESS: RO
235 * The current status of the h264_interrupt signal
237 #define ARG_IC_ICTRL_H264_INTERRUPT_STATUS BIT(28)
239 /* acc=LWC VP9_INTERRUPT_INT FIELD ACCESS: LWC
242 * This is set and held when an vp9_interrupt interrupt edge is detected
243 * The polarity of the edge is set by the VP9_INTERRUPT_EDGE field
244 * Write a 1 to this bit to clear down the latched interrupt
245 * The latched interrupt is only enabled out onto the interrupt line if
246 * VP9_INTERRUPT_EN is set
247 * Reset value is *0* decimal.
249 #define ARG_IC_ICTRL_VP9_INTERRUPT_INT BIT(29)
251 /* VP9_INTERRUPT_EDGE Sets the polarity of the interrupt edge detection logic
252 * This logic detects edges of the vp9_interrupt line from the argon h264 core
253 * 0 = negedge, 1 = posedge
254 * Reset value is *0* decimal.
256 #define ARG_IC_ICTRL_VP9_INTERRUPT_EDGE BIT(30)
258 /* VP9_INTERRUPT_EN Enables VP9_INTERRUPT_INT out onto the argon interrupt line.
259 * If this isn't set, the interrupt logic will work but no interrupt will be
260 * set to the interrupt controller
261 * Reset value is *1* decimal.
263 #define ARG_IC_ICTRL_VP9_INTERRUPT_EN BIT(31)
265 /* Bits 19:12, 11 reserved - read ?, write 0 */
266 #define ARG_IC_ICTRL_SET_ZERO_MASK ((0xff << 12) | BIT(11))
269 #define ARG_IC_ICTRL_ALL_IRQ_MASK (\
270 ARG_IC_ICTRL_VP9_INTERRUPT_INT |\
271 ARG_IC_ICTRL_H264_INTERRUPT_INT |\
272 ARG_IC_ICTRL_ACTIVE1_INT_SET |\
273 ARG_IC_ICTRL_ACTIVE2_INT_SET)
275 /* Regulate claim Q */
276 void rpivid_hw_irq_active1_enable_claim(struct rpivid_dev *dev,
278 /* Auto release once all CBs called */
279 void rpivid_hw_irq_active1_claim(struct rpivid_dev *dev,
280 struct rpivid_hw_irq_ent *ient,
281 rpivid_irq_callback ready_cb, void *ctx);
282 /* May only be called in claim cb */
283 void rpivid_hw_irq_active1_irq(struct rpivid_dev *dev,
284 struct rpivid_hw_irq_ent *ient,
285 rpivid_irq_callback irq_cb, void *ctx);
286 /* May only be called in irq cb */
287 void rpivid_hw_irq_active1_thread(struct rpivid_dev *dev,
288 struct rpivid_hw_irq_ent *ient,
289 rpivid_irq_callback thread_cb, void *ctx);
291 /* Auto release once all CBs called */
292 void rpivid_hw_irq_active2_claim(struct rpivid_dev *dev,
293 struct rpivid_hw_irq_ent *ient,
294 rpivid_irq_callback ready_cb, void *ctx);
295 /* May only be called in claim cb */
296 void rpivid_hw_irq_active2_irq(struct rpivid_dev *dev,
297 struct rpivid_hw_irq_ent *ient,
298 rpivid_irq_callback irq_cb, void *ctx);
300 int rpivid_hw_probe(struct rpivid_dev *dev);
301 void rpivid_hw_remove(struct rpivid_dev *dev);