drivers/staging/media/imx/imx8mq-mipi-csi2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NXP i.MX8MQ SoC series MIPI-CSI2 receiver driver
   4  *
   5  * Copyright (C) 2021 Purism SPC
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/errno.h>
  12 #include <linux/interconnect.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/reset.h>
  26 #include <linux/spinlock.h>
  27
  28 #include <media/v4l2-common.h>
  29 #include <media/v4l2-device.h>
  30 #include <media/v4l2-fwnode.h>
  31 #include <media/v4l2-mc.h>
  32 #include <media/v4l2-subdev.h>
  33
  34 #define MIPI_CSI2_DRIVER_NAME                   "imx8mq-mipi-csi2"
  35 #define MIPI_CSI2_SUBDEV_NAME                   MIPI_CSI2_DRIVER_NAME
  36
  37 #define MIPI_CSI2_PAD_SINK                      0
  38 #define MIPI_CSI2_PAD_SOURCE                    1
  39 #define MIPI_CSI2_PADS_NUM                      2
  40
  41 #define MIPI_CSI2_DEF_PIX_WIDTH                 640
  42 #define MIPI_CSI2_DEF_PIX_HEIGHT                480
  43
  44 /* Register map definition */
  45
  46 /* i.MX8MQ CSI-2 controller CSR */
  47 #define CSI2RX_CFG_NUM_LANES                    0x100
  48 #define CSI2RX_CFG_DISABLE_DATA_LANES           0x104
  49 #define CSI2RX_BIT_ERR                          0x108
  50 #define CSI2RX_IRQ_STATUS                       0x10c
  51 #define CSI2RX_IRQ_MASK                         0x110
  52 #define CSI2RX_IRQ_MASK_ALL                     0x1ff
  53 #define CSI2RX_IRQ_MASK_ULPS_STATUS_CHANGE      0x8
  54 #define CSI2RX_ULPS_STATUS                      0x114
  55 #define CSI2RX_PPI_ERRSOT_HS                    0x118
  56 #define CSI2RX_PPI_ERRSOTSYNC_HS                0x11c
  57 #define CSI2RX_PPI_ERRESC                       0x120
  58 #define CSI2RX_PPI_ERRSYNCESC                   0x124
  59 #define CSI2RX_PPI_ERRCONTROL                   0x128
  60 #define CSI2RX_CFG_DISABLE_PAYLOAD_0            0x12c
  61 #define CSI2RX_CFG_VID_VC_IGNORE                0x180
  62 #define CSI2RX_CFG_VID_VC                       0x184
  63 #define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL        0x188
  64 #define CSI2RX_CFG_DISABLE_PAYLOAD_1            0x130
  65
  66 enum {
  67         ST_POWERED      = 1,
  68         ST_STREAMING    = 2,
  69         ST_SUSPENDED    = 4,
  70 };
  71
  72 enum imx8mq_mipi_csi_clk {
  73         CSI2_CLK_CORE,
  74         CSI2_CLK_ESC,
  75         CSI2_CLK_UI,
  76         CSI2_NUM_CLKS,
  77 };
  78
  79 static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
  80         [CSI2_CLK_CORE] = "core",
  81         [CSI2_CLK_ESC] = "esc",
  82         [CSI2_CLK_UI] = "ui",
  83 };
  84
  85 #define CSI2_NUM_CLKS   ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
  86
  87 #define GPR_CSI2_1_RX_ENABLE            BIT(13)
  88 #define GPR_CSI2_1_VID_INTFC_ENB        BIT(12)
  89 #define GPR_CSI2_1_HSEL                 BIT(10)
  90 #define GPR_CSI2_1_CONT_CLK_MODE        BIT(8)
  91 #define GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((x) & 0x3f) << 2)
  92
  93 /*
  94  * The send level configures the number of entries that must accumulate in
  95  * the Pixel FIFO before the data will be transferred to the video output.
  96  * The exact value needed for this configuration is dependent on the rate at
  97  * which the sensor transfers data to the CSI-2 Controller and the user
  98  * video clock.
  99  *
 100  * The calculation is the classical rate-in rate-out type of problem: If the
 101  * video bandwidth is 10% faster than the incoming mipi data and the video
 102  * line length is 500 pixels, then the fifo should be allowed to fill
 103  * 10% of the line length or 50 pixels. If the gap data is ok, then the level
 104  * can be set to 16 and ignored.
 105  */
 106 #define CSI2RX_SEND_LEVEL                       64
 107
 108 struct csi_state {
 109         struct device *dev;
 110         void __iomem *regs;
 111         struct clk_bulk_data clks[CSI2_NUM_CLKS];
 112         struct reset_control *rst;
 113         struct regulator *mipi_phy_regulator;
 114
 115         struct v4l2_subdev sd;
 116         struct media_pad pads[MIPI_CSI2_PADS_NUM];
 117         struct v4l2_async_notifier notifier;
 118         struct v4l2_subdev *src_sd;
 119
 120         struct v4l2_mbus_config_mipi_csi2 bus;
 121
 122         struct mutex lock; /* Protect state */
 123         u32 state;
 124
 125         struct regmap *phy_gpr;
 126         u8 phy_gpr_reg;
 127
 128         struct icc_path                 *icc_path;
 129         s32                             icc_path_bw;
 130 };
 131
 132 /* -----------------------------------------------------------------------------
 133  * Format helpers
 134  */
 135
 136 struct csi2_pix_format {
 137         u32 code;
 138         u8 width;
 139 };
 140
 141 static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
 142         /* RAW (Bayer and greyscale) formats. */
 143         {
 144                 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
 145                 .width = 8,
 146         }, {
 147                 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
 148                 .width = 8,
 149         }, {
 150                 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
 151                 .width = 8,
 152         }, {
 153                 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
 154                 .width = 8,
 155         }, {
 156                 .code = MEDIA_BUS_FMT_Y8_1X8,
 157                 .width = 8,
 158         }, {
 159                 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
 160                 .width = 10,
 161         }, {
 162                 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
 163                 .width = 10,
 164         }, {
 165                 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
 166                 .width = 10,
 167         }, {
 168                 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
 169                 .width = 10,
 170         }, {
 171                 .code = MEDIA_BUS_FMT_Y10_1X10,
 172                 .width = 10,
 173         }, {
 174                 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
 175                 .width = 12,
 176         }, {
 177                 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
 178                 .width = 12,
 179         }, {
 180                 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
 181                 .width = 12,
 182         }, {
 183                 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
 184                 .width = 12,
 185         }, {
 186                 .code = MEDIA_BUS_FMT_Y12_1X12,
 187                 .width = 12,
 188         }, {
 189                 .code = MEDIA_BUS_FMT_SBGGR14_1X14,
 190                 .width = 14,
 191         }, {
 192                 .code = MEDIA_BUS_FMT_SGBRG14_1X14,
 193                 .width = 14,
 194         }, {
 195                 .code = MEDIA_BUS_FMT_SGRBG14_1X14,
 196                 .width = 14,
 197         }, {
 198                 .code = MEDIA_BUS_FMT_SRGGB14_1X14,
 199                 .width = 14,
 200         },
 201         /* YUV formats */
 202         {
 203                 .code = MEDIA_BUS_FMT_YUYV8_1X16,
 204                 .width = 16,
 205         }, {
 206                 .code = MEDIA_BUS_FMT_UYVY8_1X16,
 207                 .width = 16,
 208         }
 209 };
 210
 211 static const struct csi2_pix_format *find_csi2_format(u32 code)
 212 {
 213         unsigned int i;
 214
 215         for (i = 0; i < ARRAY_SIZE(imx8mq_mipi_csi_formats); i++)
 216                 if (code == imx8mq_mipi_csi_formats[i].code)
 217                         return &imx8mq_mipi_csi_formats[i];
 218         return NULL;
 219 }
 220
 221 /* -----------------------------------------------------------------------------
 222  * Hardware configuration
 223  */
 224
 225 static inline void imx8mq_mipi_csi_write(struct csi_state *state, u32 reg, u32 val)
 226 {
 227         writel(val, state->regs + reg);
 228 }
 229
 230 static int imx8mq_mipi_csi_sw_reset(struct csi_state *state)
 231 {
 232         int ret;
 233
 234         /*
 235          * these are most likely self-clearing reset bits. to make it
 236          * more clear, the reset-imx7 driver should implement the
 237          * .reset() operation.
 238          */
 239         ret = reset_control_assert(state->rst);
 240         if (ret < 0) {
 241                 dev_err(state->dev, "Failed to assert resets: %d\n", ret);
 242                 return ret;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static void imx8mq_mipi_csi_set_params(struct csi_state *state)
 249 {
 250         int lanes = state->bus.num_data_lanes;
 251
 252         imx8mq_mipi_csi_write(state, CSI2RX_CFG_NUM_LANES, lanes - 1);
 253         imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES,
 254                               (0xf << lanes) & 0xf);
 255         imx8mq_mipi_csi_write(state, CSI2RX_IRQ_MASK, CSI2RX_IRQ_MASK_ALL);
 256         /*
 257          * 0x180 bit 0 controls the Virtual Channel behaviour: when set the
 258          * interface ignores the Virtual Channel (VC) field in received packets;
 259          * when cleared it causes the interface to only accept packets whose VC
 260          * matches the value to which VC is set at offset 0x184.
 261          */
 262         imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_VC_IGNORE, 1);
 263         imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL,
 264                               CSI2RX_SEND_LEVEL);
 265 }
 266
 267 static int imx8mq_mipi_csi_clk_enable(struct csi_state *state)
 268 {
 269         return clk_bulk_prepare_enable(CSI2_NUM_CLKS, state->clks);
 270 }
 271
 272 static void imx8mq_mipi_csi_clk_disable(struct csi_state *state)
 273 {
 274         clk_bulk_disable_unprepare(CSI2_NUM_CLKS, state->clks);
 275 }
 276
 277 static int imx8mq_mipi_csi_clk_get(struct csi_state *state)
 278 {
 279         unsigned int i;
 280
 281         for (i = 0; i < CSI2_NUM_CLKS; i++)
 282                 state->clks[i].id = imx8mq_mipi_csi_clk_id[i];
 283
 284         return devm_clk_bulk_get(state->dev, CSI2_NUM_CLKS, state->clks);
 285 }
 286
 287 static int imx8mq_mipi_csi_calc_hs_settle(struct csi_state *state,
 288                                           struct v4l2_subdev_state *sd_state,
 289                                           u32 *hs_settle)
 290 {
 291         s64 link_freq;
 292         u32 lane_rate;
 293         unsigned long esc_clk_rate;
 294         u32 min_ths_settle, max_ths_settle, ths_settle_ns, esc_clk_period_ns;
 295         const struct v4l2_mbus_framefmt *fmt;
 296         const struct csi2_pix_format *csi2_fmt;
 297
 298         /* Calculate the line rate from the pixel rate. */
 299
 300         fmt = v4l2_subdev_get_pad_format(&state->sd, sd_state, MIPI_CSI2_PAD_SINK);
 301         csi2_fmt = find_csi2_format(fmt->code);
 302
 303         link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler,
 304                                        csi2_fmt->width,
 305                                        state->bus.num_data_lanes * 2);
 306         if (link_freq < 0) {
 307                 dev_err(state->dev, "Unable to obtain link frequency: %d\n",
 308                         (int)link_freq);
 309                 return link_freq;
 310         }
 311
 312         lane_rate = link_freq * 2;
 313         if (lane_rate < 80000000 || lane_rate > 1500000000) {
 314                 dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate);
 315                 return -EINVAL;
 316         }
 317
 318         /*
 319          * The D-PHY specification requires Ths-settle to be in the range
 320          * 85ns + 6*UI to 140ns + 10*UI, with the unit interval UI being half
 321          * the clock period.
 322          *
 323          * The Ths-settle value is expressed in the hardware as a multiple of
 324          * the Esc clock period:
 325          *
 326          * Ths-settle = (PRG_RXHS_SETTLE + 1) * Tperiod of RxClkInEsc
 327          *
 328          * Due to the one cycle inaccuracy introduced by rounding, the
 329          * documentation recommends picking a value away from the boundaries.
 330          * Let's pick the average.
 331          */
 332         esc_clk_rate = clk_get_rate(state->clks[CSI2_CLK_ESC].clk);
 333         if (!esc_clk_rate) {
 334                 dev_err(state->dev, "Could not get esc clock rate.\n");
 335                 return -EINVAL;
 336         }
 337
 338         dev_dbg(state->dev, "esc clk rate: %lu\n", esc_clk_rate);
 339         esc_clk_period_ns = 1000000000 / esc_clk_rate;
 340
 341         min_ths_settle = 85 + 6 * 1000000 / (lane_rate / 1000);
 342         max_ths_settle = 140 + 10 * 1000000 / (lane_rate / 1000);
 343         ths_settle_ns = (min_ths_settle + max_ths_settle) / 2;
 344
 345         *hs_settle = ths_settle_ns / esc_clk_period_ns - 1;
 346
 347         dev_dbg(state->dev, "lane rate %u Ths_settle %u hs_settle %u\n",
 348                 lane_rate, ths_settle_ns, *hs_settle);
 349
 350         return 0;
 351 }
 352
 353 static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
 354                                         struct v4l2_subdev_state *sd_state)
 355 {
 356         int ret;
 357         u32 hs_settle = 0;
 358
 359         ret = imx8mq_mipi_csi_sw_reset(state);
 360         if (ret)
 361                 return ret;
 362
 363         imx8mq_mipi_csi_set_params(state);
 364         ret = imx8mq_mipi_csi_calc_hs_settle(state, sd_state, &hs_settle);
 365         if (ret)
 366                 return ret;
 367
 368         regmap_update_bits(state->phy_gpr,
 369                            state->phy_gpr_reg,
 370                            0x3fff,
 371                            GPR_CSI2_1_RX_ENABLE |
 372                            GPR_CSI2_1_VID_INTFC_ENB |
 373                            GPR_CSI2_1_HSEL |
 374                            GPR_CSI2_1_CONT_CLK_MODE |
 375                            GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
 376
 377         return 0;
 378 }
 379
 380 static void imx8mq_mipi_csi_stop_stream(struct csi_state *state)
 381 {
 382         imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES, 0xf);
 383 }
 384
 385 /* -----------------------------------------------------------------------------
 386  * V4L2 subdev operations
 387  */
 388
 389 static struct csi_state *mipi_sd_to_csi2_state(struct v4l2_subdev *sdev)
 390 {
 391         return container_of(sdev, struct csi_state, sd);
 392 }
 393
 394 static int imx8mq_mipi_csi_s_stream(struct v4l2_subdev *sd, int enable)
 395 {
 396         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 397         struct v4l2_subdev_state *sd_state;
 398         int ret = 0;
 399
 400         if (enable) {
 401                 ret = pm_runtime_resume_and_get(state->dev);
 402                 if (ret < 0)
 403                         return ret;
 404         }
 405
 406         mutex_lock(&state->lock);
 407
 408         if (enable) {
 409                 if (state->state & ST_SUSPENDED) {
 410                         ret = -EBUSY;
 411                         goto unlock;
 412                 }
 413
 414                 sd_state = v4l2_subdev_lock_and_get_active_state(sd);
 415                 ret = imx8mq_mipi_csi_start_stream(state, sd_state);
 416                 v4l2_subdev_unlock_state(sd_state);
 417
 418                 if (ret < 0)
 419                         goto unlock;
 420
 421                 ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
 422                 if (ret < 0)
 423                         goto unlock;
 424
 425                 state->state |= ST_STREAMING;
 426         } else {
 427                 v4l2_subdev_call(state->src_sd, video, s_stream, 0);
 428                 imx8mq_mipi_csi_stop_stream(state);
 429                 state->state &= ~ST_STREAMING;
 430         }
 431
 432 unlock:
 433         mutex_unlock(&state->lock);
 434
 435         if (!enable || ret < 0)
 436                 pm_runtime_put(state->dev);
 437
 438         return ret;
 439 }
 440
 441 static int imx8mq_mipi_csi_init_cfg(struct v4l2_subdev *sd,
 442                                     struct v4l2_subdev_state *sd_state)
 443 {
 444         struct v4l2_mbus_framefmt *fmt_sink;
 445         struct v4l2_mbus_framefmt *fmt_source;
 446
 447         fmt_sink = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SINK);
 448         fmt_source = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SOURCE);
 449
 450         fmt_sink->code = MEDIA_BUS_FMT_SGBRG10_1X10;
 451         fmt_sink->width = MIPI_CSI2_DEF_PIX_WIDTH;
 452         fmt_sink->height = MIPI_CSI2_DEF_PIX_HEIGHT;
 453         fmt_sink->field = V4L2_FIELD_NONE;
 454
 455         fmt_sink->colorspace = V4L2_COLORSPACE_RAW;
 456         fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
 457         fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
 458         fmt_sink->quantization =
 459                 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
 460                                               fmt_sink->ycbcr_enc);
 461
 462         *fmt_source = *fmt_sink;
 463
 464         return 0;
 465 }
 466
 467 static int imx8mq_mipi_csi_enum_mbus_code(struct v4l2_subdev *sd,
 468                                           struct v4l2_subdev_state *sd_state,
 469                                           struct v4l2_subdev_mbus_code_enum *code)
 470 {
 471         /*
 472          * We can't transcode in any way, the source format is identical
 473          * to the sink format.
 474          */
 475         if (code->pad == MIPI_CSI2_PAD_SOURCE) {
 476                 struct v4l2_mbus_framefmt *fmt;
 477
 478                 if (code->index > 0)
 479                         return -EINVAL;
 480
 481                 fmt = v4l2_subdev_get_pad_format(sd, sd_state, code->pad);
 482                 code->code = fmt->code;
 483                 return 0;
 484         }
 485
 486         if (code->pad != MIPI_CSI2_PAD_SINK)
 487                 return -EINVAL;
 488
 489         if (code->index >= ARRAY_SIZE(imx8mq_mipi_csi_formats))
 490                 return -EINVAL;
 491
 492         code->code = imx8mq_mipi_csi_formats[code->index].code;
 493
 494         return 0;
 495 }
 496
 497 static int imx8mq_mipi_csi_set_fmt(struct v4l2_subdev *sd,
 498                                    struct v4l2_subdev_state *sd_state,
 499                                    struct v4l2_subdev_format *sdformat)
 500 {
 501         const struct csi2_pix_format *csi2_fmt;
 502         struct v4l2_mbus_framefmt *fmt;
 503
 504         /*
 505          * The device can't transcode in any way, the source format can't be
 506          * modified.
 507          */
 508         if (sdformat->pad == MIPI_CSI2_PAD_SOURCE)
 509                 return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
 510
 511         if (sdformat->pad != MIPI_CSI2_PAD_SINK)
 512                 return -EINVAL;
 513
 514         csi2_fmt = find_csi2_format(sdformat->format.code);
 515         if (!csi2_fmt)
 516                 csi2_fmt = &imx8mq_mipi_csi_formats[0];
 517
 518         fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad);
 519
 520         fmt->code = csi2_fmt->code;
 521         fmt->width = sdformat->format.width;
 522         fmt->height = sdformat->format.height;
 523
 524         sdformat->format = *fmt;
 525
 526         /* Propagate the format from sink to source. */
 527         fmt = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SOURCE);
 528         *fmt = sdformat->format;
 529
 530         return 0;
 531 }
 532
 533 static const struct v4l2_subdev_video_ops imx8mq_mipi_csi_video_ops = {
 534         .s_stream       = imx8mq_mipi_csi_s_stream,
 535 };
 536
 537 static const struct v4l2_subdev_pad_ops imx8mq_mipi_csi_pad_ops = {
 538         .init_cfg               = imx8mq_mipi_csi_init_cfg,
 539         .enum_mbus_code         = imx8mq_mipi_csi_enum_mbus_code,
 540         .get_fmt                = v4l2_subdev_get_fmt,
 541         .set_fmt                = imx8mq_mipi_csi_set_fmt,
 542 };
 543
 544 static const struct v4l2_subdev_ops imx8mq_mipi_csi_subdev_ops = {
 545         .video  = &imx8mq_mipi_csi_video_ops,
 546         .pad    = &imx8mq_mipi_csi_pad_ops,
 547 };
 548
 549 /* -----------------------------------------------------------------------------
 550  * Media entity operations
 551  */
 552
 553 static const struct media_entity_operations imx8mq_mipi_csi_entity_ops = {
 554         .link_validate  = v4l2_subdev_link_validate,
 555         .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
 556 };
 557
 558 /* -----------------------------------------------------------------------------
 559  * Async subdev notifier
 560  */
 561
 562 static struct csi_state *
 563 mipi_notifier_to_csi2_state(struct v4l2_async_notifier *n)
 564 {
 565         return container_of(n, struct csi_state, notifier);
 566 }
 567
 568 static int imx8mq_mipi_csi_notify_bound(struct v4l2_async_notifier *notifier,
 569                                         struct v4l2_subdev *sd,
 570                                         struct v4l2_async_subdev *asd)
 571 {
 572         struct csi_state *state = mipi_notifier_to_csi2_state(notifier);
 573         struct media_pad *sink = &state->sd.entity.pads[MIPI_CSI2_PAD_SINK];
 574
 575         state->src_sd = sd;
 576
 577         return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
 578                                                MEDIA_LNK_FL_IMMUTABLE);
 579 }
 580
 581 static const struct v4l2_async_notifier_operations imx8mq_mipi_csi_notify_ops = {
 582         .bound = imx8mq_mipi_csi_notify_bound,
 583 };
 584
 585 static int imx8mq_mipi_csi_async_register(struct csi_state *state)
 586 {
 587         struct v4l2_fwnode_endpoint vep = {
 588                 .bus_type = V4L2_MBUS_CSI2_DPHY,
 589         };
 590         struct v4l2_async_subdev *asd;
 591         struct fwnode_handle *ep;
 592         unsigned int i;
 593         int ret;
 594
 595         v4l2_async_nf_init(&state->notifier);
 596
 597         ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
 598                                              FWNODE_GRAPH_ENDPOINT_NEXT);
 599         if (!ep)
 600                 return -ENOTCONN;
 601
 602         ret = v4l2_fwnode_endpoint_parse(ep, &vep);
 603         if (ret)
 604                 goto err_parse;
 605
 606         for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
 607                 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
 608                         dev_err(state->dev,
 609                                 "data lanes reordering is not supported");
 610                         ret = -EINVAL;
 611                         goto err_parse;
 612                 }
 613         }
 614
 615         state->bus = vep.bus.mipi_csi2;
 616
 617         dev_dbg(state->dev, "data lanes: %d flags: 0x%08x\n",
 618                 state->bus.num_data_lanes,
 619                 state->bus.flags);
 620
 621         asd = v4l2_async_nf_add_fwnode_remote(&state->notifier, ep,
 622                                               struct v4l2_async_subdev);
 623         if (IS_ERR(asd)) {
 624                 ret = PTR_ERR(asd);
 625                 goto err_parse;
 626         }
 627
 628         fwnode_handle_put(ep);
 629
 630         state->notifier.ops = &imx8mq_mipi_csi_notify_ops;
 631
 632         ret = v4l2_async_subdev_nf_register(&state->sd, &state->notifier);
 633         if (ret)
 634                 return ret;
 635
 636         return v4l2_async_register_subdev(&state->sd);
 637
 638 err_parse:
 639         fwnode_handle_put(ep);
 640
 641         return ret;
 642 }
 643
 644 /* -----------------------------------------------------------------------------
 645  * Suspend/resume
 646  */
 647
 648 static void imx8mq_mipi_csi_pm_suspend(struct device *dev)
 649 {
 650         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 651         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 652
 653         mutex_lock(&state->lock);
 654
 655         if (state->state & ST_POWERED) {
 656                 imx8mq_mipi_csi_stop_stream(state);
 657                 imx8mq_mipi_csi_clk_disable(state);
 658                 state->state &= ~ST_POWERED;
 659         }
 660
 661         mutex_unlock(&state->lock);
 662 }
 663
 664 static int imx8mq_mipi_csi_pm_resume(struct device *dev)
 665 {
 666         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 667         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 668         struct v4l2_subdev_state *sd_state;
 669         int ret = 0;
 670
 671         mutex_lock(&state->lock);
 672
 673         if (!(state->state & ST_POWERED)) {
 674                 state->state |= ST_POWERED;
 675                 ret = imx8mq_mipi_csi_clk_enable(state);
 676         }
 677         if (state->state & ST_STREAMING) {
 678                 sd_state = v4l2_subdev_lock_and_get_active_state(sd);
 679                 ret = imx8mq_mipi_csi_start_stream(state, sd_state);
 680                 v4l2_subdev_unlock_state(sd_state);
 681                 if (ret)
 682                         goto unlock;
 683         }
 684
 685         state->state &= ~ST_SUSPENDED;
 686
 687 unlock:
 688         mutex_unlock(&state->lock);
 689
 690         return ret ? -EAGAIN : 0;
 691 }
 692
 693 static int __maybe_unused imx8mq_mipi_csi_suspend(struct device *dev)
 694 {
 695         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 696         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 697
 698         imx8mq_mipi_csi_pm_suspend(dev);
 699
 700         state->state |= ST_SUSPENDED;
 701
 702         return 0;
 703 }
 704
 705 static int __maybe_unused imx8mq_mipi_csi_resume(struct device *dev)
 706 {
 707         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 708         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 709
 710         if (!(state->state & ST_SUSPENDED))
 711                 return 0;
 712
 713         return imx8mq_mipi_csi_pm_resume(dev);
 714 }
 715
 716 static int __maybe_unused imx8mq_mipi_csi_runtime_suspend(struct device *dev)
 717 {
 718         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 719         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 720         int ret;
 721
 722         imx8mq_mipi_csi_pm_suspend(dev);
 723
 724         ret = icc_set_bw(state->icc_path, 0, 0);
 725         if (ret)
 726                 dev_err(dev, "icc_set_bw failed with %d\n", ret);
 727
 728         return ret;
 729 }
 730
 731 static int __maybe_unused imx8mq_mipi_csi_runtime_resume(struct device *dev)
 732 {
 733         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 734         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 735         int ret;
 736
 737         ret = icc_set_bw(state->icc_path, 0, state->icc_path_bw);
 738         if (ret) {
 739                 dev_err(dev, "icc_set_bw failed with %d\n", ret);
 740                 return ret;
 741         }
 742
 743         return imx8mq_mipi_csi_pm_resume(dev);
 744 }
 745
 746 static const struct dev_pm_ops imx8mq_mipi_csi_pm_ops = {
 747         SET_RUNTIME_PM_OPS(imx8mq_mipi_csi_runtime_suspend,
 748                            imx8mq_mipi_csi_runtime_resume,
 749                            NULL)
 750         SET_SYSTEM_SLEEP_PM_OPS(imx8mq_mipi_csi_suspend, imx8mq_mipi_csi_resume)
 751 };
 752
 753 /* -----------------------------------------------------------------------------
 754  * Probe/remove & platform driver
 755  */
 756
 757 static int imx8mq_mipi_csi_subdev_init(struct csi_state *state)
 758 {
 759         struct v4l2_subdev *sd = &state->sd;
 760         int ret;
 761
 762         v4l2_subdev_init(sd, &imx8mq_mipi_csi_subdev_ops);
 763         sd->owner = THIS_MODULE;
 764         snprintf(sd->name, sizeof(sd->name), "%s %s",
 765                  MIPI_CSI2_SUBDEV_NAME, dev_name(state->dev));
 766
 767         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
 768
 769         sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
 770         sd->entity.ops = &imx8mq_mipi_csi_entity_ops;
 771
 772         sd->dev = state->dev;
 773
 774         state->pads[MIPI_CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
 775                                          | MEDIA_PAD_FL_MUST_CONNECT;
 776         state->pads[MIPI_CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
 777                                            | MEDIA_PAD_FL_MUST_CONNECT;
 778         ret = media_entity_pads_init(&sd->entity, MIPI_CSI2_PADS_NUM,
 779                                      state->pads);
 780         if (ret)
 781                 return ret;
 782
 783         ret = v4l2_subdev_init_finalize(sd);
 784         if (ret) {
 785                 media_entity_cleanup(&sd->entity);
 786                 return ret;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static void imx8mq_mipi_csi_release_icc(struct platform_device *pdev)
 793 {
 794         struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
 795         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 796
 797         icc_put(state->icc_path);
 798 }
 799
 800 static int imx8mq_mipi_csi_init_icc(struct platform_device *pdev)
 801 {
 802         struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
 803         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 804
 805         /* Optional interconnect request */
 806         state->icc_path = of_icc_get(&pdev->dev, "dram");
 807         if (IS_ERR_OR_NULL(state->icc_path))
 808                 return PTR_ERR_OR_ZERO(state->icc_path);
 809
 810         state->icc_path_bw = MBps_to_icc(700);
 811
 812         return 0;
 813 }
 814
 815 static int imx8mq_mipi_csi_parse_dt(struct csi_state *state)
 816 {
 817         struct device *dev = state->dev;
 818         struct device_node *np = state->dev->of_node;
 819         struct device_node *node;
 820         phandle ph;
 821         u32 out_val[2];
 822         int ret = 0;
 823
 824         state->rst = devm_reset_control_array_get_exclusive(dev);
 825         if (IS_ERR(state->rst)) {
 826                 dev_err(dev, "Failed to get reset: %pe\n", state->rst);
 827                 return PTR_ERR(state->rst);
 828         }
 829
 830         ret = of_property_read_u32_array(np, "fsl,mipi-phy-gpr", out_val,
 831                                          ARRAY_SIZE(out_val));
 832         if (ret) {
 833                 dev_err(dev, "no fsl,mipi-phy-gpr property found: %d\n", ret);
 834                 return ret;
 835         }
 836
 837         ph = *out_val;
 838
 839         node = of_find_node_by_phandle(ph);
 840         if (!node) {
 841                 dev_err(dev, "Error finding node by phandle\n");
 842                 return -ENODEV;
 843         }
 844         state->phy_gpr = syscon_node_to_regmap(node);
 845         of_node_put(node);
 846         if (IS_ERR(state->phy_gpr)) {
 847                 dev_err(dev, "failed to get gpr regmap: %pe\n", state->phy_gpr);
 848                 return PTR_ERR(state->phy_gpr);
 849         }
 850
 851         state->phy_gpr_reg = out_val[1];
 852         dev_dbg(dev, "phy gpr register set to 0x%x\n", state->phy_gpr_reg);
 853
 854         return ret;
 855 }
 856
 857 static int imx8mq_mipi_csi_probe(struct platform_device *pdev)
 858 {
 859         struct device *dev = &pdev->dev;
 860         struct csi_state *state;
 861         int ret;
 862
 863         state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
 864         if (!state)
 865                 return -ENOMEM;
 866
 867         state->dev = dev;
 868
 869         ret = imx8mq_mipi_csi_parse_dt(state);
 870         if (ret < 0) {
 871                 dev_err(dev, "Failed to parse device tree: %d\n", ret);
 872                 return ret;
 873         }
 874
 875         /* Acquire resources. */
 876         state->regs = devm_platform_ioremap_resource(pdev, 0);
 877         if (IS_ERR(state->regs))
 878                 return PTR_ERR(state->regs);
 879
 880         ret = imx8mq_mipi_csi_clk_get(state);
 881         if (ret < 0)
 882                 return ret;
 883
 884         platform_set_drvdata(pdev, &state->sd);
 885
 886         mutex_init(&state->lock);
 887
 888         ret = imx8mq_mipi_csi_subdev_init(state);
 889         if (ret < 0)
 890                 goto mutex;
 891
 892         ret = imx8mq_mipi_csi_init_icc(pdev);
 893         if (ret)
 894                 goto mutex;
 895
 896         /* Enable runtime PM. */
 897         pm_runtime_enable(dev);
 898         if (!pm_runtime_enabled(dev)) {
 899                 ret = imx8mq_mipi_csi_runtime_resume(dev);
 900                 if (ret < 0)
 901                         goto icc;
 902         }
 903
 904         ret = imx8mq_mipi_csi_async_register(state);
 905         if (ret < 0)
 906                 goto cleanup;
 907
 908         return 0;
 909
 910 cleanup:
 911         pm_runtime_disable(&pdev->dev);
 912         imx8mq_mipi_csi_runtime_suspend(&pdev->dev);
 913
 914         media_entity_cleanup(&state->sd.entity);
 915         v4l2_subdev_cleanup(&state->sd);
 916         v4l2_async_nf_unregister(&state->notifier);
 917         v4l2_async_nf_cleanup(&state->notifier);
 918         v4l2_async_unregister_subdev(&state->sd);
 919 icc:
 920         imx8mq_mipi_csi_release_icc(pdev);
 921 mutex:
 922         mutex_destroy(&state->lock);
 923
 924         return ret;
 925 }
 926
 927 static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
 928 {
 929         struct v4l2_subdev *sd = platform_get_drvdata(pdev);
 930         struct csi_state *state = mipi_sd_to_csi2_state(sd);
 931
 932         v4l2_async_nf_unregister(&state->notifier);
 933         v4l2_async_nf_cleanup(&state->notifier);
 934         v4l2_async_unregister_subdev(&state->sd);
 935
 936         pm_runtime_disable(&pdev->dev);
 937         imx8mq_mipi_csi_runtime_suspend(&pdev->dev);
 938         media_entity_cleanup(&state->sd.entity);
 939         v4l2_subdev_cleanup(&state->sd);
 940         mutex_destroy(&state->lock);
 941         pm_runtime_set_suspended(&pdev->dev);
 942         imx8mq_mipi_csi_release_icc(pdev);
 943 }
 944
 945 static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
 946         { .compatible = "fsl,imx8mq-mipi-csi2", },
 947         { /* sentinel */ },
 948 };
 949 MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);
 950
 951 static struct platform_driver imx8mq_mipi_csi_driver = {
 952         .probe          = imx8mq_mipi_csi_probe,
 953         .remove_new     = imx8mq_mipi_csi_remove,
 954         .driver         = {
 955                 .of_match_table = imx8mq_mipi_csi_of_match,
 956                 .name           = MIPI_CSI2_DRIVER_NAME,
 957                 .pm             = &imx8mq_mipi_csi_pm_ops,
 958         },
 959 };
 960
 961 module_platform_driver(imx8mq_mipi_csi_driver);
 962
 963 MODULE_DESCRIPTION("i.MX8MQ MIPI CSI-2 receiver driver");
 964 MODULE_AUTHOR("Martin Kepplinger <martin.kepplinger@puri.sm>");
 965 MODULE_LICENSE("GPL v2");
 966 MODULE_ALIAS("platform:imx8mq-mipi-csi2");