drivers/staging/media/hantro/hantro_drv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hantro VPU codec driver
   4  *
   5  * Copyright (C) 2018 Collabora, Ltd.
   6  * Copyright 2018 Google LLC.
   7  *      Tomasz Figa <tfiga@chromium.org>
   8  *
   9  * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
  10  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/slab.h>
  20 #include <linux/videodev2.h>
  21 #include <linux/workqueue.h>
  22 #include <media/v4l2-event.h>
  23 #include <media/v4l2-mem2mem.h>
  24 #include <media/videobuf2-core.h>
  25 #include <media/videobuf2-vmalloc.h>
  26
  27 #include "hantro_v4l2.h"
  28 #include "hantro.h"
  29 #include "hantro_hw.h"
  30
  31 #define DRIVER_NAME "hantro-vpu"
  32
  33 int hantro_debug;
  34 module_param_named(debug, hantro_debug, int, 0644);
  35 MODULE_PARM_DESC(debug,
  36                  "Debug level - higher value produces more verbose messages");
  37
  38 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id)
  39 {
  40         struct v4l2_ctrl *ctrl;
  41
  42         ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id);
  43         return ctrl ? ctrl->p_cur.p : NULL;
  44 }
  45
  46 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts)
  47 {
  48         struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
  49         struct vb2_buffer *buf;
  50         int index;
  51
  52         index = vb2_find_timestamp(q, ts, 0);
  53         if (index < 0)
  54                 return 0;
  55         buf = vb2_get_buffer(q, index);
  56         return hantro_get_dec_buf_addr(ctx, buf);
  57 }
  58
  59 static void hantro_job_finish_no_pm(struct hantro_dev *vpu,
  60                                     struct hantro_ctx *ctx,
  61                                     enum vb2_buffer_state result)
  62 {
  63         struct vb2_v4l2_buffer *src, *dst;
  64
  65         src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  66         dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  67
  68         if (WARN_ON(!src))
  69                 return;
  70         if (WARN_ON(!dst))
  71                 return;
  72
  73         src->sequence = ctx->sequence_out++;
  74         dst->sequence = ctx->sequence_cap++;
  75
  76         v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
  77                                          result);
  78 }
  79
  80 static void hantro_job_finish(struct hantro_dev *vpu,
  81                               struct hantro_ctx *ctx,
  82                               enum vb2_buffer_state result)
  83 {
  84         pm_runtime_mark_last_busy(vpu->dev);
  85         pm_runtime_put_autosuspend(vpu->dev);
  86
  87         clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
  88
  89         hantro_job_finish_no_pm(vpu, ctx, result);
  90 }
  91
  92 void hantro_irq_done(struct hantro_dev *vpu,
  93                      enum vb2_buffer_state result)
  94 {
  95         struct hantro_ctx *ctx =
  96                 v4l2_m2m_get_curr_priv(vpu->m2m_dev);
  97
  98         /*
  99          * If cancel_delayed_work returns false
 100          * the timeout expired. The watchdog is running,
 101          * and will take care of finishing the job.
 102          */
 103         if (cancel_delayed_work(&vpu->watchdog_work)) {
 104                 if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done)
 105                         ctx->codec_ops->done(ctx);
 106                 hantro_job_finish(vpu, ctx, result);
 107         }
 108 }
 109
 110 void hantro_watchdog(struct work_struct *work)
 111 {
 112         struct hantro_dev *vpu;
 113         struct hantro_ctx *ctx;
 114
 115         vpu = container_of(to_delayed_work(work),
 116                            struct hantro_dev, watchdog_work);
 117         ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev);
 118         if (ctx) {
 119                 vpu_err("frame processing timed out!\n");
 120                 ctx->codec_ops->reset(ctx);
 121                 hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR);
 122         }
 123 }
 124
 125 void hantro_start_prepare_run(struct hantro_ctx *ctx)
 126 {
 127         struct vb2_v4l2_buffer *src_buf;
 128
 129         src_buf = hantro_get_src_buf(ctx);
 130         v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
 131                                 &ctx->ctrl_handler);
 132
 133         if (!ctx->is_encoder) {
 134                 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
 135                         hantro_postproc_enable(ctx);
 136                 else
 137                         hantro_postproc_disable(ctx);
 138         }
 139 }
 140
 141 void hantro_end_prepare_run(struct hantro_ctx *ctx)
 142 {
 143         struct vb2_v4l2_buffer *src_buf;
 144
 145         src_buf = hantro_get_src_buf(ctx);
 146         v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
 147                                    &ctx->ctrl_handler);
 148
 149         /* Kick the watchdog. */
 150         schedule_delayed_work(&ctx->dev->watchdog_work,
 151                               msecs_to_jiffies(2000));
 152 }
 153
 154 static void device_run(void *priv)
 155 {
 156         struct hantro_ctx *ctx = priv;
 157         struct vb2_v4l2_buffer *src, *dst;
 158         int ret;
 159
 160         src = hantro_get_src_buf(ctx);
 161         dst = hantro_get_dst_buf(ctx);
 162
 163         ret = pm_runtime_resume_and_get(ctx->dev->dev);
 164         if (ret < 0)
 165                 goto err_cancel_job;
 166
 167         ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks);
 168         if (ret)
 169                 goto err_cancel_job;
 170
 171         v4l2_m2m_buf_copy_metadata(src, dst, true);
 172
 173         if (ctx->codec_ops->run(ctx))
 174                 goto err_cancel_job;
 175
 176         return;
 177
 178 err_cancel_job:
 179         hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR);
 180 }
 181
 182 static struct v4l2_m2m_ops vpu_m2m_ops = {
 183         .device_run = device_run,
 184 };
 185
 186 static int
 187 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
 188 {
 189         struct hantro_ctx *ctx = priv;
 190         int ret;
 191
 192         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
 193         src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
 194         src_vq->drv_priv = ctx;
 195         src_vq->ops = &hantro_queue_ops;
 196         src_vq->mem_ops = &vb2_dma_contig_memops;
 197
 198         /*
 199          * Driver does mostly sequential access, so sacrifice TLB efficiency
 200          * for faster allocation. Also, no CPU access on the source queue,
 201          * so no kernel mapping needed.
 202          */
 203         src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
 204                             DMA_ATTR_NO_KERNEL_MAPPING;
 205         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
 206         src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 207         src_vq->lock = &ctx->dev->vpu_mutex;
 208         src_vq->dev = ctx->dev->v4l2_dev.dev;
 209         src_vq->supports_requests = true;
 210
 211         ret = vb2_queue_init(src_vq);
 212         if (ret)
 213                 return ret;
 214
 215         /*
 216          * When encoding, the CAPTURE queue doesn't need dma memory,
 217          * as the CPU needs to create the JPEG frames, from the
 218          * hardware-produced JPEG payload.
 219          *
 220          * For the DMA destination buffer, we use a bounce buffer.
 221          */
 222         if (ctx->is_encoder) {
 223                 dst_vq->mem_ops = &vb2_vmalloc_memops;
 224         } else {
 225                 dst_vq->bidirectional = true;
 226                 dst_vq->mem_ops = &vb2_dma_contig_memops;
 227                 dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
 228                                     DMA_ATTR_NO_KERNEL_MAPPING;
 229         }
 230
 231         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 232         dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
 233         dst_vq->drv_priv = ctx;
 234         dst_vq->ops = &hantro_queue_ops;
 235         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
 236         dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 237         dst_vq->lock = &ctx->dev->vpu_mutex;
 238         dst_vq->dev = ctx->dev->v4l2_dev.dev;
 239
 240         return vb2_queue_init(dst_vq);
 241 }
 242
 243 static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
 244 {
 245         if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
 246                 const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
 247
 248                 if (sps->chroma_format_idc > 1)
 249                         /* Only 4:0:0 and 4:2:0 are supported */
 250                         return -EINVAL;
 251                 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
 252                         /* Luma and chroma bit depth mismatch */
 253                         return -EINVAL;
 254                 if (sps->bit_depth_luma_minus8 != 0)
 255                         /* Only 8-bit is supported */
 256                         return -EINVAL;
 257         } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
 258                 const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
 259
 260                 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
 261                         /* Luma and chroma bit depth mismatch */
 262                         return -EINVAL;
 263                 if (sps->bit_depth_luma_minus8 != 0)
 264                         /* Only 8-bit is supported */
 265                         return -EINVAL;
 266                 if (sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED)
 267                         /* No scaling support */
 268                         return -EINVAL;
 269         }
 270         return 0;
 271 }
 272
 273 static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
 274 {
 275         struct hantro_ctx *ctx;
 276
 277         ctx = container_of(ctrl->handler,
 278                            struct hantro_ctx, ctrl_handler);
 279
 280         vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
 281
 282         switch (ctrl->id) {
 283         case V4L2_CID_JPEG_COMPRESSION_QUALITY:
 284                 ctx->jpeg_quality = ctrl->val;
 285                 break;
 286         default:
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl)
 294 {
 295         struct hantro_ctx *ctx;
 296
 297         ctx = container_of(ctrl->handler,
 298                            struct hantro_ctx, ctrl_handler);
 299
 300         vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
 301
 302         switch (ctrl->id) {
 303         case V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP:
 304                 ctx->hevc_dec.ctrls.hevc_hdr_skip_length = ctrl->val;
 305                 break;
 306         default:
 307                 return -EINVAL;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static const struct v4l2_ctrl_ops hantro_ctrl_ops = {
 314         .try_ctrl = hantro_try_ctrl,
 315 };
 316
 317 static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = {
 318         .s_ctrl = hantro_jpeg_s_ctrl,
 319 };
 320
 321 static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = {
 322         .s_ctrl = hantro_hevc_s_ctrl,
 323 };
 324
 325 static const struct hantro_ctrl controls[] = {
 326         {
 327                 .codec = HANTRO_JPEG_ENCODER,
 328                 .cfg = {
 329                         .id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
 330                         .min = 5,
 331                         .max = 100,
 332                         .step = 1,
 333                         .def = 50,
 334                         .ops = &hantro_jpeg_ctrl_ops,
 335                 },
 336         }, {
 337                 .codec = HANTRO_MPEG2_DECODER,
 338                 .cfg = {
 339                         .id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
 340                 },
 341         }, {
 342                 .codec = HANTRO_MPEG2_DECODER,
 343                 .cfg = {
 344                         .id = V4L2_CID_STATELESS_MPEG2_PICTURE,
 345                 },
 346         }, {
 347                 .codec = HANTRO_MPEG2_DECODER,
 348                 .cfg = {
 349                         .id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
 350                 },
 351         }, {
 352                 .codec = HANTRO_VP8_DECODER,
 353                 .cfg = {
 354                         .id = V4L2_CID_STATELESS_VP8_FRAME,
 355                 },
 356         }, {
 357                 .codec = HANTRO_H264_DECODER,
 358                 .cfg = {
 359                         .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
 360                 },
 361         }, {
 362                 .codec = HANTRO_H264_DECODER,
 363                 .cfg = {
 364                         .id = V4L2_CID_STATELESS_H264_SPS,
 365                         .ops = &hantro_ctrl_ops,
 366                 },
 367         }, {
 368                 .codec = HANTRO_H264_DECODER,
 369                 .cfg = {
 370                         .id = V4L2_CID_STATELESS_H264_PPS,
 371                 },
 372         }, {
 373                 .codec = HANTRO_H264_DECODER,
 374                 .cfg = {
 375                         .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
 376                 },
 377         }, {
 378                 .codec = HANTRO_H264_DECODER,
 379                 .cfg = {
 380                         .id = V4L2_CID_STATELESS_H264_DECODE_MODE,
 381                         .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
 382                         .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
 383                         .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
 384                 },
 385         }, {
 386                 .codec = HANTRO_H264_DECODER,
 387                 .cfg = {
 388                         .id = V4L2_CID_STATELESS_H264_START_CODE,
 389                         .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
 390                         .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
 391                         .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
 392                 },
 393         }, {
 394                 .codec = HANTRO_H264_DECODER,
 395                 .cfg = {
 396                         .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
 397                         .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
 398                         .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
 399                         .menu_skip_mask =
 400                         BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
 401                         .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
 402                 }
 403         }, {
 404                 .codec = HANTRO_HEVC_DECODER,
 405                 .cfg = {
 406                         .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,
 407                         .min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
 408                         .max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
 409                         .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
 410                 },
 411         }, {
 412                 .codec = HANTRO_HEVC_DECODER,
 413                 .cfg = {
 414                         .id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE,
 415                         .min = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
 416                         .max = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
 417                         .def = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
 418                 },
 419         }, {
 420                 .codec = HANTRO_HEVC_DECODER,
 421                 .cfg = {
 422                         .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
 423                         .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
 424                         .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
 425                         .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
 426                 },
 427         }, {
 428                 .codec = HANTRO_HEVC_DECODER,
 429                 .cfg = {
 430                         .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
 431                         .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
 432                         .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
 433                 },
 434         }, {
 435                 .codec = HANTRO_HEVC_DECODER,
 436                 .cfg = {
 437                         .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
 438                         .ops = &hantro_ctrl_ops,
 439                 },
 440         }, {
 441                 .codec = HANTRO_HEVC_DECODER,
 442                 .cfg = {
 443                         .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
 444                 },
 445         }, {
 446                 .codec = HANTRO_HEVC_DECODER,
 447                 .cfg = {
 448                         .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
 449                 },
 450         }, {
 451                 .codec = HANTRO_HEVC_DECODER,
 452                 .cfg = {
 453                         .id = V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP,
 454                         .name = "Hantro HEVC slice header skip bytes",
 455                         .type = V4L2_CTRL_TYPE_INTEGER,
 456                         .min = 0,
 457                         .def = 0,
 458                         .max = 0x100,
 459                         .step = 1,
 460                         .ops = &hantro_hevc_ctrl_ops,
 461                 },
 462         },
 463 };
 464
 465 static int hantro_ctrls_setup(struct hantro_dev *vpu,
 466                               struct hantro_ctx *ctx,
 467                               int allowed_codecs)
 468 {
 469         int i, num_ctrls = ARRAY_SIZE(controls);
 470
 471         v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls);
 472
 473         for (i = 0; i < num_ctrls; i++) {
 474                 if (!(allowed_codecs & controls[i].codec))
 475                         continue;
 476
 477                 v4l2_ctrl_new_custom(&ctx->ctrl_handler,
 478                                      &controls[i].cfg, NULL);
 479                 if (ctx->ctrl_handler.error) {
 480                         vpu_err("Adding control (%d) failed %d\n",
 481                                 controls[i].cfg.id,
 482                                 ctx->ctrl_handler.error);
 483                         v4l2_ctrl_handler_free(&ctx->ctrl_handler);
 484                         return ctx->ctrl_handler.error;
 485                 }
 486         }
 487         return v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
 488 }
 489
 490 /*
 491  * V4L2 file operations.
 492  */
 493
 494 static int hantro_open(struct file *filp)
 495 {
 496         struct hantro_dev *vpu = video_drvdata(filp);
 497         struct video_device *vdev = video_devdata(filp);
 498         struct hantro_func *func = hantro_vdev_to_func(vdev);
 499         struct hantro_ctx *ctx;
 500         int allowed_codecs, ret;
 501
 502         /*
 503          * We do not need any extra locking here, because we operate only
 504          * on local data here, except reading few fields from dev, which
 505          * do not change through device's lifetime (which is guaranteed by
 506          * reference on module from open()) and V4L2 internal objects (such
 507          * as vdev and ctx->fh), which have proper locking done in respective
 508          * helper functions used here.
 509          */
 510
 511         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 512         if (!ctx)
 513                 return -ENOMEM;
 514
 515         ctx->dev = vpu;
 516         if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
 517                 allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS;
 518                 ctx->is_encoder = true;
 519         } else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
 520                 allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
 521                 ctx->is_encoder = false;
 522         } else {
 523                 ret = -ENODEV;
 524                 goto err_ctx_free;
 525         }
 526
 527         ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init);
 528         if (IS_ERR(ctx->fh.m2m_ctx)) {
 529                 ret = PTR_ERR(ctx->fh.m2m_ctx);
 530                 goto err_ctx_free;
 531         }
 532
 533         v4l2_fh_init(&ctx->fh, vdev);
 534         filp->private_data = &ctx->fh;
 535         v4l2_fh_add(&ctx->fh);
 536
 537         hantro_reset_fmts(ctx);
 538
 539         ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs);
 540         if (ret) {
 541                 vpu_err("Failed to set up controls\n");
 542                 goto err_fh_free;
 543         }
 544         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
 545
 546         return 0;
 547
 548 err_fh_free:
 549         v4l2_fh_del(&ctx->fh);
 550         v4l2_fh_exit(&ctx->fh);
 551 err_ctx_free:
 552         kfree(ctx);
 553         return ret;
 554 }
 555
 556 static int hantro_release(struct file *filp)
 557 {
 558         struct hantro_ctx *ctx =
 559                 container_of(filp->private_data, struct hantro_ctx, fh);
 560
 561         /*
 562          * No need for extra locking because this was the last reference
 563          * to this file.
 564          */
 565         v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
 566         v4l2_fh_del(&ctx->fh);
 567         v4l2_fh_exit(&ctx->fh);
 568         v4l2_ctrl_handler_free(&ctx->ctrl_handler);
 569         kfree(ctx);
 570
 571         return 0;
 572 }
 573
 574 static const struct v4l2_file_operations hantro_fops = {
 575         .owner = THIS_MODULE,
 576         .open = hantro_open,
 577         .release = hantro_release,
 578         .poll = v4l2_m2m_fop_poll,
 579         .unlocked_ioctl = video_ioctl2,
 580         .mmap = v4l2_m2m_fop_mmap,
 581 };
 582
 583 static const struct of_device_id of_hantro_match[] = {
 584 #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP
 585         { .compatible = "rockchip,px30-vpu",   .data = &px30_vpu_variant, },
 586         { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, },
 587         { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, },
 588         { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
 589         { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
 590         { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
 591 #endif
 592 #ifdef CONFIG_VIDEO_HANTRO_IMX8M
 593         { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
 594         { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
 595 #endif
 596 #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
 597         { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
 598 #endif
 599         { /* sentinel */ }
 600 };
 601 MODULE_DEVICE_TABLE(of, of_hantro_match);
 602
 603 static int hantro_register_entity(struct media_device *mdev,
 604                                   struct media_entity *entity,
 605                                   const char *entity_name,
 606                                   struct media_pad *pads, int num_pads,
 607                                   int function, struct video_device *vdev)
 608 {
 609         char *name;
 610         int ret;
 611
 612         entity->obj_type = MEDIA_ENTITY_TYPE_BASE;
 613         if (function == MEDIA_ENT_F_IO_V4L) {
 614                 entity->info.dev.major = VIDEO_MAJOR;
 615                 entity->info.dev.minor = vdev->minor;
 616         }
 617
 618         name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name,
 619                               entity_name);
 620         if (!name)
 621                 return -ENOMEM;
 622
 623         entity->name = name;
 624         entity->function = function;
 625
 626         ret = media_entity_pads_init(entity, num_pads, pads);
 627         if (ret)
 628                 return ret;
 629
 630         ret = media_device_register_entity(mdev, entity);
 631         if (ret)
 632                 return ret;
 633
 634         return 0;
 635 }
 636
 637 static int hantro_attach_func(struct hantro_dev *vpu,
 638                               struct hantro_func *func)
 639 {
 640         struct media_device *mdev = &vpu->mdev;
 641         struct media_link *link;
 642         int ret;
 643
 644         /* Create the three encoder entities with their pads */
 645         func->source_pad.flags = MEDIA_PAD_FL_SOURCE;
 646         ret = hantro_register_entity(mdev, &func->vdev.entity, "source",
 647                                      &func->source_pad, 1, MEDIA_ENT_F_IO_V4L,
 648                                      &func->vdev);
 649         if (ret)
 650                 return ret;
 651
 652         func->proc_pads[0].flags = MEDIA_PAD_FL_SINK;
 653         func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE;
 654         ret = hantro_register_entity(mdev, &func->proc, "proc",
 655                                      func->proc_pads, 2, func->id,
 656                                      &func->vdev);
 657         if (ret)
 658                 goto err_rel_entity0;
 659
 660         func->sink_pad.flags = MEDIA_PAD_FL_SINK;
 661         ret = hantro_register_entity(mdev, &func->sink, "sink",
 662                                      &func->sink_pad, 1, MEDIA_ENT_F_IO_V4L,
 663                                      &func->vdev);
 664         if (ret)
 665                 goto err_rel_entity1;
 666
 667         /* Connect the three entities */
 668         ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
 669                                     MEDIA_LNK_FL_IMMUTABLE |
 670                                     MEDIA_LNK_FL_ENABLED);
 671         if (ret)
 672                 goto err_rel_entity2;
 673
 674         ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
 675                                     MEDIA_LNK_FL_IMMUTABLE |
 676                                     MEDIA_LNK_FL_ENABLED);
 677         if (ret)
 678                 goto err_rm_links0;
 679
 680         /* Create video interface */
 681         func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO,
 682                                                   0, VIDEO_MAJOR,
 683                                                   func->vdev.minor);
 684         if (!func->intf_devnode) {
 685                 ret = -ENOMEM;
 686                 goto err_rm_links1;
 687         }
 688
 689         /* Connect the two DMA engines to the interface */
 690         link = media_create_intf_link(&func->vdev.entity,
 691                                       &func->intf_devnode->intf,
 692                                       MEDIA_LNK_FL_IMMUTABLE |
 693                                       MEDIA_LNK_FL_ENABLED);
 694         if (!link) {
 695                 ret = -ENOMEM;
 696                 goto err_rm_devnode;
 697         }
 698
 699         link = media_create_intf_link(&func->sink, &func->intf_devnode->intf,
 700                                       MEDIA_LNK_FL_IMMUTABLE |
 701                                       MEDIA_LNK_FL_ENABLED);
 702         if (!link) {
 703                 ret = -ENOMEM;
 704                 goto err_rm_devnode;
 705         }
 706         return 0;
 707
 708 err_rm_devnode:
 709         media_devnode_remove(func->intf_devnode);
 710
 711 err_rm_links1:
 712         media_entity_remove_links(&func->sink);
 713
 714 err_rm_links0:
 715         media_entity_remove_links(&func->proc);
 716         media_entity_remove_links(&func->vdev.entity);
 717
 718 err_rel_entity2:
 719         media_device_unregister_entity(&func->sink);
 720
 721 err_rel_entity1:
 722         media_device_unregister_entity(&func->proc);
 723
 724 err_rel_entity0:
 725         media_device_unregister_entity(&func->vdev.entity);
 726         return ret;
 727 }
 728
 729 static void hantro_detach_func(struct hantro_func *func)
 730 {
 731         media_devnode_remove(func->intf_devnode);
 732         media_entity_remove_links(&func->sink);
 733         media_entity_remove_links(&func->proc);
 734         media_entity_remove_links(&func->vdev.entity);
 735         media_device_unregister_entity(&func->sink);
 736         media_device_unregister_entity(&func->proc);
 737         media_device_unregister_entity(&func->vdev.entity);
 738 }
 739
 740 static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)
 741 {
 742         const struct of_device_id *match;
 743         struct hantro_func *func;
 744         struct video_device *vfd;
 745         int ret;
 746
 747         match = of_match_node(of_hantro_match, vpu->dev->of_node);
 748         func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL);
 749         if (!func) {
 750                 v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n");
 751                 return -ENOMEM;
 752         }
 753
 754         func->id = funcid;
 755
 756         vfd = &func->vdev;
 757         vfd->fops = &hantro_fops;
 758         vfd->release = video_device_release_empty;
 759         vfd->lock = &vpu->vpu_mutex;
 760         vfd->v4l2_dev = &vpu->v4l2_dev;
 761         vfd->vfl_dir = VFL_DIR_M2M;
 762         vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
 763         vfd->ioctl_ops = &hantro_ioctl_ops;
 764         snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible,
 765                  funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec");
 766
 767         if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
 768                 vpu->encoder = func;
 769         else
 770                 vpu->decoder = func;
 771
 772         video_set_drvdata(vfd, vpu);
 773
 774         ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
 775         if (ret) {
 776                 v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n");
 777                 return ret;
 778         }
 779
 780         ret = hantro_attach_func(vpu, func);
 781         if (ret) {
 782                 v4l2_err(&vpu->v4l2_dev,
 783                          "Failed to attach functionality to the media device\n");
 784                 goto err_unreg_dev;
 785         }
 786
 787         v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name,
 788                   vfd->num);
 789
 790         return 0;
 791
 792 err_unreg_dev:
 793         video_unregister_device(vfd);
 794         return ret;
 795 }
 796
 797 static int hantro_add_enc_func(struct hantro_dev *vpu)
 798 {
 799         if (!vpu->variant->enc_fmts)
 800                 return 0;
 801
 802         return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
 803 }
 804
 805 static int hantro_add_dec_func(struct hantro_dev *vpu)
 806 {
 807         if (!vpu->variant->dec_fmts)
 808                 return 0;
 809
 810         return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
 811 }
 812
 813 static void hantro_remove_func(struct hantro_dev *vpu,
 814                                unsigned int funcid)
 815 {
 816         struct hantro_func *func;
 817
 818         if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
 819                 func = vpu->encoder;
 820         else
 821                 func = vpu->decoder;
 822
 823         if (!func)
 824                 return;
 825
 826         hantro_detach_func(func);
 827         video_unregister_device(&func->vdev);
 828 }
 829
 830 static void hantro_remove_enc_func(struct hantro_dev *vpu)
 831 {
 832         hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
 833 }
 834
 835 static void hantro_remove_dec_func(struct hantro_dev *vpu)
 836 {
 837         hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
 838 }
 839
 840 static const struct media_device_ops hantro_m2m_media_ops = {
 841         .req_validate = vb2_request_validate,
 842         .req_queue = v4l2_m2m_request_queue,
 843 };
 844
 845 static int hantro_probe(struct platform_device *pdev)
 846 {
 847         const struct of_device_id *match;
 848         struct hantro_dev *vpu;
 849         struct resource *res;
 850         int num_bases;
 851         int i, ret;
 852
 853         vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL);
 854         if (!vpu)
 855                 return -ENOMEM;
 856
 857         vpu->dev = &pdev->dev;
 858         vpu->pdev = pdev;
 859         mutex_init(&vpu->vpu_mutex);
 860         spin_lock_init(&vpu->irqlock);
 861
 862         match = of_match_node(of_hantro_match, pdev->dev.of_node);
 863         vpu->variant = match->data;
 864
 865         INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);
 866
 867         vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,
 868                                    sizeof(*vpu->clocks), GFP_KERNEL);
 869         if (!vpu->clocks)
 870                 return -ENOMEM;
 871
 872         if (vpu->variant->num_clocks > 1) {
 873                 for (i = 0; i < vpu->variant->num_clocks; i++)
 874                         vpu->clocks[i].id = vpu->variant->clk_names[i];
 875
 876                 ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks,
 877                                         vpu->clocks);
 878                 if (ret)
 879                         return ret;
 880         } else {
 881                 /*
 882                  * If the driver has a single clk, chances are there will be no
 883                  * actual name in the DT bindings.
 884                  */
 885                 vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL);
 886                 if (IS_ERR(vpu->clocks[0].clk))
 887                         return PTR_ERR(vpu->clocks[0].clk);
 888         }
 889
 890         num_bases = vpu->variant->num_regs ?: 1;
 891         vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
 892                                       sizeof(*vpu->reg_bases), GFP_KERNEL);
 893         if (!vpu->reg_bases)
 894                 return -ENOMEM;
 895
 896         for (i = 0; i < num_bases; i++) {
 897                 res = vpu->variant->reg_names ?
 898                       platform_get_resource_byname(vpu->pdev, IORESOURCE_MEM,
 899                                                    vpu->variant->reg_names[i]) :
 900                       platform_get_resource(vpu->pdev, IORESOURCE_MEM, 0);
 901                 vpu->reg_bases[i] = devm_ioremap_resource(vpu->dev, res);
 902                 if (IS_ERR(vpu->reg_bases[i]))
 903                         return PTR_ERR(vpu->reg_bases[i]);
 904         }
 905         vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
 906         vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
 907
 908         ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
 909         if (ret) {
 910                 dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
 911                 return ret;
 912         }
 913         vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
 914
 915         for (i = 0; i < vpu->variant->num_irqs; i++) {
 916                 const char *irq_name;
 917                 int irq;
 918
 919                 if (!vpu->variant->irqs[i].handler)
 920                         continue;
 921
 922                 if (vpu->variant->num_clocks > 1) {
 923                         irq_name = vpu->variant->irqs[i].name;
 924                         irq = platform_get_irq_byname(vpu->pdev, irq_name);
 925                 } else {
 926                         /*
 927                          * If the driver has a single IRQ, chances are there
 928                          * will be no actual name in the DT bindings.
 929                          */
 930                         irq_name = "default";
 931                         irq = platform_get_irq(vpu->pdev, 0);
 932                 }
 933                 if (irq <= 0)
 934                         return -ENXIO;
 935
 936                 ret = devm_request_irq(vpu->dev, irq,
 937                                        vpu->variant->irqs[i].handler, 0,
 938                                        dev_name(vpu->dev), vpu);
 939                 if (ret) {
 940                         dev_err(vpu->dev, "Could not request %s IRQ.\n",
 941                                 irq_name);
 942                         return ret;
 943                 }
 944         }
 945
 946         if (vpu->variant->init) {
 947                 ret = vpu->variant->init(vpu);
 948                 if (ret) {
 949                         dev_err(&pdev->dev, "Failed to init VPU hardware\n");
 950                         return ret;
 951                 }
 952         }
 953
 954         pm_runtime_set_autosuspend_delay(vpu->dev, 100);
 955         pm_runtime_use_autosuspend(vpu->dev);
 956         pm_runtime_enable(vpu->dev);
 957
 958         ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
 959         if (ret) {
 960                 dev_err(&pdev->dev, "Failed to prepare clocks\n");
 961                 return ret;
 962         }
 963
 964         ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
 965         if (ret) {
 966                 dev_err(&pdev->dev, "Failed to register v4l2 device\n");
 967                 goto err_clk_unprepare;
 968         }
 969         platform_set_drvdata(pdev, vpu);
 970
 971         vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops);
 972         if (IS_ERR(vpu->m2m_dev)) {
 973                 v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n");
 974                 ret = PTR_ERR(vpu->m2m_dev);
 975                 goto err_v4l2_unreg;
 976         }
 977
 978         vpu->mdev.dev = vpu->dev;
 979         strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model));
 980         strscpy(vpu->mdev.bus_info, "platform: " DRIVER_NAME,
 981                 sizeof(vpu->mdev.model));
 982         media_device_init(&vpu->mdev);
 983         vpu->mdev.ops = &hantro_m2m_media_ops;
 984         vpu->v4l2_dev.mdev = &vpu->mdev;
 985
 986         ret = hantro_add_enc_func(vpu);
 987         if (ret) {
 988                 dev_err(&pdev->dev, "Failed to register encoder\n");
 989                 goto err_m2m_rel;
 990         }
 991
 992         ret = hantro_add_dec_func(vpu);
 993         if (ret) {
 994                 dev_err(&pdev->dev, "Failed to register decoder\n");
 995                 goto err_rm_enc_func;
 996         }
 997
 998         ret = media_device_register(&vpu->mdev);
 999         if (ret) {
1000                 v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n");
1001                 goto err_rm_dec_func;
1002         }
1003
1004         return 0;
1005
1006 err_rm_dec_func:
1007         hantro_remove_dec_func(vpu);
1008 err_rm_enc_func:
1009         hantro_remove_enc_func(vpu);
1010 err_m2m_rel:
1011         media_device_cleanup(&vpu->mdev);
1012         v4l2_m2m_release(vpu->m2m_dev);
1013 err_v4l2_unreg:
1014         v4l2_device_unregister(&vpu->v4l2_dev);
1015 err_clk_unprepare:
1016         clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1017         pm_runtime_dont_use_autosuspend(vpu->dev);
1018         pm_runtime_disable(vpu->dev);
1019         return ret;
1020 }
1021
1022 static int hantro_remove(struct platform_device *pdev)
1023 {
1024         struct hantro_dev *vpu = platform_get_drvdata(pdev);
1025
1026         v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name);
1027
1028         media_device_unregister(&vpu->mdev);
1029         hantro_remove_dec_func(vpu);
1030         hantro_remove_enc_func(vpu);
1031         media_device_cleanup(&vpu->mdev);
1032         v4l2_m2m_release(vpu->m2m_dev);
1033         v4l2_device_unregister(&vpu->v4l2_dev);
1034         clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1035         pm_runtime_dont_use_autosuspend(vpu->dev);
1036         pm_runtime_disable(vpu->dev);
1037         return 0;
1038 }
1039
1040 #ifdef CONFIG_PM
1041 static int hantro_runtime_resume(struct device *dev)
1042 {
1043         struct hantro_dev *vpu = dev_get_drvdata(dev);
1044
1045         if (vpu->variant->runtime_resume)
1046                 return vpu->variant->runtime_resume(vpu);
1047
1048         return 0;
1049 }
1050 #endif
1051
1052 static const struct dev_pm_ops hantro_pm_ops = {
1053         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1054                                 pm_runtime_force_resume)
1055         SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL)
1056 };
1057
1058 static struct platform_driver hantro_driver = {
1059         .probe = hantro_probe,
1060         .remove = hantro_remove,
1061         .driver = {
1062                    .name = DRIVER_NAME,
1063                    .of_match_table = of_match_ptr(of_hantro_match),
1064                    .pm = &hantro_pm_ops,
1065         },
1066 };
1067 module_platform_driver(hantro_driver);
1068
1069 MODULE_LICENSE("GPL v2");
1070 MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>");
1071 MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>");
1072 MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
1073 MODULE_DESCRIPTION("Hantro VPU codec driver");