1 /* SPDX-License-Identifier: GPL-2.0+ */
2 #ifndef KPC_DMA_DRIVER_H
3 #define KPC_DMA_DRIVER_H
4 #include <linux/platform_device.h>
5 #include <linux/cdev.h>
6 #include <linux/kfifo.h>
7 #include <linux/list.h>
8 #include <linux/spinlock.h>
9 #include <linux/sched.h>
10 #include <linux/miscdevice.h>
11 #include <linux/rwsem.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmapool.h>
14 #include <linux/pci.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17 #include <linux/aio.h>
18 #include <linux/bitops.h>
23 struct kpc_dma_device {
24 struct list_head list;
25 struct platform_device *pldev;
26 u32 __iomem *eng_regs;
27 struct device *kpc_dma_dev;
31 int dir; // DMA_FROM_DEVICE || DMA_TO_DEVICE
34 struct work_struct irq_work;
38 size_t accumulated_bytes;
39 u32 accumulated_flags;
41 // Descriptor "Pool" housekeeping
43 struct dma_pool *desc_pool;
44 struct kpc_dma_descriptor *desc_pool_first;
45 struct kpc_dma_descriptor *desc_pool_last;
47 struct kpc_dma_descriptor *desc_next;
48 struct kpc_dma_descriptor *desc_completed;
51 struct dev_private_data {
52 struct kpc_dma_device *ldev;
59 struct kpc_dma_device * kpc_dma_lookup_device(int minor);
61 extern struct file_operations kpc_dma_fops;
63 #define ENG_CAP_PRESENT 0x00000001
64 #define ENG_CAP_DIRECTION 0x00000002
65 #define ENG_CAP_TYPE_MASK 0x000000F0
66 #define ENG_CAP_NUMBER_MASK 0x0000FF00
67 #define ENG_CAP_CARD_ADDR_SIZE_MASK 0x007F0000
68 #define ENG_CAP_DESC_MAX_BYTE_CNT_MASK 0x3F000000
69 #define ENG_CAP_PERF_SCALE_MASK 0xC0000000
71 #define ENG_CTL_IRQ_ENABLE BIT(0)
72 #define ENG_CTL_IRQ_ACTIVE BIT(1)
73 #define ENG_CTL_DESC_COMPLETE BIT(2)
74 #define ENG_CTL_DESC_ALIGN_ERR BIT(3)
75 #define ENG_CTL_DESC_FETCH_ERR BIT(4)
76 #define ENG_CTL_SW_ABORT_ERR BIT(5)
77 #define ENG_CTL_DESC_CHAIN_END BIT(7)
78 #define ENG_CTL_DMA_ENABLE BIT(8)
79 #define ENG_CTL_DMA_RUNNING BIT(10)
80 #define ENG_CTL_DMA_WAITING BIT(11)
81 #define ENG_CTL_DMA_WAITING_PERSIST BIT(12)
82 #define ENG_CTL_DMA_RESET_REQUEST BIT(14)
83 #define ENG_CTL_DMA_RESET BIT(15)
84 #define ENG_CTL_DESC_FETCH_ERR_CLASS_MASK 0x700000
87 struct dev_private_data *priv;
88 struct kpc_dma_device *ldev;
89 struct completion *cpl;
94 unsigned int page_count;
95 struct page **user_pages;
97 int mapped_entry_count;
100 #define ACD_FLAG_DONE 0
101 #define ACD_FLAG_ABORT 1
102 #define ACD_FLAG_ENG_ACCUM_ERROR 4
103 #define ACD_FLAG_ENG_ACCUM_SHORT 5
105 struct kpc_dma_descriptor {
107 volatile u32 DescByteCount :20;
108 volatile u32 DescStatusErrorFlags :4;
109 volatile u32 DescStatusFlags :8;
111 volatile u32 DescUserControlLS;
112 volatile u32 DescUserControlMS;
113 volatile u32 DescCardAddrLS;
115 volatile u32 DescBufferByteCount :20;
116 volatile u32 DescCardAddrMS :4;
117 volatile u32 DescControlFlags :8;
119 volatile u32 DescSystemAddrLS;
120 volatile u32 DescSystemAddrMS;
121 volatile u32 DescNextDescPtr;
123 dma_addr_t MyDMAAddr;
124 struct kpc_dma_descriptor *Next;
126 struct aio_cb_data *acd;
127 } __attribute__((packed));
129 #define DMA_DESC_CTL_SOP BIT(7)
130 #define DMA_DESC_CTL_EOP BIT(6)
131 #define DMA_DESC_CTL_AFIFO BIT(2)
132 #define DMA_DESC_CTL_IRQONERR BIT(1)
133 #define DMA_DESC_CTL_IRQONDONE BIT(0)
135 #define DMA_DESC_STS_SOP BIT(7)
136 #define DMA_DESC_STS_EOP BIT(6)
137 #define DMA_DESC_STS_ERROR BIT(4)
138 #define DMA_DESC_STS_USMSZ BIT(3)
139 #define DMA_DESC_STS_USLSZ BIT(2)
140 #define DMA_DESC_STS_SHORT BIT(1)
141 #define DMA_DESC_STS_COMPLETE BIT(0)
142 // DescStatusErrorFlags:
143 #define DMA_DESC_ESTS_ECRC BIT(2)
144 #define DMA_DESC_ESTS_POISON BIT(1)
145 #define DMA_DESC_ESTS_UNSUCCESSFUL BIT(0)
147 #define DMA_DESC_ALIGNMENT 0x20
150 u32 GetEngineCapabilities(struct kpc_dma_device *eng)
152 return readl(eng->eng_regs + 0);
156 void WriteEngineControl(struct kpc_dma_device *eng, u32 value)
158 writel(value, eng->eng_regs + 1);
161 u32 GetEngineControl(struct kpc_dma_device *eng)
163 return readl(eng->eng_regs + 1);
166 void SetClearEngineControl(struct kpc_dma_device *eng, u32 set_bits, u32 clear_bits)
168 u32 val = GetEngineControl(eng);
171 WriteEngineControl(eng, val);
175 void SetEngineNextPtr(struct kpc_dma_device *eng, struct kpc_dma_descriptor * desc)
177 writel(desc->MyDMAAddr, eng->eng_regs + 2);
180 void SetEngineSWPtr(struct kpc_dma_device *eng, struct kpc_dma_descriptor * desc)
182 writel(desc->MyDMAAddr, eng->eng_regs + 3);
185 void ClearEngineCompletePtr(struct kpc_dma_device *eng)
187 writel(0, eng->eng_regs + 4);
190 u32 GetEngineCompletePtr(struct kpc_dma_device *eng)
192 return readl(eng->eng_regs + 4);
196 void lock_engine(struct kpc_dma_device *eng)
199 mutex_lock(&eng->sem);
203 void unlock_engine(struct kpc_dma_device *eng)
206 mutex_unlock(&eng->sem);
211 void start_dma_engine(struct kpc_dma_device *eng);
212 int setup_dma_engine(struct kpc_dma_device *eng, u32 desc_cnt);
213 void stop_dma_engine(struct kpc_dma_device *eng);
214 void destroy_dma_engine(struct kpc_dma_device *eng);
215 void clear_desc(struct kpc_dma_descriptor *desc);
216 int count_descriptors_available(struct kpc_dma_device *eng);
217 void transfer_complete_cb(struct aio_cb_data *acd, size_t xfr_count, u32 flags);
219 #endif /* KPC_DMA_DRIVER_H */