2 * Copyright © 2005 Agere Systems Inc.
8 * This software is provided subject to the following terms and conditions,
9 * which you should read carefully before using the software. Using this
10 * software indicates your acceptance of these terms and conditions. If you do
11 * not agree with these terms and conditions, do not use the software.
13 * Copyright © 2005 Agere Systems Inc.
14 * All rights reserved.
16 * Redistribution and use in source or binary forms, with or without
17 * modifications, are permitted provided that the following conditions are met:
19 * . Redistributions of source code must retain the above copyright notice, this
20 * list of conditions and the following Disclaimer as comments in the code as
21 * well as in the documentation and/or other materials provided with the
24 * . Redistributions in binary form must reproduce the above copyright notice,
25 * this list of conditions and the following Disclaimer in the documentation
26 * and/or other materials provided with the distribution.
28 * . Neither the name of Agere Systems Inc. nor the names of the contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
35 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
49 #define DRIVER_NAME "et131x"
50 #define DRIVER_VERSION "v2.0"
52 /* EEPROM registers */
54 /* LBCIF Register Groups (addressed via 32-bit offsets) */
55 #define LBCIF_DWORD0_GROUP 0xAC
56 #define LBCIF_DWORD1_GROUP 0xB0
58 /* LBCIF Registers (addressed via 8-bit offsets) */
59 #define LBCIF_ADDRESS_REGISTER 0xAC
60 #define LBCIF_DATA_REGISTER 0xB0
61 #define LBCIF_CONTROL_REGISTER 0xB1
62 #define LBCIF_STATUS_REGISTER 0xB2
64 /* LBCIF Control Register Bits */
65 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
66 #define LBCIF_CONTROL_PAGE_WRITE 0x02
67 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
68 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
69 #define LBCIF_CONTROL_I2C_WRITE 0x40
70 #define LBCIF_CONTROL_LBCIF_ENABLE 0x80
72 /* LBCIF Status Register Bits */
73 #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
74 #define LBCIF_STATUS_I2C_IDLE 0x02
75 #define LBCIF_STATUS_ACK_ERROR 0x04
76 #define LBCIF_STATUS_GENERAL_ERROR 0x08
77 #define LBCIF_STATUS_CHECKSUM_ERROR 0x40
78 #define LBCIF_STATUS_EEPROM_PRESENT 0x80
80 /* START OF GLOBAL REGISTER ADDRESS MAP */
85 * Tx queue start address reg in global address map at address 0x0000
86 * tx queue end address reg in global address map at address 0x0004
87 * rx queue start address reg in global address map at address 0x0008
88 * rx queue end address reg in global address map at address 0x000C
92 * structure for power management control status reg in global address map
93 * located at address 0x0010
94 * jagcore_rx_rdy bit 9
95 * jagcore_tx_rdy bit 8
101 * jagcore_rx_en bit 2
102 * jagcore_tx_en bit 1
106 #define ET_PM_PHY_SW_COMA 0x40
107 #define ET_PMCSR_INIT 0x38
110 * Interrupt status reg at address 0x0018
113 #define ET_INTR_TXDMA_ISR 0x00000008
114 #define ET_INTR_TXDMA_ERR 0x00000010
115 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
116 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
117 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
118 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
119 #define ET_INTR_RXDMA_ERR 0x00000200
120 #define ET_INTR_WATCHDOG 0x00004000
121 #define ET_INTR_WOL 0x00008000
122 #define ET_INTR_PHY 0x00010000
123 #define ET_INTR_TXMAC 0x00020000
124 #define ET_INTR_RXMAC 0x00040000
125 #define ET_INTR_MAC_STAT 0x00080000
126 #define ET_INTR_SLV_TIMEOUT 0x00100000
129 * Interrupt mask register at address 0x001C
130 * Interrupt alias clear mask reg at address 0x0020
131 * Interrupt status alias reg at address 0x0024
133 * Same masks as above
137 * Software reset reg at address 0x0028
143 * 5: mac_stat_sw_reset
149 * SLV Timer reg at address 0x002C (low 24 bits)
153 * MSI Configuration reg at address 0x0030
156 #define ET_MSI_VECTOR 0x0000001F
157 #define ET_MSI_TC 0x00070000
160 * Loopback reg located at address 0x0034
163 #define ET_LOOP_MAC 0x00000001
164 #define ET_LOOP_DMA 0x00000002
167 * GLOBAL Module of JAGCore Address Mapping
168 * Located at address 0x0000
170 struct global_regs { /* Location: */
171 u32 txq_start_addr; /* 0x0000 */
172 u32 txq_end_addr; /* 0x0004 */
173 u32 rxq_start_addr; /* 0x0008 */
174 u32 rxq_end_addr; /* 0x000C */
175 u32 pm_csr; /* 0x0010 */
176 u32 unused; /* 0x0014 */
177 u32 int_status; /* 0x0018 */
178 u32 int_mask; /* 0x001C */
179 u32 int_alias_clr_en; /* 0x0020 */
180 u32 int_status_alias; /* 0x0024 */
181 u32 sw_reset; /* 0x0028 */
182 u32 slv_timer; /* 0x002C */
183 u32 msi_config; /* 0x0030 */
184 u32 loopback; /* 0x0034 */
185 u32 watchdog_timer; /* 0x0038 */
189 /* START OF TXDMA REGISTER ADDRESS MAP */
192 * txdma control status reg at address 0x1000
195 #define ET_TXDMA_CSR_HALT 0x00000001
196 #define ET_TXDMA_DROP_TLP 0x00000002
197 #define ET_TXDMA_CACHE_THRS 0x000000F0
198 #define ET_TXDMA_CACHE_SHIFT 4
199 #define ET_TXDMA_SNGL_EPKT 0x00000100
200 #define ET_TXDMA_CLASS 0x00001E00
203 * structure for txdma packet ring base address hi reg in txdma address map
204 * located at address 0x1004
205 * Defined earlier (u32)
209 * structure for txdma packet ring base address low reg in txdma address map
210 * located at address 0x1008
211 * Defined earlier (u32)
215 * structure for txdma packet ring number of descriptor reg in txdma address
216 * map. Located at address 0x100C
222 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
223 #define ET_DMA12_WRAP 0x1000
224 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
225 #define ET_DMA10_WRAP 0x0400
226 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
227 #define ET_DMA4_WRAP 0x0010
229 #define INDEX12(x) ((x) & ET_DMA12_MASK)
230 #define INDEX10(x) ((x) & ET_DMA10_MASK)
231 #define INDEX4(x) ((x) & ET_DMA4_MASK)
234 * 10bit DMA with wrap
235 * txdma tx queue write address reg in txdma address map at 0x1010
236 * txdma tx queue write address external reg in txdma address map at 0x1014
237 * txdma tx queue read address reg in txdma address map at 0x1018
240 * txdma status writeback address hi reg in txdma address map at0x101C
241 * txdma status writeback address lo reg in txdma address map at 0x1020
243 * 10bit DMA with wrap
244 * txdma service request reg in txdma address map at 0x1024
245 * structure for txdma service complete reg in txdma address map at 0x1028
248 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
249 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
251 * txdma error reg in txdma address map at address 0x1034
261 * Tx DMA Module of JAGCore Address Mapping
262 * Located at address 0x1000
264 struct txdma_regs { /* Location: */
265 u32 csr; /* 0x1000 */
266 u32 pr_base_hi; /* 0x1004 */
267 u32 pr_base_lo; /* 0x1008 */
268 u32 pr_num_des; /* 0x100C */
269 u32 txq_wr_addr; /* 0x1010 */
270 u32 txq_wr_addr_ext; /* 0x1014 */
271 u32 txq_rd_addr; /* 0x1018 */
272 u32 dma_wb_base_hi; /* 0x101C */
273 u32 dma_wb_base_lo; /* 0x1020 */
274 u32 service_request; /* 0x1024 */
275 u32 service_complete; /* 0x1028 */
276 u32 cache_rd_index; /* 0x102C */
277 u32 cache_wr_index; /* 0x1030 */
278 u32 tx_dma_error; /* 0x1034 */
279 u32 desc_abort_cnt; /* 0x1038 */
280 u32 payload_abort_cnt; /* 0x103c */
281 u32 writeback_abort_cnt; /* 0x1040 */
282 u32 desc_timeout_cnt; /* 0x1044 */
283 u32 payload_timeout_cnt; /* 0x1048 */
284 u32 writeback_timeout_cnt; /* 0x104c */
285 u32 desc_error_cnt; /* 0x1050 */
286 u32 payload_error_cnt; /* 0x1054 */
287 u32 writeback_error_cnt; /* 0x1058 */
288 u32 dropped_tlp_cnt; /* 0x105c */
289 u32 new_service_complete; /* 0x1060 */
290 u32 ethernet_packet_cnt; /* 0x1064 */
293 /* END OF TXDMA REGISTER ADDRESS MAP */
296 /* START OF RXDMA REGISTER ADDRESS MAP */
299 * structure for control status reg in rxdma address map
300 * Located at address 0x2000
314 * 15: pkt_drop_disable
320 #define ET_RXDMA_CSR_HALT 0x0001
321 #define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100
322 #define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200
323 #define ET_RXDMA_CSR_FBR0_ENABLE 0x0400
324 #define ET_RXDMA_CSR_FBR1_SIZE_LO 0x0800
325 #define ET_RXDMA_CSR_FBR1_SIZE_HI 0x1000
326 #define ET_RXDMA_CSR_FBR1_ENABLE 0x2000
327 #define ET_RXDMA_CSR_HALT_STATUS 0x00020000
330 * structure for dma writeback lo reg in rxdma address map
331 * located at address 0x2004
332 * Defined earlier (u32)
336 * structure for dma writeback hi reg in rxdma address map
337 * located at address 0x2008
338 * Defined earlier (u32)
342 * structure for number of packets done reg in rxdma address map
343 * located at address 0x200C
350 * structure for max packet time reg in rxdma address map
351 * located at address 0x2010
358 * structure for rx queue read address reg in rxdma address map
359 * located at address 0x2014
360 * Defined earlier (u32)
364 * structure for rx queue read address external reg in rxdma address map
365 * located at address 0x2018
366 * Defined earlier (u32)
370 * structure for rx queue write address reg in rxdma address map
371 * located at address 0x201C
372 * Defined earlier (u32)
376 * structure for packet status ring base address lo reg in rxdma address map
377 * located at address 0x2020
378 * Defined earlier (u32)
382 * structure for packet status ring base address hi reg in rxdma address map
383 * located at address 0x2024
384 * Defined earlier (u32)
388 * structure for packet status ring number of descriptors reg in rxdma address
389 * map. Located at address 0x2028
396 * structure for packet status ring available offset reg in rxdma address map
397 * located at address 0x202C
405 * structure for packet status ring full offset reg in rxdma address map
406 * located at address 0x2030
414 * structure for packet status ring access index reg in rxdma address map
415 * located at address 0x2034
422 * structure for packet status ring minimum descriptors reg in rxdma address
423 * map. Located at address 0x2038
430 * structure for free buffer ring base lo address reg in rxdma address map
431 * located at address 0x203C
432 * Defined earlier (u32)
436 * structure for free buffer ring base hi address reg in rxdma address map
437 * located at address 0x2040
438 * Defined earlier (u32)
442 * structure for free buffer ring number of descriptors reg in rxdma address
443 * map. Located at address 0x2044
450 * structure for free buffer ring 0 available offset reg in rxdma address map
451 * located at address 0x2048
452 * Defined earlier (u32)
456 * structure for free buffer ring 0 full offset reg in rxdma address map
457 * located at address 0x204C
458 * Defined earlier (u32)
462 * structure for free buffer cache 0 full offset reg in rxdma address map
463 * located at address 0x2050
470 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
471 * located at address 0x2054
478 * structure for free buffer ring 1 base address lo reg in rxdma address map
479 * located at address 0x2058 - 0x205C
480 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
484 * structure for free buffer ring 1 number of descriptors reg in rxdma address
485 * map. Located at address 0x2060
486 * Defined earlier (RXDMA_FBR_NUM_DES_t)
490 * structure for free buffer ring 1 available offset reg in rxdma address map
491 * located at address 0x2064
492 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
496 * structure for free buffer ring 1 full offset reg in rxdma address map
497 * located at address 0x2068
498 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
502 * structure for free buffer cache 1 read index reg in rxdma address map
503 * located at address 0x206C
504 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
508 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
509 * located at address 0x2070
510 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
514 * Rx DMA Module of JAGCore Address Mapping
515 * Located at address 0x2000
517 struct rxdma_regs { /* Location: */
518 u32 csr; /* 0x2000 */
519 u32 dma_wb_base_lo; /* 0x2004 */
520 u32 dma_wb_base_hi; /* 0x2008 */
521 u32 num_pkt_done; /* 0x200C */
522 u32 max_pkt_time; /* 0x2010 */
523 u32 rxq_rd_addr; /* 0x2014 */
524 u32 rxq_rd_addr_ext; /* 0x2018 */
525 u32 rxq_wr_addr; /* 0x201C */
526 u32 psr_base_lo; /* 0x2020 */
527 u32 psr_base_hi; /* 0x2024 */
528 u32 psr_num_des; /* 0x2028 */
529 u32 psr_avail_offset; /* 0x202C */
530 u32 psr_full_offset; /* 0x2030 */
531 u32 psr_access_index; /* 0x2034 */
532 u32 psr_min_des; /* 0x2038 */
533 u32 fbr0_base_lo; /* 0x203C */
534 u32 fbr0_base_hi; /* 0x2040 */
535 u32 fbr0_num_des; /* 0x2044 */
536 u32 fbr0_avail_offset; /* 0x2048 */
537 u32 fbr0_full_offset; /* 0x204C */
538 u32 fbr0_rd_index; /* 0x2050 */
539 u32 fbr0_min_des; /* 0x2054 */
540 u32 fbr1_base_lo; /* 0x2058 */
541 u32 fbr1_base_hi; /* 0x205C */
542 u32 fbr1_num_des; /* 0x2060 */
543 u32 fbr1_avail_offset; /* 0x2064 */
544 u32 fbr1_full_offset; /* 0x2068 */
545 u32 fbr1_rd_index; /* 0x206C */
546 u32 fbr1_min_des; /* 0x2070 */
549 /* END OF RXDMA REGISTER ADDRESS MAP */
552 /* START OF TXMAC REGISTER ADDRESS MAP */
555 * structure for control reg in txmac address map
556 * located at address 0x3000
571 * structure for shadow pointer reg in txmac address map
572 * located at address 0x3004
580 * structure for error count reg in txmac address map
581 * located at address 0x3008
590 * structure for max fill reg in txmac address map
591 * located at address 0x300C
597 * structure for cf parameter reg in txmac address map
598 * located at address 0x3010
604 * structure for tx test reg in txmac address map
605 * located at address 0x3014
610 * 10-0: txq test pointer
614 * structure for error reg in txmac address map
615 * located at address 0x3018
629 * structure for error interrupt reg in txmac address map
630 * located at address 0x301C
644 * structure for error interrupt reg in txmac address map
645 * located at address 0x3020
653 * Tx MAC Module of JAGCore Address Mapping
655 struct txmac_regs { /* Location: */
656 u32 ctl; /* 0x3000 */
657 u32 shadow_ptr; /* 0x3004 */
658 u32 err_cnt; /* 0x3008 */
659 u32 max_fill; /* 0x300C */
660 u32 cf_param; /* 0x3010 */
661 u32 tx_test; /* 0x3014 */
662 u32 err; /* 0x3018 */
663 u32 err_int; /* 0x301C */
664 u32 bp_ctrl; /* 0x3020 */
667 /* END OF TXMAC REGISTER ADDRESS MAP */
669 /* START OF RXMAC REGISTER ADDRESS MAP */
672 * structure for rxmac control reg in rxmac address map
673 * located at address 0x4000
676 * 6: rxmac_int_disable
680 * 2: pkt_filter_disable
686 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
687 * located at address 0x4004
701 * structure for CRC 1 and CRC 2 reg in rxmac address map
702 * located at address 0x4008
709 * structure for CRC 3 and CRC 4 reg in rxmac address map
710 * located at address 0x400C
717 * structure for Wake On Lan Source Address Lo reg in rxmac address map
718 * located at address 0x4010
726 #define ET_WOL_LO_SA3_SHIFT 24
727 #define ET_WOL_LO_SA4_SHIFT 16
728 #define ET_WOL_LO_SA5_SHIFT 8
731 * structure for Wake On Lan Source Address Hi reg in rxmac address map
732 * located at address 0x4014
739 #define ET_WOL_HI_SA1_SHIFT 8
742 * structure for Wake On Lan mask reg in rxmac address map
743 * located at address 0x4018 - 0x4064
744 * Defined earlier (u32)
748 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
749 * located at address 0x4068
757 #define ET_UNI_PF_ADDR1_3_SHIFT 24
758 #define ET_UNI_PF_ADDR1_4_SHIFT 16
759 #define ET_UNI_PF_ADDR1_5_SHIFT 8
762 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
763 * located at address 0x406C
771 #define ET_UNI_PF_ADDR2_3_SHIFT 24
772 #define ET_UNI_PF_ADDR2_4_SHIFT 16
773 #define ET_UNI_PF_ADDR2_5_SHIFT 8
776 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
777 * located at address 0x4070
785 #define ET_UNI_PF_ADDR2_1_SHIFT 24
786 #define ET_UNI_PF_ADDR2_2_SHIFT 16
787 #define ET_UNI_PF_ADDR1_1_SHIFT 8
791 * structure for Multicast Hash reg in rxmac address map
792 * located at address 0x4074 - 0x4080
793 * Defined earlier (u32)
797 * structure for Packet Filter Control reg in rxmac address map
798 * located at address 0x4084
801 * 22-16: min_pkt_size
810 * structure for Memory Controller Interface Control Max Segment reg in rxmac
811 * address map. Located at address 0x4088
820 * structure for Memory Controller Interface Water Mark reg in rxmac address
821 * map. Located at address 0x408C
830 * structure for Rx Queue Dialog reg in rxmac address map.
831 * located at address 0x4090
840 * structure for space available reg in rxmac address map.
841 * located at address 0x4094
850 * structure for management interface reg in rxmac address map.
851 * located at address 0x4098
855 * 16-0: drop_pkt_mask
859 * structure for Error reg in rxmac address map.
860 * located at address 0x409C
870 * Rx MAC Module of JAGCore Address Mapping
872 struct rxmac_regs { /* Location: */
873 u32 ctrl; /* 0x4000 */
874 u32 crc0; /* 0x4004 */
875 u32 crc12; /* 0x4008 */
876 u32 crc34; /* 0x400C */
877 u32 sa_lo; /* 0x4010 */
878 u32 sa_hi; /* 0x4014 */
879 u32 mask0_word0; /* 0x4018 */
880 u32 mask0_word1; /* 0x401C */
881 u32 mask0_word2; /* 0x4020 */
882 u32 mask0_word3; /* 0x4024 */
883 u32 mask1_word0; /* 0x4028 */
884 u32 mask1_word1; /* 0x402C */
885 u32 mask1_word2; /* 0x4030 */
886 u32 mask1_word3; /* 0x4034 */
887 u32 mask2_word0; /* 0x4038 */
888 u32 mask2_word1; /* 0x403C */
889 u32 mask2_word2; /* 0x4040 */
890 u32 mask2_word3; /* 0x4044 */
891 u32 mask3_word0; /* 0x4048 */
892 u32 mask3_word1; /* 0x404C */
893 u32 mask3_word2; /* 0x4050 */
894 u32 mask3_word3; /* 0x4054 */
895 u32 mask4_word0; /* 0x4058 */
896 u32 mask4_word1; /* 0x405C */
897 u32 mask4_word2; /* 0x4060 */
898 u32 mask4_word3; /* 0x4064 */
899 u32 uni_pf_addr1; /* 0x4068 */
900 u32 uni_pf_addr2; /* 0x406C */
901 u32 uni_pf_addr3; /* 0x4070 */
902 u32 multi_hash1; /* 0x4074 */
903 u32 multi_hash2; /* 0x4078 */
904 u32 multi_hash3; /* 0x407C */
905 u32 multi_hash4; /* 0x4080 */
906 u32 pf_ctrl; /* 0x4084 */
907 u32 mcif_ctrl_max_seg; /* 0x4088 */
908 u32 mcif_water_mark; /* 0x408C */
909 u32 rxq_diag; /* 0x4090 */
910 u32 space_avail; /* 0x4094 */
912 u32 mif_ctrl; /* 0x4098 */
913 u32 err_reg; /* 0x409C */
916 /* END OF RXMAC REGISTER ADDRESS MAP */
919 /* START OF MAC REGISTER ADDRESS MAP */
922 * structure for configuration #1 reg in mac address map.
923 * located at address 0x5000
943 #define CFG1_LOOPBACK 0x00000100
944 #define CFG1_RX_FLOW 0x00000020
945 #define CFG1_TX_FLOW 0x00000010
946 #define CFG1_RX_ENABLE 0x00000004
947 #define CFG1_TX_ENABLE 0x00000001
948 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
951 * structure for configuration #2 reg in mac address map.
952 * located at address 0x5004
968 * structure for Interpacket gap reg in mac address map.
969 * located at address 0x5008
972 * 30-24: non B2B ipg 1
974 * 22-16: non B2B ipg 2
975 * 15-8: Min ifg enforce
978 * structure for half duplex reg in mac address map.
979 * located at address 0x500C
981 * 23-20: Alt BEB trunc
988 * 9-0: collision window
992 * structure for Maximum Frame Length reg in mac address map.
993 * located at address 0x5010: bits 0-15 hold the length.
997 * structure for Reserve 1 reg in mac address map.
998 * located at address 0x5014 - 0x5018
999 * Defined earlier (u32)
1003 * structure for Test reg in mac address map.
1004 * located at address 0x501C
1005 * test: bits 0-2, rest unused
1009 * structure for MII Management Configuration reg in mac address map.
1010 * located at address 0x5020
1012 * 31: reset MII mgmt
1014 * 5: scan auto increment
1015 * 4: preamble suppress
1017 * 2-0: mgmt clock reset
1021 * structure for MII Management Command reg in mac address map.
1022 * located at address 0x5024
1028 * structure for MII Management Address reg in mac address map.
1029 * located at address 0x5028
1036 #define MII_ADDR(phy, reg) ((phy) << 8 | (reg))
1039 * structure for MII Management Control reg in mac address map.
1040 * located at address 0x502C
1046 * structure for MII Management Status reg in mac address map.
1047 * located at address 0x5030
1053 * structure for MII Management Indicators reg in mac address map.
1054 * located at address 0x5034
1061 #define MGMT_BUSY 0x00000001 /* busy */
1062 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1065 * structure for Interface Control reg in mac address map.
1066 * located at address 0x5038
1068 * 31: reset if module
1081 * 8: disable link fail
1084 * 0: enable jabber protection
1088 * structure for Interface Status reg in mac address map.
1089 * located at address 0x503C
1096 * 5: phy_full_duplex
1098 * 3: pe100x_link_fail
1099 * 2: pe10t_loss_carrier
1100 * 1: pe10t_sqe_error
1105 * structure for Mac Station Address, Part 1 reg in mac address map.
1106 * located at address 0x5040
1114 #define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
1115 #define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
1116 #define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
1119 * structure for Mac Station Address, Part 2 reg in mac address map.
1120 * located at address 0x5044
1127 #define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
1128 #define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
1131 * MAC Module of JAGCore Address Mapping
1133 struct mac_regs { /* Location: */
1134 u32 cfg1; /* 0x5000 */
1135 u32 cfg2; /* 0x5004 */
1136 u32 ipg; /* 0x5008 */
1137 u32 hfdp; /* 0x500C */
1138 u32 max_fm_len; /* 0x5010 */
1139 u32 rsv1; /* 0x5014 */
1140 u32 rsv2; /* 0x5018 */
1141 u32 mac_test; /* 0x501C */
1142 u32 mii_mgmt_cfg; /* 0x5020 */
1143 u32 mii_mgmt_cmd; /* 0x5024 */
1144 u32 mii_mgmt_addr; /* 0x5028 */
1145 u32 mii_mgmt_ctrl; /* 0x502C */
1146 u32 mii_mgmt_stat; /* 0x5030 */
1147 u32 mii_mgmt_indicator; /* 0x5034 */
1148 u32 if_ctrl; /* 0x5038 */
1149 u32 if_stat; /* 0x503C */
1150 u32 station_addr_1; /* 0x5040 */
1151 u32 station_addr_2; /* 0x5044 */
1154 /* END OF MAC REGISTER ADDRESS MAP */
1156 /* START OF MAC STAT REGISTER ADDRESS MAP */
1159 * structure for Carry Register One and it's Mask Register reg located in mac
1160 * stat address map address 0x6130 and 0x6138.
1190 * structure for Carry Register Two Mask Register reg in mac stat address map.
1191 * located at address 0x613C
1217 * MAC STATS Module of JAGCore Address Mapping
1219 struct macstat_regs { /* Location: */
1220 u32 pad[32]; /* 0x6000 - 607C */
1222 /* Tx/Rx 0-64 Byte Frame Counter */
1223 u32 txrx_0_64_byte_frames; /* 0x6080 */
1225 /* Tx/Rx 65-127 Byte Frame Counter */
1226 u32 txrx_65_127_byte_frames; /* 0x6084 */
1228 /* Tx/Rx 128-255 Byte Frame Counter */
1229 u32 txrx_128_255_byte_frames; /* 0x6088 */
1231 /* Tx/Rx 256-511 Byte Frame Counter */
1232 u32 txrx_256_511_byte_frames; /* 0x608C */
1234 /* Tx/Rx 512-1023 Byte Frame Counter */
1235 u32 txrx_512_1023_byte_frames; /* 0x6090 */
1237 /* Tx/Rx 1024-1518 Byte Frame Counter */
1238 u32 txrx_1024_1518_byte_frames; /* 0x6094 */
1240 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1241 u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
1243 /* Rx Byte Counter */
1244 u32 rx_bytes; /* 0x609C */
1246 /* Rx Packet Counter */
1247 u32 rx_packets; /* 0x60A0 */
1249 /* Rx FCS Error Counter */
1250 u32 rx_fcs_errs; /* 0x60A4 */
1252 /* Rx Multicast Packet Counter */
1253 u32 rx_multicast_packets; /* 0x60A8 */
1255 /* Rx Broadcast Packet Counter */
1256 u32 rx_broadcast_packets; /* 0x60AC */
1258 /* Rx Control Frame Packet Counter */
1259 u32 rx_control_frames; /* 0x60B0 */
1261 /* Rx Pause Frame Packet Counter */
1262 u32 rx_pause_frames; /* 0x60B4 */
1264 /* Rx Unknown OP Code Counter */
1265 u32 rx_unknown_opcodes; /* 0x60B8 */
1267 /* Rx Alignment Error Counter */
1268 u32 rx_align_errs; /* 0x60BC */
1270 /* Rx Frame Length Error Counter */
1271 u32 rx_frame_len_errs; /* 0x60C0 */
1273 /* Rx Code Error Counter */
1274 u32 rx_code_errs; /* 0x60C4 */
1276 /* Rx Carrier Sense Error Counter */
1277 u32 rx_carrier_sense_errs; /* 0x60C8 */
1279 /* Rx Undersize Packet Counter */
1280 u32 rx_undersize_packets; /* 0x60CC */
1282 /* Rx Oversize Packet Counter */
1283 u32 rx_oversize_packets; /* 0x60D0 */
1285 /* Rx Fragment Counter */
1286 u32 rx_fragment_packets; /* 0x60D4 */
1288 /* Rx Jabber Counter */
1289 u32 rx_jabbers; /* 0x60D8 */
1292 u32 rx_drops; /* 0x60DC */
1294 /* Tx Byte Counter */
1295 u32 tx_bytes; /* 0x60E0 */
1297 /* Tx Packet Counter */
1298 u32 tx_packets; /* 0x60E4 */
1300 /* Tx Multicast Packet Counter */
1301 u32 tx_multicast_packets; /* 0x60E8 */
1303 /* Tx Broadcast Packet Counter */
1304 u32 tx_broadcast_packets; /* 0x60EC */
1306 /* Tx Pause Control Frame Counter */
1307 u32 tx_pause_frames; /* 0x60F0 */
1309 /* Tx Deferral Packet Counter */
1310 u32 tx_deferred; /* 0x60F4 */
1312 /* Tx Excessive Deferral Packet Counter */
1313 u32 tx_excessive_deferred; /* 0x60F8 */
1315 /* Tx Single Collision Packet Counter */
1316 u32 tx_single_collisions; /* 0x60FC */
1318 /* Tx Multiple Collision Packet Counter */
1319 u32 tx_multiple_collisions; /* 0x6100 */
1321 /* Tx Late Collision Packet Counter */
1322 u32 tx_late_collisions; /* 0x6104 */
1324 /* Tx Excessive Collision Packet Counter */
1325 u32 tx_excessive_collisions; /* 0x6108 */
1327 /* Tx Total Collision Packet Counter */
1328 u32 tx_total_collisions; /* 0x610C */
1330 /* Tx Pause Frame Honored Counter */
1331 u32 tx_pause_honored_frames; /* 0x6110 */
1333 /* Tx Drop Frame Counter */
1334 u32 tx_drops; /* 0x6114 */
1336 /* Tx Jabber Frame Counter */
1337 u32 tx_jabbers; /* 0x6118 */
1339 /* Tx FCS Error Counter */
1340 u32 tx_fcs_errs; /* 0x611C */
1342 /* Tx Control Frame Counter */
1343 u32 tx_control_frames; /* 0x6120 */
1345 /* Tx Oversize Frame Counter */
1346 u32 tx_oversize_frames; /* 0x6124 */
1348 /* Tx Undersize Frame Counter */
1349 u32 tx_undersize_frames; /* 0x6128 */
1351 /* Tx Fragments Frame Counter */
1352 u32 tx_fragments; /* 0x612C */
1354 /* Carry Register One Register */
1355 u32 carry_reg1; /* 0x6130 */
1357 /* Carry Register Two Register */
1358 u32 carry_reg2; /* 0x6134 */
1360 /* Carry Register One Mask Register */
1361 u32 carry_reg1_mask; /* 0x6138 */
1363 /* Carry Register Two Mask Register */
1364 u32 carry_reg2_mask; /* 0x613C */
1367 /* END OF MAC STAT REGISTER ADDRESS MAP */
1369 /* START OF MMC REGISTER ADDRESS MAP */
1372 * Main Memory Controller Control reg in mmc address map.
1373 * located at address 0x7000
1376 #define ET_MMC_ENABLE 1
1377 #define ET_MMC_ARB_DISABLE 2
1378 #define ET_MMC_RXMAC_DISABLE 4
1379 #define ET_MMC_TXMAC_DISABLE 8
1380 #define ET_MMC_TXDMA_DISABLE 16
1381 #define ET_MMC_RXDMA_DISABLE 32
1382 #define ET_MMC_FORCE_CE 64
1385 * Main Memory Controller Host Memory Access Address reg in mmc
1386 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1389 #define ET_SRAM_REQ_ACCESS 1
1390 #define ET_SRAM_WR_ACCESS 2
1391 #define ET_SRAM_IS_CTRL 4
1394 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1395 * address map. Located at address 0x7008 - 0x7014
1396 * Defined earlier (u32)
1400 * Memory Control Module of JAGCore Address Mapping
1402 struct mmc_regs { /* Location: */
1403 u32 mmc_ctrl; /* 0x7000 */
1404 u32 sram_access; /* 0x7004 */
1405 u32 sram_word1; /* 0x7008 */
1406 u32 sram_word2; /* 0x700C */
1407 u32 sram_word3; /* 0x7010 */
1408 u32 sram_word4; /* 0x7014 */
1411 /* END OF MMC REGISTER ADDRESS MAP */
1415 * JAGCore Address Mapping
1417 struct address_map {
1418 struct global_regs global;
1419 /* unused section of global address map */
1420 u8 unused_global[4096 - sizeof(struct global_regs)];
1421 struct txdma_regs txdma;
1422 /* unused section of txdma address map */
1423 u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1424 struct rxdma_regs rxdma;
1425 /* unused section of rxdma address map */
1426 u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1427 struct txmac_regs txmac;
1428 /* unused section of txmac address map */
1429 u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1430 struct rxmac_regs rxmac;
1431 /* unused section of rxmac address map */
1432 u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
1433 struct mac_regs mac;
1434 /* unused section of mac address map */
1435 u8 unused_mac[4096 - sizeof(struct mac_regs)];
1436 struct macstat_regs macstat;
1437 /* unused section of mac stat address map */
1438 u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1439 struct mmc_regs mmc;
1440 /* unused section of mmc address map */
1441 u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1442 /* unused section of address map */
1443 u8 unused_[1015808];
1445 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1446 u8 unused__[524288]; /* unused section of address map */
1450 * Defines for generic MII registers 0x00 -> 0x0F can be found in
1451 * include/linux/mii.h
1454 /* some defines for modem registers that seem to be 'reserved' */
1455 #define PHY_INDEX_REG 0x10
1456 #define PHY_DATA_REG 0x11
1457 #define PHY_MPHY_CONTROL_REG 0x12
1459 /* defines for specified registers */
1460 #define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
1461 /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
1462 #define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
1463 #define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
1464 #define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
1465 #define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
1466 #define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
1467 #define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
1468 #define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
1469 #define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
1470 /* TRU_VMI_LINK_CONTROL_REG 29 */
1471 /* TRU_VMI_TIMING_CONTROL_REG */
1473 /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
1474 #define ET_1000BT_MSTR_SLV 0x4000
1476 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
1478 /* MI Register 19: Loopback Control Reg(0x13)
1482 * 12: all_digital_en
1484 * 10: line_driver_en
1488 /* MI Register 20: Reserved Reg(0x14) */
1490 /* MI Register 21: Management Interface Control Reg(0x15)
1492 * 10-4: mi_error_count
1496 * 0: preamble_suppress_en
1499 /* MI Register 22: PHY Configuration Reg(0x16)
1502 * 13-12: tx_fifo_depth
1503 * 11-10: speed_downshift
1514 #define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
1516 #define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
1517 #define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
1518 #define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
1519 #define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
1521 /* MI Register 23: PHY CONTROL Reg(0x17)
1525 * 12-11: downshift_attempts
1529 * 3: tp_loopback_10baseT
1530 * 2: preamble_gen_en
1535 /* MI Register 24: Interrupt Mask Reg(0x18)
1541 * 5: err_counter_full
1542 * 4: fifo_over_underflow
1545 * 1: automatic_speed
1549 /* MI Register 25: Interrupt Status Reg(0x19)
1555 * 5: err_counter_full
1556 * 4: fifo_over_underflow
1559 * 1: automatic_speed
1563 /* MI Register 26: PHY Status Reg(0x1A)
1565 * 14-13: autoneg_fault
1566 * 12: autoneg_status
1568 * 10: polarity_status
1574 * 3: collision_status
1579 #define ET_PHY_AUTONEG_STATUS 0x1000
1580 #define ET_PHY_POLARITY_STATUS 0x0400
1581 #define ET_PHY_SPEED_STATUS 0x0300
1582 #define ET_PHY_DUPLEX_STATUS 0x0080
1583 #define ET_PHY_LSTATUS 0x0040
1584 #define ET_PHY_AUTONEG_ENABLE 0x0020
1586 /* MI Register 27: LED Control Reg 1(0x1B)
1588 * 13-12: led_dup_indicate
1589 * 11-10: led_10baseT
1590 * 9-8: led_collision
1597 /* MI Register 28: LED Control Reg 2(0x1C)
1600 * 7-4: led_100BaseTX
1601 * 3-0: led_1000BaseT
1603 #define ET_LED2_LED_LINK 0xF000
1604 #define ET_LED2_LED_TXRX 0x0F00
1605 #define ET_LED2_LED_100TX 0x00F0
1606 #define ET_LED2_LED_1000T 0x000F
1608 /* defines for LED control reg 2 values */
1609 #define LED_VAL_1000BT 0x0
1610 #define LED_VAL_100BTX 0x1
1611 #define LED_VAL_10BT 0x2
1612 #define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
1613 #define LED_VAL_LINKON 0x4
1614 #define LED_VAL_TX 0x5
1615 #define LED_VAL_RX 0x6
1616 #define LED_VAL_TXRX 0x7 /* TX or RX */
1617 #define LED_VAL_DUPLEXFULL 0x8
1618 #define LED_VAL_COLLISION 0x9
1619 #define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
1620 #define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
1621 #define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
1622 #define LED_VAL_BLINK 0xD
1623 #define LED_VAL_ON 0xE
1624 #define LED_VAL_OFF 0xF
1626 #define LED_LINK_SHIFT 12
1627 #define LED_TXRX_SHIFT 8
1628 #define LED_100TX_SHIFT 4
1630 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
1632 /* Defines for PHY access routines */
1634 /* Define bit operation flags */
1635 #define TRUEPHY_BIT_CLEAR 0
1636 #define TRUEPHY_BIT_SET 1
1637 #define TRUEPHY_BIT_READ 2
1639 /* Define read/write operation flags */
1640 #ifndef TRUEPHY_READ
1641 #define TRUEPHY_READ 0
1642 #define TRUEPHY_WRITE 1
1643 #define TRUEPHY_MASK 2
1646 /* Define master/slave configuration values */
1647 #define TRUEPHY_CFG_SLAVE 0
1648 #define TRUEPHY_CFG_MASTER 1
1650 /* Define MDI/MDI-X settings */
1651 #define TRUEPHY_MDI 0
1652 #define TRUEPHY_MDIX 1
1653 #define TRUEPHY_AUTO_MDI_MDIX 2
1655 /* Define 10Base-T link polarities */
1656 #define TRUEPHY_POLARITY_NORMAL 0
1657 #define TRUEPHY_POLARITY_INVERTED 1
1659 /* Define auto-negotiation results */
1660 #define TRUEPHY_ANEG_NOT_COMPLETE 0
1661 #define TRUEPHY_ANEG_COMPLETE 1
1662 #define TRUEPHY_ANEG_DISABLED 2
1664 /* Define duplex advertisement flags */
1665 #define TRUEPHY_ADV_DUPLEX_NONE 0x00
1666 #define TRUEPHY_ADV_DUPLEX_FULL 0x01
1667 #define TRUEPHY_ADV_DUPLEX_HALF 0x02
1668 #define TRUEPHY_ADV_DUPLEX_BOTH \
1669 (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)