3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_tx.c - Routines used to perform data transmission.
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et1310_pm.h"
88 #include "et1310_jagcore.h"
90 #include "et131x_adapter.h"
91 #include "et131x_initpci.h"
92 #include "et131x_isr.h"
94 #include "et1310_tx.h"
97 static inline void et131x_free_send_packet(struct et131x_adapter *etdev,
99 static int et131x_send_packet(struct sk_buff *skb,
100 struct et131x_adapter *etdev);
101 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb);
104 * et131x_tx_dma_memory_alloc
105 * @adapter: pointer to our private adapter structure
107 * Returns 0 on success and errno on failure (as defined in errno.h).
109 * Allocates memory that will be visible both to the device and to the CPU.
110 * The OS will pass us packets, pointers to which we will insert in the Tx
111 * Descriptor queue. The device will read this queue to find the packets in
112 * memory. The device will update the "status" in memory each time it xmits a
115 int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
118 struct tx_ring *tx_ring = &adapter->tx_ring;
120 /* Allocate memory for the TCB's (Transmit Control Block) */
121 adapter->tx_ring.tcb_ring = (struct tcb *)
122 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
123 if (!adapter->tx_ring.tcb_ring) {
124 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
128 /* Allocate enough memory for the Tx descriptor ring, and allocate
129 * some extra so that the ring can be aligned on a 4k boundary.
131 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
132 tx_ring->tx_desc_ring =
133 (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
134 &tx_ring->tx_desc_ring_pa);
135 if (!adapter->tx_ring.tx_desc_ring) {
136 dev_err(&adapter->pdev->dev,
137 "Cannot alloc memory for Tx Ring\n");
141 /* Save physical address
143 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
144 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
145 * are ever returned, make sure the high part is retrieved here before
146 * storing the adjusted address.
148 /* Allocate memory for the Tx status block */
149 tx_ring->tx_status = pci_alloc_consistent(adapter->pdev,
151 &tx_ring->tx_status_pa);
152 if (!adapter->tx_ring.tx_status_pa) {
153 dev_err(&adapter->pdev->dev,
154 "Cannot alloc memory for Tx status block\n");
161 * et131x_tx_dma_memory_free - Free all memory allocated within this module
162 * @adapter: pointer to our private adapter structure
164 * Returns 0 on success and errno on failure (as defined in errno.h).
166 void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
170 if (adapter->tx_ring.tx_desc_ring) {
171 /* Free memory relating to Tx rings here */
172 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
174 pci_free_consistent(adapter->pdev,
176 adapter->tx_ring.tx_desc_ring,
177 adapter->tx_ring.tx_desc_ring_pa);
178 adapter->tx_ring.tx_desc_ring = NULL;
181 /* Free memory for the Tx status block */
182 if (adapter->tx_ring.tx_status) {
183 pci_free_consistent(adapter->pdev,
185 adapter->tx_ring.tx_status,
186 adapter->tx_ring.tx_status_pa);
188 adapter->tx_ring.tx_status = NULL;
190 /* Free the memory for the tcb structures */
191 kfree(adapter->tx_ring.tcb_ring);
195 * ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
196 * @etdev: pointer to our private adapter structure
198 * Configure the transmit engine with the ring buffers we have created
199 * and prepare it for use.
201 void ConfigTxDmaRegs(struct et131x_adapter *etdev)
203 struct txdma_regs __iomem *txdma = &etdev->regs->txdma;
205 /* Load the hardware with the start of the transmit descriptor ring. */
206 writel((u32) ((u64)etdev->tx_ring.tx_desc_ring_pa >> 32),
208 writel((u32) etdev->tx_ring.tx_desc_ring_pa,
211 /* Initialise the transmit DMA engine */
212 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
214 /* Load the completion writeback physical address */
215 writel((u32)((u64)etdev->tx_ring.tx_status_pa >> 32),
216 &txdma->dma_wb_base_hi);
217 writel((u32)etdev->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo);
219 *etdev->tx_ring.tx_status = 0;
221 writel(0, &txdma->service_request);
222 etdev->tx_ring.send_idx = 0;
226 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
227 * @etdev: pointer to our adapter structure
229 void et131x_tx_dma_disable(struct et131x_adapter *etdev)
231 /* Setup the tramsmit dma configuration register */
232 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
233 &etdev->regs->txdma.csr);
237 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
238 * @etdev: pointer to our adapter structure
240 * Mainly used after a return to the D0 (full-power) state from a lower state.
242 void et131x_tx_dma_enable(struct et131x_adapter *etdev)
244 /* Setup the transmit dma configuration register for normal
247 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
248 &etdev->regs->txdma.csr);
252 * et131x_init_send - Initialize send data structures
253 * @adapter: pointer to our private adapter structure
255 void et131x_init_send(struct et131x_adapter *adapter)
259 struct tx_ring *tx_ring;
261 /* Setup some convenience pointers */
262 tx_ring = &adapter->tx_ring;
263 tcb = adapter->tx_ring.tcb_ring;
265 tx_ring->tcb_qhead = tcb;
267 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
269 /* Go through and set up each TCB */
270 for (ct = 0; ct++ < NUM_TCB; tcb++)
271 /* Set the link pointer in HW TCB to the next TCB in the
276 /* Set the tail pointer */
278 tx_ring->tcb_qtail = tcb;
280 /* Curr send queue should now be empty */
281 tx_ring->send_head = NULL;
282 tx_ring->send_tail = NULL;
286 * et131x_send_packets - This function is called by the OS to send packets
287 * @skb: the packet(s) to send
288 * @netdev:device on which to TX the above packet(s)
290 * Return 0 in almost all cases; non-zero value in extreme hard failure only
292 int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
295 struct et131x_adapter *etdev = NULL;
297 etdev = netdev_priv(netdev);
299 /* Send these packets
301 * NOTE: The Linux Tx entry point is only given one packet at a time
302 * to Tx, so the PacketCount and it's array used makes no sense here
305 /* TCB is not available */
306 if (etdev->tx_ring.used >= NUM_TCB) {
307 /* NOTE: If there's an error on send, no need to queue the
308 * packet under Linux; if we just send an error up to the
309 * netif layer, it will resend the skb to us.
313 /* We need to see if the link is up; if it's not, make the
314 * netif layer think we're good and drop the packet
316 if ((etdev->Flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
317 !netif_carrier_ok(netdev)) {
318 dev_kfree_skb_any(skb);
321 etdev->net_stats.tx_dropped++;
323 status = et131x_send_packet(skb, etdev);
324 if (status != 0 && status != -ENOMEM) {
325 /* On any other error, make netif think we're
326 * OK and drop the packet
328 dev_kfree_skb_any(skb);
330 etdev->net_stats.tx_dropped++;
338 * et131x_send_packet - Do the work to send a packet
339 * @skb: the packet(s) to send
340 * @etdev: a pointer to the device's private adapter structure
342 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
344 * Assumption: Send spinlock has been acquired
346 static int et131x_send_packet(struct sk_buff *skb,
347 struct et131x_adapter *etdev)
350 struct tcb *tcb = NULL;
354 /* All packets must have at least a MAC address and a protocol type */
355 if (skb->len < ETH_HLEN)
358 /* Get a TCB for this packet */
359 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
361 tcb = etdev->tx_ring.tcb_qhead;
364 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
368 etdev->tx_ring.tcb_qhead = tcb->next;
370 if (etdev->tx_ring.tcb_qhead == NULL)
371 etdev->tx_ring.tcb_qtail = NULL;
373 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
377 if (skb->data != NULL && skb->len - skb->data_len >= 6) {
378 shbufva = (u16 *) skb->data;
380 if ((shbufva[0] == 0xffff) &&
381 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
382 tcb->flags |= fMP_DEST_BROAD;
383 } else if ((shbufva[0] & 0x3) == 0x0001) {
384 tcb->flags |= fMP_DEST_MULTI;
390 /* Call the NIC specific send handler. */
391 status = nic_send_packet(etdev, tcb);
394 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
396 if (etdev->tx_ring.tcb_qtail)
397 etdev->tx_ring.tcb_qtail->next = tcb;
399 /* Apparently ready Q is empty. */
400 etdev->tx_ring.tcb_qhead = tcb;
402 etdev->tx_ring.tcb_qtail = tcb;
403 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
406 WARN_ON(etdev->tx_ring.used > NUM_TCB);
411 * nic_send_packet - NIC specific send handler for version B silicon.
412 * @etdev: pointer to our adapter
413 * @tcb: pointer to struct tcb
415 * Returns 0 or errno.
417 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
420 struct tx_desc desc[24]; /* 24 x 16 byte */
422 u32 thiscopy, remainder;
423 struct sk_buff *skb = tcb->skb;
424 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
425 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
428 /* Part of the optimizations of this send routine restrict us to
429 * sending 24 fragments at a pass. In practice we should never see
430 * more than 5 fragments.
432 * NOTE: The older version of this function (below) can handle any
433 * number of fragments. If needed, we can call this function,
434 * although it is less efficient.
439 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
441 for (i = 0; i < nr_frags; i++) {
442 /* If there is something in this element, lets get a
443 * descriptor from the ring and get the necessary data
446 /* If the fragments are smaller than a standard MTU,
447 * then map them to a single descriptor in the Tx
448 * Desc ring. However, if they're larger, as is
449 * possible with support for jumbo packets, then
450 * split them each across 2 descriptors.
452 * This will work until we determine why the hardware
453 * doesn't seem to like large fragments.
455 if ((skb->len - skb->data_len) <= 1514) {
456 desc[frag].addr_hi = 0;
457 /* Low 16bits are length, high is vlan and
458 unused currently so zero */
459 desc[frag].len_vlan =
460 skb->len - skb->data_len;
462 /* NOTE: Here, the dma_addr_t returned from
463 * pci_map_single() is implicitly cast as a
464 * u32. Although dma_addr_t can be
465 * 64-bit, the address returned by
466 * pci_map_single() is always 32-bit
467 * addressable (as defined by the pci/dma
470 desc[frag++].addr_lo =
471 pci_map_single(etdev->pdev,
477 desc[frag].addr_hi = 0;
478 desc[frag].len_vlan =
479 (skb->len - skb->data_len) / 2;
481 /* NOTE: Here, the dma_addr_t returned from
482 * pci_map_single() is implicitly cast as a
483 * u32. Although dma_addr_t can be
484 * 64-bit, the address returned by
485 * pci_map_single() is always 32-bit
486 * addressable (as defined by the pci/dma
489 desc[frag++].addr_lo =
490 pci_map_single(etdev->pdev,
495 desc[frag].addr_hi = 0;
497 desc[frag].len_vlan =
498 (skb->len - skb->data_len) / 2;
500 /* NOTE: Here, the dma_addr_t returned from
501 * pci_map_single() is implicitly cast as a
502 * u32. Although dma_addr_t can be
503 * 64-bit, the address returned by
504 * pci_map_single() is always 32-bit
505 * addressable (as defined by the pci/dma
508 desc[frag++].addr_lo =
509 pci_map_single(etdev->pdev,
518 desc[frag].addr_hi = 0;
519 desc[frag].len_vlan =
522 /* NOTE: Here, the dma_addr_t returned from
523 * pci_map_page() is implicitly cast as a u32.
524 * Although dma_addr_t can be 64-bit, the address
525 * returned by pci_map_page() is always 32-bit
526 * addressable (as defined by the pci/dma subsystem)
528 desc[frag++].addr_lo =
529 pci_map_page(etdev->pdev,
531 frags[i - 1].page_offset,
540 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
541 if (++etdev->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
542 /* Last element & Interrupt flag */
543 desc[frag - 1].flags = 0x5;
544 etdev->tx_ring.since_irq = 0;
545 } else { /* Last element */
546 desc[frag - 1].flags = 0x1;
549 desc[frag - 1].flags = 0x5;
551 desc[0].flags |= 2; /* First element flag */
553 tcb->index_start = etdev->tx_ring.send_idx;
556 spin_lock_irqsave(&etdev->SendHWLock, flags);
558 thiscopy = NUM_DESC_PER_RING_TX -
559 INDEX10(etdev->tx_ring.send_idx);
561 if (thiscopy >= frag) {
565 remainder = frag - thiscopy;
568 memcpy(etdev->tx_ring.tx_desc_ring +
569 INDEX10(etdev->tx_ring.send_idx), desc,
570 sizeof(struct tx_desc) * thiscopy);
572 add_10bit(&etdev->tx_ring.send_idx, thiscopy);
574 if (INDEX10(etdev->tx_ring.send_idx) == 0 ||
575 INDEX10(etdev->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
576 etdev->tx_ring.send_idx &= ~ET_DMA10_MASK;
577 etdev->tx_ring.send_idx ^= ET_DMA10_WRAP;
581 memcpy(etdev->tx_ring.tx_desc_ring,
583 sizeof(struct tx_desc) * remainder);
585 add_10bit(&etdev->tx_ring.send_idx, remainder);
588 if (INDEX10(etdev->tx_ring.send_idx) == 0) {
589 if (etdev->tx_ring.send_idx)
590 tcb->index = NUM_DESC_PER_RING_TX - 1;
592 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
594 tcb->index = etdev->tx_ring.send_idx - 1;
596 spin_lock(&etdev->TCBSendQLock);
598 if (etdev->tx_ring.send_tail)
599 etdev->tx_ring.send_tail->next = tcb;
601 etdev->tx_ring.send_head = tcb;
603 etdev->tx_ring.send_tail = tcb;
605 WARN_ON(tcb->next != NULL);
607 etdev->tx_ring.used++;
609 spin_unlock(&etdev->TCBSendQLock);
611 /* Write the new write pointer back to the device. */
612 writel(etdev->tx_ring.send_idx,
613 &etdev->regs->txdma.service_request);
615 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
616 * timer to wake us up if this packet isn't followed by N more.
618 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
619 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
620 &etdev->regs->global.watchdog_timer);
622 spin_unlock_irqrestore(&etdev->SendHWLock, flags);
629 * et131x_free_send_packet - Recycle a struct tcb
630 * @etdev: pointer to our adapter
631 * @tcb: pointer to struct tcb
633 * Complete the packet if necessary
634 * Assumption - Send spinlock has been acquired
636 inline void et131x_free_send_packet(struct et131x_adapter *etdev,
640 struct tx_desc *desc = NULL;
641 struct net_device_stats *stats = &etdev->net_stats;
643 if (tcb->flags & fMP_DEST_BROAD)
644 atomic_inc(&etdev->Stats.brdcstxmt);
645 else if (tcb->flags & fMP_DEST_MULTI)
646 atomic_inc(&etdev->Stats.multixmt);
648 atomic_inc(&etdev->Stats.unixmt);
651 stats->tx_bytes += tcb->skb->len;
653 /* Iterate through the TX descriptors on the ring
654 * corresponding to this packet and umap the fragments
658 desc = (struct tx_desc *)(etdev->tx_ring.tx_desc_ring +
659 INDEX10(tcb->index_start));
661 pci_unmap_single(etdev->pdev,
663 desc->len_vlan, PCI_DMA_TODEVICE);
665 add_10bit(&tcb->index_start, 1);
666 if (INDEX10(tcb->index_start) >=
667 NUM_DESC_PER_RING_TX) {
668 tcb->index_start &= ~ET_DMA10_MASK;
669 tcb->index_start ^= ET_DMA10_WRAP;
671 } while (desc != (etdev->tx_ring.tx_desc_ring +
672 INDEX10(tcb->index)));
674 dev_kfree_skb_any(tcb->skb);
677 memset(tcb, 0, sizeof(struct tcb));
679 /* Add the TCB to the Ready Q */
680 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
682 etdev->Stats.opackets++;
684 if (etdev->tx_ring.tcb_qtail)
685 etdev->tx_ring.tcb_qtail->next = tcb;
687 /* Apparently ready Q is empty. */
688 etdev->tx_ring.tcb_qhead = tcb;
690 etdev->tx_ring.tcb_qtail = tcb;
692 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
693 WARN_ON(etdev->tx_ring.used < 0);
697 * et131x_free_busy_send_packets - Free and complete the stopped active sends
698 * @etdev: pointer to our adapter
700 * Assumption - Send spinlock has been acquired
702 void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
708 /* Any packets being sent? Check the first TCB on the send list */
709 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
711 tcb = etdev->tx_ring.send_head;
713 while (tcb != NULL && freed < NUM_TCB) {
714 struct tcb *next = tcb->next;
716 etdev->tx_ring.send_head = next;
719 etdev->tx_ring.send_tail = NULL;
721 etdev->tx_ring.used--;
723 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
726 et131x_free_send_packet(etdev, tcb);
728 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
730 tcb = etdev->tx_ring.send_head;
733 WARN_ON(freed == NUM_TCB);
735 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
737 etdev->tx_ring.used = 0;
741 * et131x_handle_send_interrupt - Interrupt handler for sending processing
742 * @etdev: pointer to our adapter
744 * Re-claim the send resources, complete sends and get more to send from
745 * the send wait queue.
747 * Assumption - Send spinlock has been acquired
749 void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
756 serviced = readl(&etdev->regs->txdma.NewServiceComplete);
757 index = INDEX10(serviced);
759 /* Has the ring wrapped? Process any descriptors that do not have
760 * the same "wrap" indicator as the current completion indicator
762 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
764 tcb = etdev->tx_ring.send_head;
767 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
768 index < INDEX10(tcb->index)) {
769 etdev->tx_ring.used--;
770 etdev->tx_ring.send_head = tcb->next;
771 if (tcb->next == NULL)
772 etdev->tx_ring.send_tail = NULL;
774 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
775 et131x_free_send_packet(etdev, tcb);
776 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
778 /* Goto the next packet */
779 tcb = etdev->tx_ring.send_head;
782 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
783 && index > (tcb->index & ET_DMA10_MASK)) {
784 etdev->tx_ring.used--;
785 etdev->tx_ring.send_head = tcb->next;
786 if (tcb->next == NULL)
787 etdev->tx_ring.send_tail = NULL;
789 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
790 et131x_free_send_packet(etdev, tcb);
791 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
793 /* Goto the next packet */
794 tcb = etdev->tx_ring.send_head;
797 /* Wake up the queue when we hit a low-water mark */
798 if (etdev->tx_ring.used <= NUM_TCB / 3)
799 netif_wake_queue(etdev->netdev);
801 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);