2 tristate "DesignWare USB2 DRD Core Support"
6 Say Y or M here if your system has a Dual Role HighSpeed
7 USB controller based on the DesignWare HSOTG IP Core.
9 If you choose to build this driver as dynamically linked
10 modules, the core module will be called dwc2.ko, the
11 PCI bus interface module (if you have a PCI bus system)
12 will be called dwc2_pci.ko and the platform interface module
13 (for controllers directly connected to the CPU) will be called
16 NOTE: This driver at present only implements the Host mode
17 of the controller. The existing s3c-hsotg driver supports
18 Peripheral mode, but only for the Samsung S3C platforms.
19 There are plans to merge the s3c-hsotg driver with this
20 driver in the near future to create a dual-role driver.
25 bool "Enable Debugging Messages"
27 Say Y here to enable debugging messages in the DWC2 Driver.
29 config USB_DWC2_VERBOSE
30 bool "Enable Verbose Debugging Messages"
31 depends on USB_DWC2_DEBUG
33 Say Y here to enable verbose debugging messages in the DWC2 Driver.
34 WARNING: Enabling this will quickly fill your message log.
37 config USB_DWC2_TRACK_MISSED_SOFS
38 bool "Enable Missed SOF Tracking"
40 Say Y here to enable logging of missed SOF events to the dmesg log.
41 WARNING: This feature is still experimental.
44 config USB_DWC2_DEBUG_PERIODIC
45 bool "Enable Debugging Messages For Periodic Transfers"
46 depends on USB_DWC2_DEBUG || USB_DWC2_VERBOSE
49 Say N here to disable (verbose) debugging messages to be
50 logged for periodic transfers. This allows better debugging of
51 non-periodic transfers, but of course the debug logs will be
52 incomplete. Note that this also disables some debug messages
53 for which the transfer type cannot be deduced.