4 * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
6 ********************************************************************
8 * Copyright (C) 1999 RG Studio s.c.
9 * Written by Krzysztof Halasa <khc@rgstudio.com.pl>
11 * Portions (C) SBE Inc., used by permission.
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #ifndef __COMEDI_PLX9080_H
20 #define __COMEDI_PLX9080_H
23 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
24 * @pci_start_addr: PCI Bus address for transfer (DMAPADR).
25 * @local_start_addr: Local Bus address for transfer (DMALADR).
26 * @transfer_size: Transfer size in bytes (max 8 MiB) (DMASIZ).
27 * @next: Address of next descriptor + flags (DMADPR).
29 * Describes the format of a scatter-gather DMA descriptor for the PLX
30 * PCI 9080. All members are raw, little-endian register values that
31 * will be transferred by the DMA engine from local or PCI memory into
32 * corresponding registers for the DMA channel.
34 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
35 * of @next contain flags describing the address space of the next
36 * descriptor (local or PCI), an "end of chain" marker, an "interrupt on
37 * terminal count" bit, and a data transfer direction.
40 __le32 pci_start_addr;
41 __le32 local_start_addr;
47 * Register Offsets and Bit Definitions
50 /* Local Address Space 0 Range Register */
51 #define PLX_REG_LAS0RR 0x0000
52 /* Local Address Space 1 Range Register */
53 #define PLX_REG_LAS1RR 0x00f0
55 #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
56 #define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
57 #define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
58 #define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
59 #define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */
60 #define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
61 /* bits that specify range for memory space decode bits */
62 #define PLX_LASRR_MEM_MASK GENMASK(31, 4)
63 /* bits that specify range for i/o space decode bits */
64 #define PLX_LASRR_IO_MASK GENMASK(31, 2)
66 /* Local Address Space 0 Local Base Address (Remap) Register */
67 #define PLX_REG_LAS0BA 0x0004
68 /* Local Address Space 1 Local Base Address (Remap) Register */
69 #define PLX_REG_LAS1BA 0x00f4
71 #define PLX_LASBA_EN BIT(0) /* Enable slave decode */
72 /* bits that specify local base address for memory space */
73 #define PLX_LASBA_MEM_MASK GENMASK(31, 4)
74 /* bits that specify local base address for i/o space */
75 #define PLX_LASBA_IO_MASK GENMASK(31, 2)
77 /* Mode/Arbitration Register */
78 #define PLX_REG_MARBR 0x0008
79 /* DMA Arbitration Register (alias of MARBR). */
80 #define PLX_REG_DMAARB 0x00ac
82 /* Local Bus Latency Timer */
83 #define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff))
84 #define PLX_MARBR_LT_MASK GENMASK(7, 0)
85 #define PLX_MARBR_LT_SHIFT 0
86 /* Local Bus Pause Timer */
87 #define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff))
88 #define PLX_MARBR_PT_MASK GENMASK(15, 8)
89 #define PLX_MARBR_PT_SHIFT 8
90 /* Local Bus Latency Timer Enable */
91 #define PLX_MARBR_LTEN BIT(16)
92 /* Local Bus Pause Timer Enable */
93 #define PLX_MARBR_PTEN BIT(17)
94 /* Local Bus BREQ Enable */
95 #define PLX_MARBR_BREQEN BIT(18)
96 /* DMA Channel Priority */
97 #define PLX_MARBR_PRIO_ROT (BIT(19) * 0) /* Rotational priority */
98 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
99 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
100 #define PLX_MARBR_PRIO_MASK GENMASK(20, 19)
101 /* Local Bus Direct Slave Give Up Bus Mode */
102 #define PLX_MARBR_DSGUBM BIT(21)
103 /* Direct Slace LLOCKo# Enable */
104 #define PLX_MARBR_DSLLOCKOEN BIT(22)
105 /* PCI Request Mode */
106 #define PLX_MARBR_PCIREQM BIT(23)
107 /* PCI Specification v2.1 Mode */
108 #define PLX_MARBR_PCIV21M BIT(24)
109 /* PCI Read No Write Mode */
110 #define PLX_MARBR_PCIRNWM BIT(25)
111 /* PCI Read with Write Flush Mode */
112 #define PLX_MARBR_PCIRWFM BIT(26)
113 /* Gate Local Bus Latency Timer with BREQ */
114 #define PLX_MARBR_GLTBREQ BIT(27)
115 /* PCI Read No Flush Mode */
116 #define PLX_MARBR_PCIRNFM BIT(28)
118 * Make reads from PCI Configuration register 0 return Subsystem ID and
119 * Subsystem Vendor ID instead of Device ID and Vendor ID
121 #define PLX_MARBR_SUBSYSIDS BIT(29)
123 /* Big/Little Endian Descriptor Register */
124 #define PLX_REG_BIGEND 0x000c
126 /* Configuration Register Big Endian Mode */
127 #define PLX_BIGEND_CONFIG BIT(0)
128 /* Direct Master Big Endian Mode */
129 #define PLX_BIGEND_DM BIT(1)
130 /* Direct Slave Address Space 0 Big Endian Mode */
131 #define PLX_BIGEND_DSAS0 BIT(2)
132 /* Direct Slave Expansion ROM Big Endian Mode */
133 #define PLX_BIGEND_EROM BIT(3)
134 /* Big Endian Byte Lane Mode - use most significant byte lanes */
135 #define PLX_BIGEND_BEBLM BIT(4)
136 /* Direct Slave Address Space 1 Big Endian Mode */
137 #define PLX_BIGEND_DSAS1 BIT(5)
138 /* DMA Channel 1 Big Endian Mode */
139 #define PLX_BIGEND_DMA1 BIT(6)
140 /* DMA Channel 0 Big Endian Mode */
141 #define PLX_BIGEND_DMA0 BIT(7)
142 /* DMA Channel N Big Endian Mode (N <= 1) */
143 #define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)
146 * Note: The Expansion ROM stuff is only relevant to the PC environment.
147 * This expansion ROM code is executed by the host CPU at boot time.
148 * For this reason no bit definitions are provided here.
151 /* Expansion ROM Range Register */
152 #define PLX_REG_EROMRR 0x0010
153 /* Expansion ROM Local Base Address (Remap) Register */
154 #define PLX_REG_EROMBA 0x0014
156 /* Local Address Space 0/Expansion ROM Bus Region Descriptor Register */
157 #define PLX_REG_LBRD0 0x0018
158 /* Local Address Space 1 Bus Region Descriptor Register */
159 #define PLX_REG_LBRD1 0x00f8
161 /* Memory Space Local Bus Width */
162 #define PLX_LBRD_MSWIDTH8 (BIT(0) * 0) /* 8 bits wide */
163 #define PLX_LBRD_MSWIDTH16 (BIT(0) * 1) /* 16 bits wide */
164 #define PLX_LBRD_MSWIDTH32 (BIT(0) * 2) /* 32 bits wide */
165 #define PLX_LBRD_MSWIDTH32A (BIT(0) * 3) /* 32 bits wide */
166 #define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0)
167 #define PLX_LBRD_MSWIDTH_SHIFT 0
168 /* Memory Space Internal Wait States */
169 #define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf))
170 #define PLX_LBRD_MSIWS_MASK GENMASK(5, 2)
171 #define PLX_LBRD_MSIWS_SHIFT 2
172 /* Memory Space Ready Input Enable */
173 #define PLX_LBRD_MSREADYIEN BIT(6)
174 /* Memory Space BTERM# Input Enable */
175 #define PLX_LBRD_MSBTERMIEN BIT(7)
176 /* Memory Space 0 Prefetch Disable (LBRD0 only) */
177 #define PLX_LBRD0_MSPREDIS BIT(8)
178 /* Memory Space 1 Burst Enable (LBRD1 only) */
179 #define PLX_LBRD1_MSBURSTEN BIT(8)
180 /* Expansion ROM Space Prefetch Disable (LBRD0 only) */
181 #define PLX_LBRD0_EROMPREDIS BIT(9)
182 /* Memory Space 1 Prefetch Disable (LBRD1 only) */
183 #define PLX_LBRD1_MSPREDIS BIT(9)
184 /* Read Prefetch Count Enable */
185 #define PLX_LBRD_RPFCOUNTEN BIT(10)
186 /* Prefetch Counter */
187 #define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf))
188 #define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11)
189 #define PLX_LBRD_PFCOUNT_SHIFT 11
190 /* Expansion ROM Space Local Bus Width (LBRD0 only) */
191 #define PLX_LBRD0_EROMWIDTH8 (BIT(16) * 0) /* 8 bits wide */
192 #define PLX_LBRD0_EROMWIDTH16 (BIT(16) * 1) /* 16 bits wide */
193 #define PLX_LBRD0_EROMWIDTH32 (BIT(16) * 2) /* 32 bits wide */
194 #define PLX_LBRD0_EROMWIDTH32A (BIT(16) * 3) /* 32 bits wide */
195 #define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16)
196 #define PLX_LBRD0_EROMWIDTH_SHIFT 16
197 /* Expansion ROM Space Internal Wait States (LBRD0 only) */
198 #define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf))
199 #define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18)
200 #define PLX_LBRD0_EROMIWS_SHIFT 18
201 /* Expansion ROM Space Ready Input Enable (LBDR0 only) */
202 #define PLX_LBRD0_EROMREADYIEN BIT(22)
203 /* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */
204 #define PLX_LBRD0_EROMBTERMIEN BIT(23)
205 /* Memory Space 0 Burst Enable (LBRD0 only) */
206 #define PLX_LBRD0_MSBURSTEN BIT(24)
207 /* Extra Long Load From Serial EEPROM (LBRD0 only) */
208 #define PLX_LBRD0_EELONGLOAD BIT(25)
209 /* Expansion ROM Space Burst Enable (LBRD0 only) */
210 #define PLX_LBRD0_EROMBURSTEN BIT(26)
211 /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
212 #define PLX_LBRD0_DSWMTRDY BIT(27)
213 /* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */
214 #define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF))
215 #define PLX_LBRD0_TRDELAY_MASK GENMASK(31, 28)
216 #define PLX_LBRD0_TRDELAY_SHIFT 28
218 /* Local Range Register for Direct Master to PCI */
219 #define PLX_REG_DMRR 0x001c
221 /* Local Bus Base Address Register for Direct Master to PCI Memory */
222 #define PLX_REG_DMLBAM 0x0020
224 /* Local Base Address Register for Direct Master to PCI IO/CFG */
225 #define PLX_REG_DMLBAI 0x0024
227 /* PCI Base Address (Remap) Register for Direct Master to PCI Memory */
228 #define PLX_REG_DMPBAM 0x0028
230 /* Direct Master Memory Access Enable */
231 #define PLX_DMPBAM_MEMACCEN BIT(0)
232 /* Direct Master I/O Access Enable */
233 #define PLX_DMPBAM_IOACCEN BIT(1)
234 /* LLOCK# Input Enable */
235 #define PLX_DMPBAM_LLOCKIEN BIT(2)
236 /* Direct Master Read Prefetch Size Control (bits 12, 3) */
237 #define PLX_DMPBAM_RPSIZECONT ((BIT(12) * 0) | (BIT(3) * 0))
238 #define PLX_DMPBAM_RPSIZE4 ((BIT(12) * 0) | (BIT(3) * 1))
239 #define PLX_DMPBAM_RPSIZE8 ((BIT(12) * 1) | (BIT(3) * 0))
240 #define PLX_DMPBAM_RPSIZE16 ((BIT(12) * 1) | (BIT(3) * 1))
241 #define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3))
242 /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
243 #define PLX_DMPBAM_RMIRDY BIT(4)
244 /* Programmable Almost Full Level (bits 10, 8:5) */
245 #define PLX_DMPBAM_PAFL(x) ((BIT(10) * !!((x) & 0x10)) | \
246 (BIT(5) * ((x) & 0xf)))
247 #define PLX_DMPBAM_TO_PAFL(v) ((((BIT(10) & (v)) >> 1) | \
248 (GENMASK(8, 5) & (v))) >> 5)
249 #define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5))
250 /* Write And Invalidate Mode */
251 #define PLX_DMPBAM_WIM BIT(9)
252 /* Direct Master Prefetch Limit */
253 #define PLX_DBPBAM_PFLIMIT BIT(11)
254 /* I/O Remap Select */
255 #define PLX_DMPBAM_IOREMAPSEL BIT(13)
256 /* Direct Master Write Delay */
257 #define PLX_DMPBAM_WDELAYNONE (BIT(14) * 0)
258 #define PLX_DMPBAM_WDELAY4 (BIT(14) * 1)
259 #define PLX_DMPBAM_WDELAY8 (BIT(14) * 2)
260 #define PLX_DMPBAM_WDELAY16 (BIT(14) * 3)
261 #define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14)
262 /* Remap of Local-to-PCI Space Into PCI Address Space */
263 #define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16)
265 /* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
266 #define PLX_REG_DMCFGA 0x002c
268 /* Congiguration Type */
269 #define PLX_DMCFGA_TYPE0 (BIT(0) * 0)
270 #define PLX_DMCFGA_TYPE1 (BIT(0) * 1)
271 #define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0)
272 /* Register Number */
273 #define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f))
274 #define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2)
275 #define PLX_DMCFGA_REGNUM_SHIFT 2
276 /* Function Number */
277 #define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7))
278 #define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8)
279 #define PLX_DMCFGA_FUNCNUM_SHIFT 8
281 #define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f))
282 #define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11)
283 #define PLX_DMCFGA_DEVNUM_SHIFT 11
285 #define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff))
286 #define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16)
287 #define PLX_DMCFGA_BUSNUM_SHIFT 16
288 /* Configuration Enable */
289 #define PLX_DMCFGA_CONFIGEN BIT(31)
292 * Mailbox Register N (N <= 7)
294 * Note that if the I2O feature is enabled (QSR[0] is set), Mailbox Register 0
295 * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced
296 * by the Outbound Queue Port. However, Mailbox Register 0 and 1 are always
297 * accessible at alternative offsets if the I2O feature is enabled.
299 #define PLX_REG_MBOX(n) (0x0040 + (n) * 4)
300 #define PLX_REG_MBOX0 PLX_REG_MBOX(0)
301 #define PLX_REG_MBOX1 PLX_REG_MBOX(1)
302 #define PLX_REG_MBOX2 PLX_REG_MBOX(2)
303 #define PLX_REG_MBOX3 PLX_REG_MBOX(3)
304 #define PLX_REG_MBOX4 PLX_REG_MBOX(4)
305 #define PLX_REG_MBOX5 PLX_REG_MBOX(5)
306 #define PLX_REG_MBOX6 PLX_REG_MBOX(6)
307 #define PLX_REG_MBOX7 PLX_REG_MBOX(7)
309 /* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */
310 #define PLX_REG_ALT_MBOX(n) ((n) < 2 ? 0x0078 + (n) * 4 : PLX_REG_MBOX(n))
311 #define PLX_REG_ALT_MBOX0 PLX_REG_ALT_MBOX(0)
312 #define PLX_REG_ALT_MBOX1 PLX_REG_ALT_MBOX(1)
314 /* PCI-to-Local Doorbell Register */
315 #define PLX_REG_P2LDBELL 0x0060
317 /* Local-to-PCI Doorbell Register */
318 #define PLX_REG_L2PDBELL 0x0064
320 /* Interrupt Control/Status Register */
321 #define PLX_REG_INTCSR 0x0068
323 /* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */
324 #define PLX_INTCSR_LSEABORTEN BIT(0)
325 /* Enable Local Bus LSERR# when PCI parity error occurs */
326 #define PLX_INTCSR_LSEPARITYEN BIT(1)
327 /* Generate PCI Bus SERR# when set to 1 */
328 #define PLX_INTCSR_GENSERR BIT(2)
329 /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
330 #define PLX_INTCSR_MBIEN BIT(3)
331 /* PCI Interrupt Enable */
332 #define PLX_INTCSR_PIEN BIT(8)
333 /* PCI Doorbell Interrupt Enable */
334 #define PLX_INTCSR_PDBIEN BIT(9)
335 /* PCI Abort Interrupt Enable */
336 #define PLX_INTCSR_PABORTIEN BIT(10)
337 /* PCI Local Interrupt Enable */
338 #define PLX_INTCSR_PLIEN BIT(11)
339 /* Retry Abort Enable (for diagnostic purposes only) */
340 #define PLX_INTCSR_RAEN BIT(12)
341 /* PCI Doorbell Interrupt Active (read-only) */
342 #define PLX_INTCSR_PDBIA BIT(13)
343 /* PCI Abort Interrupt Active (read-only) */
344 #define PLX_INTCSR_PABORTIA BIT(14)
345 /* Local Interrupt (LINTi#) Active (read-only) */
346 #define PLX_INTCSR_PLIA BIT(15)
347 /* Local Interrupt Output (LINTo#) Enable */
348 #define PLX_INTCSR_LIOEN BIT(16)
349 /* Local Doorbell Interrupt Enable */
350 #define PLX_INTCSR_LDBIEN BIT(17)
351 /* DMA Channel 0 Interrupt Enable */
352 #define PLX_INTCSR_DMA0IEN BIT(18)
353 /* DMA Channel 1 Interrupt Enable */
354 #define PLX_INTCSR_DMA1IEN BIT(19)
355 /* DMA Channel N Interrupt Enable (N <= 1) */
356 #define PLX_INTCSR_DMAIEN(n) ((n) ? PLX_INTCSR_DMA1IEN : PLX_INTCSR_DMA0IEN)
357 /* Local Doorbell Interrupt Active (read-only) */
358 #define PLX_INTCSR_LDBIA BIT(20)
359 /* DMA Channel 0 Interrupt Active (read-only) */
360 #define PLX_INTCSR_DMA0IA BIT(21)
361 /* DMA Channel 1 Interrupt Active (read-only) */
362 #define PLX_INTCSR_DMA1IA BIT(22)
363 /* DMA Channel N Interrupt Active (N <= 1) (read-only) */
364 #define PLX_INTCSR_DMAIA(n) ((n) ? PLX_INTCSR_DMA1IA : PLX_INTCSR_DMA0IA)
365 /* BIST Interrupt Active (read-only) */
366 #define PLX_INTCSR_BISTIA BIT(23)
367 /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
368 #define PLX_INTCSR_ABNOTDM BIT(24)
369 /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
370 #define PLX_INTCSR_ABNOTDMA0 BIT(25)
371 /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
372 #define PLX_INTCSR_ABNOTDMA1 BIT(26)
373 /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
374 #define PLX_INTCSR_ABNOTDMA(n) ((n) ? PLX_INTCSR_ABNOTDMA1 \
375 : PLX_INTCSR_ABNOTDMA0)
376 /* Target Abort Not Generated After 256 Master Retries (read-only) */
377 #define PLX_INTCSR_ABNOTRETRY BIT(27)
378 /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
379 #define PLX_INTCSR_MB0IA BIT(28)
380 /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
381 #define PLX_INTCSR_MB1IA BIT(29)
382 /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
383 #define PLX_INTCSR_MB2IA BIT(30)
384 /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
385 #define PLX_INTCSR_MB3IA BIT(31)
386 /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
387 #define PLX_INTCSR_MBIA(n) BIT(28 + (n))
390 * Serial EEPROM Control, PCI Command Codes, User I/O Control,
391 * Init Control Register
393 #define PLX_REG_CNTRL 0x006c
395 /* PCI Read Command Code For DMA */
396 #define PLX_CNTRL_CCRDMA(x) (BIT(0) * ((x) & 0xf))
397 #define PLX_CNTRL_CCRDMA_MASK GENMASK(3, 0)
398 #define PLX_CNTRL_CCRDMA_SHIFT 0
399 #define PLX_CNTRL_CCRDMA_NORMAL PLX_CNTRL_CCRDMA(14) /* value after reset */
400 /* PCI Write Command Code For DMA 0 */
401 #define PLX_CNTRL_CCWDMA(x) (BIT(4) * ((x) & 0xf))
402 #define PLX_CNTRL_CCWDMA_MASK GENMASK(7, 4)
403 #define PLX_CNTRL_CCWDMA_SHIFT 4
404 #define PLX_CNTRL_CCWDMA_NORMAL PLX_CNTRL_CCWDMA(7) /* value after reset */
405 /* PCI Memory Read Command Code For Direct Master */
406 #define PLX_CNTRL_CCRDM(x) (BIT(8) * ((x) & 0xf))
407 #define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8)
408 #define PLX_CNTRL_CCRDM_SHIFT 8
409 #define PLX_CNTRL_CCRDM_NORMAL PLX_CNTRL_CCRDM(6) /* value after reset */
410 /* PCI Memory Write Command Code For Direct Master */
411 #define PLX_CNTRL_CCWDM(x) (BIT(12) * ((x) & 0xf))
412 #define PLX_CNTRL_CCWDM_MASK GENMASK(15, 12)
413 #define PLX_CNTRL_CCWDM_SHIFT 12
414 #define PLX_CNTRL_CCWDM_NORMAL PLX_CNTRL_CCWDM(7) /* value after reset */
415 /* General Purpose Output (USERO) */
416 #define PLX_CNTRL_USERO BIT(16)
417 /* General Purpose Input (USERI) (read-only) */
418 #define PLX_CNTRL_USERI BIT(17)
419 /* Serial EEPROM Clock Output (EESK) */
420 #define PLX_CNTRL_EESK BIT(24)
421 /* Serial EEPROM Chip Select Output (EECS) */
422 #define PLX_CNTRL_EECS BIT(25)
423 /* Serial EEPROM Data Write Bit (EEDI (sic)) */
424 #define PLX_CNTRL_EEWB BIT(26)
425 /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
426 #define PLX_CNTRL_EERB BIT(27)
427 /* Serial EEPROM Present (read-only) */
428 #define PLX_CNTRL_EEPRESENT BIT(28)
429 /* Reload Configuration Registers from EEPROM */
430 #define PLX_CNTRL_EERELOAD BIT(29)
431 /* PCI Adapter Software Reset (asserts LRESETo#) */
432 #define PLX_CNTRL_RESET BIT(30)
433 /* Local Init Status (read-only) */
434 #define PLX_CNTRL_INITDONE BIT(31)
436 * Combined command code stuff for convenience.
438 #define PLX_CNTRL_CC_MASK \
439 (PLX_CNTRL_CCRDMA_MASK | PLX_CNTRL_CCWDMA_MASK | \
440 PLX_CNTRL_CCRDM_MASK | PLX_CNTRL_CCWDM_MASK)
441 #define PLX_CNTRL_CC_NORMAL \
442 (PLX_CNTRL_CCRDMA_NORMAL | PLX_CNTRL_CCWDMA_NORMAL | \
443 PLX_CNTRL_CCRDM_NORMAL | PLX_CNTRL_CCWDM_NORMAL) /* val after reset */
445 /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
446 #define PLX_REG_PCIHIDR 0x0070
448 /* Hard-coded ID for PLX PCI 9080 */
449 #define PLX_PCIHIDR_9080 0x908010b5
451 /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
452 #define PLX_REG_PCIHREV 0x0074
454 /* DMA Channel N Mode Register (N <= 1) */
455 #define PLX_REG_DMAMODE(n) ((n) ? PLX_REG_DMAMODE1 : PLX_REG_DMAMODE0)
456 #define PLX_REG_DMAMODE0 0x0080
457 #define PLX_REG_DMAMODE1 0x0094
459 /* Local Bus Width */
460 #define PLX_DMAMODE_WIDTH8 (BIT(0) * 0) /* 8 bits wide */
461 #define PLX_DMAMODE_WIDTH16 (BIT(0) * 1) /* 16 bits wide */
462 #define PLX_DMAMODE_WIDTH32 (BIT(0) * 2) /* 32 bits wide */
463 #define PLX_DMAMODE_WIDTH32A (BIT(0) * 3) /* 32 bits wide */
464 #define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0)
465 #define PLX_DMAMODE_WIDTH_SHIFT 0
466 /* Internal Wait States */
467 #define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf))
468 #define PLX_DMAMODE_IWS_MASK GENMASK(5, 2)
469 #define PLX_DMAMODE_SHIFT 2
470 /* Ready Input Enable */
471 #define PLX_DMAMODE_READYIEN BIT(6)
472 /* BTERM# Input Enable */
473 #define PLX_DMAMODE_BTERMIEN BIT(7)
474 /* Local Burst Enable */
475 #define PLX_DMAMODE_BURSTEN BIT(8)
476 /* Chaining Enable */
477 #define PLX_DMAMODE_CHAINEN BIT(9)
478 /* Done Interrupt Enable */
479 #define PLX_DMAMODE_DONEIEN BIT(10)
480 /* Hold Local Address Constant */
481 #define PLX_DMAMODE_LACONST BIT(11)
483 #define PLX_DMAMODE_DEMAND BIT(12)
484 /* Write And Invalidate Mode */
485 #define PLX_DMAMODE_WINVALIDATE BIT(13)
486 /* DMA EOT Enable - enables EOT0# or EOT1# input pin */
487 #define PLX_DMAMODE_EOTEN BIT(14)
488 /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
489 #define PLX_DMAMODE_STOP BIT(15)
490 /* DMA Clear Count Mode - count in descriptor cleared on completion */
491 #define PLX_DMAMODE_CLRCOUNT BIT(16)
492 /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
493 #define PLX_DMAMODE_INTRPCI BIT(17)
495 /* DMA Channel N PCI Address Register (N <= 1) */
496 #define PLX_REG_DMAPADR(n) ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0)
497 #define PLX_REG_DMAPADR0 0x0084
498 #define PLX_REG_DMAPADR1 0x0098
500 /* DMA Channel N Local Address Register (N <= 1) */
501 #define PLX_REG_DMALADR(n) ((n) ? PLX_REG_DMALADR1 : PLX_REG_DMALADR0)
502 #define PLX_REG_DMALADR0 0x0088
503 #define PLX_REG_DMALADR1 0x009c
505 /* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */
506 #define PLX_REG_DMASIZ(n) ((n) ? PLX_REG_DMASIZ1 : PLX_REG_DMASIZ0)
507 #define PLX_REG_DMASIZ0 0x008c
508 #define PLX_REG_DMASIZ1 0x00a0
510 /* DMA Channel N Descriptor Pointer Register (N <= 1) */
511 #define PLX_REG_DMADPR(n) ((n) ? PLX_REG_DMADPR1 : PLX_REG_DMADPR0)
512 #define PLX_REG_DMADPR0 0x0090
513 #define PLX_REG_DMADPR1 0x00a4
515 /* Descriptor Located In PCI Address Space (not local address space) */
516 #define PLX_DMADPR_DESCPCI BIT(0)
518 #define PLX_DMADPR_CHAINEND BIT(1)
519 /* Interrupt After Terminal Count */
520 #define PLX_DMADPR_TCINTR BIT(2)
521 /* Direction Of Transfer Local Bus To PCI (not PCI to local) */
522 #define PLX_DMADPR_XFERL2P BIT(3)
523 /* Next Descriptor Address Bits 31:4 (16 byte boundary) */
524 #define PLX_DMADPR_NEXT_MASK GENMASK(31, 4)
526 /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
527 #define PLX_REG_DMACSR(n) ((n) ? PLX_REG_DMACSR1 : PLX_REG_DMACSR0)
528 #define PLX_REG_DMACSR0 0x00a8
529 #define PLX_REG_DMACSR1 0x00a9
532 #define PLX_DMACSR_ENABLE BIT(0)
533 /* Channel Start - write 1 to start transfer (write-only) */
534 #define PLX_DMACSR_START BIT(1)
535 /* Channel Abort - write 1 to abort transfer (write-only) */
536 #define PLX_DMACSR_ABORT BIT(2)
537 /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
538 #define PLX_DMACSR_CLEARINTR BIT(3)
539 /* Channel Done - transfer complete/inactive (read-only) */
540 #define PLX_DMACSR_DONE BIT(4)
542 /* DMA Threshold Register */
543 #define PLX_REG_DMATHR 0x00b0
546 * DMA Threshold constraints:
547 * (C0PLAF + 1) + (C0PLAE + 1) <= 32
548 * (C0LPAF + 1) + (C0LPAE + 1) <= 32
549 * (C1PLAF + 1) + (C1PLAE + 1) <= 16
550 * (C1LPAF + 1) + (C1LPAE + 1) <= 16
553 /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
554 #define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf))
555 #define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0)
556 #define PLX_DMATHR_C0PLAF_SHIFT 0
557 /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
558 #define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf))
559 #define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4)
560 #define PLX_DMATHR_C0LPAE_SHIFT 4
561 /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
562 #define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf))
563 #define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8)
564 #define PLX_DMATHR_C0LPAF_SHIFT 8
565 /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
566 #define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf))
567 #define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12)
568 #define PLX_DMATHR_C0PLAE_SHIFT 12
569 /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
570 #define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf))
571 #define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16)
572 #define PLX_DMATHR_C1PLAF_SHIFT 16
573 /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
574 #define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf))
575 #define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20)
576 #define PLX_DMATHR_C1LPAE_SHIFT 20
577 /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
578 #define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf))
579 #define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24)
580 #define PLX_DMATHR_C1LPAF_SHIFT 24
581 /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
582 #define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf))
583 #define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28)
584 #define PLX_DMATHR_C1PLAE_SHIFT 28
587 * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR,
588 * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted.
589 * They are used by the I2O feature. (IQP and OQP occupy the usual offsets of
590 * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and
591 * MBOX1 are accessible via alternative offsets.
594 /* Queue Status/Control Register */
595 #define PLX_REG_QSR 0x00e8
597 /* Value of QSR after reset - disables I2O feature completely. */
598 #define PLX_QSR_VALUE_AFTER_RESET 0x00000050
601 * Accesses near the end of memory can cause the PLX chip
602 * to pre-fetch data off of end-of-ram. Limit the size of
603 * memory so host-side accesses cannot occur.
606 #define PLX_PREFETCH 32
609 * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
610 * @iobase: Remapped base address of configuration registers.
611 * @channel: DMA channel number (0 or 1).
613 * Aborts the DMA transfer on the channel, which must have been enabled
614 * and started beforehand.
618 * -%ETIMEDOUT if timed out waiting for abort to complete.
620 static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
622 void __iomem *dma_cs_addr;
624 const int timeout = 10000;
627 dma_cs_addr = iobase + PLX_REG_DMACSR(channel);
629 /* abort dma transfer if necessary */
630 dma_status = readb(dma_cs_addr);
631 if ((dma_status & PLX_DMACSR_ENABLE) == 0)
634 /* wait to make sure done bit is zero */
635 for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) {
637 dma_status = readb(dma_cs_addr);
642 /* disable and abort channel */
643 writeb(PLX_DMACSR_ABORT, dma_cs_addr);
644 /* wait for dma done bit */
645 dma_status = readb(dma_cs_addr);
646 for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) {
648 dma_status = readb(dma_cs_addr);
656 #endif /* __COMEDI_PLX9080_H */