drivers/staging/comedi/drivers/ni_tio_internal.h

   1 /*
   2     drivers/ni_tio_internal.h
   3     Header file for NI general purpose counter support code (ni_tio.c and
   4     ni_tiocmd.c)
   5
   6     COMEDI - Linux Control and Measurement Device Interface
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18
  19 #ifndef _COMEDI_NI_TIO_INTERNAL_H
  20 #define _COMEDI_NI_TIO_INTERNAL_H
  21
  22 #include "ni_tio.h"
  23
  24 #define NITIO_AUTO_INC_REG(x)           (NITIO_G0_AUTO_INC + (x))
  25 #define NITIO_CMD_REG(x)                (NITIO_G0_CMD + (x))
  26 #define NITIO_SW_SAVE_REG(x)            (NITIO_G0_SW_SAVE + (x))
  27 #define NITIO_MODE_REG(x)               (NITIO_G0_MODE + (x))
  28 #define NITIO_LOADA_REG(x)              (NITIO_G0_LOADA + (x))
  29 #define NITIO_LOADB_REG(x)              (NITIO_G0_LOADB + (x))
  30 #define NITIO_INPUT_SEL_REG(x)          (NITIO_G0_INPUT_SEL + (x))
  31 #define NITIO_CNT_MODE_REG(x)           (NITIO_G0_CNT_MODE + (x))
  32 #define NITIO_GATE2_REG(x)              (NITIO_G0_GATE2 + (x))
  33 #define NITIO_SHARED_STATUS_REG(x)      (NITIO_G01_STATUS + ((x) / 2))
  34 #define NITIO_RESET_REG(x)              (NITIO_G01_RESET + ((x) / 2))
  35 #define NITIO_STATUS1_REG(x)            (NITIO_G01_STATUS1 + ((x) / 2))
  36 #define NITIO_STATUS2_REG(x)            (NITIO_G01_STATUS2 + ((x) / 2))
  37 #define NITIO_DMA_CFG_REG(x)            (NITIO_G0_DMA_CFG + (x))
  38 #define NITIO_DMA_STATUS_REG(x)         (NITIO_G0_DMA_STATUS + (x))
  39 #define NITIO_ABZ_REG(x)                (NITIO_G0_ABZ + (x))
  40 #define NITIO_INT_ACK_REG(x)            (NITIO_G0_INT_ACK + (x))
  41 #define NITIO_STATUS_REG(x)             (NITIO_G0_STATUS + (x))
  42
  43 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(unsigned idx)
  44 {
  45         switch (idx) {
  46         case 0:
  47                 return NITIO_G0_INT_ENA;
  48         case 1:
  49                 return NITIO_G1_INT_ENA;
  50         case 2:
  51                 return NITIO_G2_INT_ENA;
  52         case 3:
  53                 return NITIO_G3_INT_ENA;
  54         }
  55         return 0;
  56 }
  57
  58 enum Gi_Auto_Increment_Reg_Bits {
  59         Gi_Auto_Increment_Mask = 0xff
  60 };
  61
  62 #define Gi_Up_Down_Shift 5
  63 enum Gi_Command_Reg_Bits {
  64         Gi_Arm_Bit = 0x1,
  65         Gi_Save_Trace_Bit = 0x2,
  66         Gi_Load_Bit = 0x4,
  67         Gi_Disarm_Bit = 0x10,
  68         Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
  69         Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
  70         Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
  71         Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
  72         Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
  73         Gi_Write_Switch_Bit = 0x80,
  74         Gi_Synchronize_Gate_Bit = 0x100,
  75         Gi_Little_Big_Endian_Bit = 0x200,
  76         Gi_Bank_Switch_Start_Bit = 0x400,
  77         Gi_Bank_Switch_Mode_Bit = 0x800,
  78         Gi_Bank_Switch_Enable_Bit = 0x1000,
  79         Gi_Arm_Copy_Bit = 0x2000,
  80         Gi_Save_Trace_Copy_Bit = 0x4000,
  81         Gi_Disarm_Copy_Bit = 0x8000
  82 };
  83
  84 #define Gi_Index_Phase_Bitshift 5
  85 #define Gi_HW_Arm_Select_Shift 8
  86 enum Gi_Counting_Mode_Reg_Bits {
  87         Gi_Counting_Mode_Mask = 0x7,
  88         Gi_Counting_Mode_Normal_Bits = 0x0,
  89         Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
  90         Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
  91         Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
  92         Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
  93         Gi_Counting_Mode_Sync_Source_Bits = 0x6,
  94         Gi_Index_Mode_Bit = 0x10,
  95         Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
  96         Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
  97         Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
  98         Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
  99         Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
 100         /* from m-series example code, not documented in 660x register level
 101          * manual */
 102         Gi_HW_Arm_Enable_Bit = 0x80,
 103         /* from m-series example code, not documented in 660x register level
 104          * manual */
 105         Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
 106         Gi_660x_Prescale_X8_Bit = 0x1000,
 107         Gi_M_Series_Prescale_X8_Bit = 0x2000,
 108         Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
 109         /* must be set for clocks over 40MHz, which includes synchronous
 110          * counting and quadrature modes */
 111         Gi_660x_Alternate_Sync_Bit = 0x2000,
 112         Gi_M_Series_Alternate_Sync_Bit = 0x4000,
 113         /* from m-series example code, not documented in 660x register level
 114          * manual */
 115         Gi_660x_Prescale_X2_Bit = 0x4000,
 116         Gi_M_Series_Prescale_X2_Bit = 0x8000,
 117 };
 118
 119 #define Gi_Source_Select_Shift 2
 120 #define Gi_Gate_Select_Shift 7
 121 enum Gi_Input_Select_Bits {
 122         Gi_Read_Acknowledges_Irq = 0x1, /*  not present on 660x */
 123         Gi_Write_Acknowledges_Irq = 0x2,        /*  not present on 660x */
 124         Gi_Source_Select_Mask = 0x7c,
 125         Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
 126         Gi_Gate_Select_Load_Source_Bit = 0x1000,
 127         Gi_Or_Gate_Bit = 0x2000,
 128         Gi_Output_Polarity_Bit = 0x4000,        /* set to invert */
 129         Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
 130 };
 131
 132 enum Gi_Mode_Bits {
 133         Gi_Gating_Mode_Mask = 0x3,
 134         Gi_Gating_Disabled_Bits = 0x0,
 135         Gi_Level_Gating_Bits = 0x1,
 136         Gi_Rising_Edge_Gating_Bits = 0x2,
 137         Gi_Falling_Edge_Gating_Bits = 0x3,
 138         Gi_Gate_On_Both_Edges_Bit = 0x4,        /* used in conjunction with
 139                                                  * rising edge gating mode */
 140         Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
 141         Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
 142         Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
 143         Gi_Edge_Gate_Starts_Bits = 0x10,
 144         Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
 145         Gi_Stop_Mode_Mask = 0x60,
 146         Gi_Stop_on_Gate_Bits = 0x00,
 147         Gi_Stop_on_Gate_or_TC_Bits = 0x20,
 148         Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
 149         Gi_Load_Source_Select_Bit = 0x80,
 150         Gi_Output_Mode_Mask = 0x300,
 151         Gi_Output_TC_Pulse_Bits = 0x100,
 152         Gi_Output_TC_Toggle_Bits = 0x200,
 153         Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
 154         Gi_Counting_Once_Mask = 0xc00,
 155         Gi_No_Hardware_Disarm_Bits = 0x000,
 156         Gi_Disarm_at_TC_Bits = 0x400,
 157         Gi_Disarm_at_Gate_Bits = 0x800,
 158         Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
 159         Gi_Loading_On_TC_Bit = 0x1000,
 160         Gi_Gate_Polarity_Bit = 0x2000,
 161         Gi_Loading_On_Gate_Bit = 0x4000,
 162         Gi_Reload_Source_Switching_Bit = 0x8000
 163 };
 164
 165 #define Gi_Second_Gate_Select_Shift 7
 166 /*FIXME: m-series has a second gate subselect bit */
 167 /*FIXME: m-series second gate sources are undocumented (by NI)*/
 168 enum Gi_Second_Gate_Bits {
 169         Gi_Second_Gate_Mode_Bit = 0x1,
 170         Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
 171         Gi_Second_Gate_Polarity_Bit = 0x2000,
 172         Gi_Second_Gate_Subselect_Bit = 0x4000,  /* m-series only */
 173         Gi_Source_Subselect_Bit = 0x8000        /* m-series only */
 174 };
 175 static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
 176 {
 177         return (second_gate_select << Gi_Second_Gate_Select_Shift) &
 178             Gi_Second_Gate_Select_Mask;
 179 }
 180
 181 enum Gxx_Status_Bits {
 182         G0_Save_Bit = 0x1,
 183         G1_Save_Bit = 0x2,
 184         G0_Counting_Bit = 0x4,
 185         G1_Counting_Bit = 0x8,
 186         G0_Next_Load_Source_Bit = 0x10,
 187         G1_Next_Load_Source_Bit = 0x20,
 188         G0_Stale_Data_Bit = 0x40,
 189         G1_Stale_Data_Bit = 0x80,
 190         G0_Armed_Bit = 0x100,
 191         G1_Armed_Bit = 0x200,
 192         G0_No_Load_Between_Gates_Bit = 0x400,
 193         G1_No_Load_Between_Gates_Bit = 0x800,
 194         G0_TC_Error_Bit = 0x1000,
 195         G1_TC_Error_Bit = 0x2000,
 196         G0_Gate_Error_Bit = 0x4000,
 197         G1_Gate_Error_Bit = 0x8000
 198 };
 199 static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
 200 {
 201         if (counter_index % 2)
 202                 return G1_Counting_Bit;
 203         return G0_Counting_Bit;
 204 }
 205
 206 static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
 207 {
 208         if (counter_index % 2)
 209                 return G1_Armed_Bit;
 210         return G0_Armed_Bit;
 211 }
 212
 213 static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
 214                                                            counter_index)
 215 {
 216         if (counter_index % 2)
 217                 return G1_Next_Load_Source_Bit;
 218         return G0_Next_Load_Source_Bit;
 219 }
 220
 221 static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
 222 {
 223         if (counter_index % 2)
 224                 return G1_Stale_Data_Bit;
 225         return G0_Stale_Data_Bit;
 226 }
 227
 228 static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
 229 {
 230         if (counter_index % 2)
 231                 return G1_TC_Error_Bit;
 232         return G0_TC_Error_Bit;
 233 }
 234
 235 static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
 236 {
 237         if (counter_index % 2)
 238                 return G1_Gate_Error_Bit;
 239         return G0_Gate_Error_Bit;
 240 }
 241
 242 /* joint reset register bits */
 243 static inline unsigned Gi_Reset_Bit(unsigned counter_index)
 244 {
 245         return 0x1 << (2 + (counter_index % 2));
 246 }
 247
 248 enum Gxx_Joint_Status2_Bits {
 249         G0_Output_Bit = 0x1,
 250         G1_Output_Bit = 0x2,
 251         G0_HW_Save_Bit = 0x1000,
 252         G1_HW_Save_Bit = 0x2000,
 253         G0_Permanent_Stale_Bit = 0x4000,
 254         G1_Permanent_Stale_Bit = 0x8000
 255 };
 256 static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
 257                                                                  counter_index)
 258 {
 259         if (counter_index % 2)
 260                 return G1_Permanent_Stale_Bit;
 261         return G0_Permanent_Stale_Bit;
 262 }
 263
 264 enum Gi_DMA_Config_Reg_Bits {
 265         Gi_DMA_Enable_Bit = 0x1,
 266         Gi_DMA_Write_Bit = 0x2,
 267         Gi_DMA_Int_Bit = 0x4
 268 };
 269
 270 enum Gi_DMA_Status_Reg_Bits {
 271         Gi_DMA_Readbank_Bit = 0x2000,
 272         Gi_DRQ_Error_Bit = 0x4000,
 273         Gi_DRQ_Status_Bit = 0x8000
 274 };
 275
 276 enum G02_Interrupt_Acknowledge_Bits {
 277         G0_Gate_Error_Confirm_Bit = 0x20,
 278         G0_TC_Error_Confirm_Bit = 0x40
 279 };
 280 enum G13_Interrupt_Acknowledge_Bits {
 281         G1_Gate_Error_Confirm_Bit = 0x2,
 282         G1_TC_Error_Confirm_Bit = 0x4
 283 };
 284 static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
 285 {
 286         if (counter_index % 2)
 287                 return G1_Gate_Error_Confirm_Bit;
 288         return G0_Gate_Error_Confirm_Bit;
 289 }
 290
 291 static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
 292 {
 293         if (counter_index % 2)
 294                 return G1_TC_Error_Confirm_Bit;
 295         return G0_TC_Error_Confirm_Bit;
 296 }
 297
 298 /* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
 299 enum Gxx_Interrupt_Acknowledge_Bits {
 300         Gi_TC_Interrupt_Ack_Bit = 0x4000,
 301         Gi_Gate_Interrupt_Ack_Bit = 0x8000
 302 };
 303
 304 enum Gi_Status_Bits {
 305         Gi_Gate_Interrupt_Bit = 0x4,
 306         Gi_TC_Bit = 0x8,
 307         Gi_Interrupt_Bit = 0x8000
 308 };
 309
 310 enum G02_Interrupt_Enable_Bits {
 311         G0_TC_Interrupt_Enable_Bit = 0x40,
 312         G0_Gate_Interrupt_Enable_Bit = 0x100
 313 };
 314 enum G13_Interrupt_Enable_Bits {
 315         G1_TC_Interrupt_Enable_Bit = 0x200,
 316         G1_Gate_Interrupt_Enable_Bit = 0x400
 317 };
 318 static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
 319 {
 320         unsigned bit;
 321
 322         if (counter_index % 2)
 323                 bit = G1_Gate_Interrupt_Enable_Bit;
 324         else
 325                 bit = G0_Gate_Interrupt_Enable_Bit;
 326         return bit;
 327 }
 328
 329 static inline void write_register(struct ni_gpct *counter, unsigned bits,
 330                                   enum ni_gpct_register reg)
 331 {
 332         BUG_ON(reg >= NITIO_NUM_REGS);
 333         counter->counter_dev->write_register(counter, bits, reg);
 334 }
 335
 336 static inline unsigned read_register(struct ni_gpct *counter,
 337                                      enum ni_gpct_register reg)
 338 {
 339         BUG_ON(reg >= NITIO_NUM_REGS);
 340         return counter->counter_dev->read_register(counter, reg);
 341 }
 342
 343 static inline int ni_tio_counting_mode_registers_present(const struct
 344                                                          ni_gpct_device
 345                                                          *counter_dev)
 346 {
 347         switch (counter_dev->variant) {
 348         case ni_gpct_variant_e_series:
 349                 return 0;
 350                 break;
 351         case ni_gpct_variant_m_series:
 352         case ni_gpct_variant_660x:
 353                 return 1;
 354                 break;
 355         default:
 356                 BUG();
 357                 break;
 358         }
 359         return 0;
 360 }
 361
 362 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
 363                                              enum ni_gpct_register
 364                                              register_index, unsigned bit_mask,
 365                                              unsigned bit_values,
 366                                              unsigned transient_bit_values)
 367 {
 368         struct ni_gpct_device *counter_dev = counter->counter_dev;
 369         unsigned long flags;
 370
 371         BUG_ON(register_index >= NITIO_NUM_REGS);
 372         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 373         counter_dev->regs[register_index] &= ~bit_mask;
 374         counter_dev->regs[register_index] |= (bit_values & bit_mask);
 375         write_register(counter,
 376                        counter_dev->regs[register_index] | transient_bit_values,
 377                        register_index);
 378         mmiowb();
 379         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 380 }
 381
 382 /* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
 383  * twiddled in interrupt context, or whose software copy may be read in
 384  * interrupt context.
 385  */
 386 static inline void ni_tio_set_bits(struct ni_gpct *counter,
 387                                    enum ni_gpct_register register_index,
 388                                    unsigned bit_mask, unsigned bit_values)
 389 {
 390         ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
 391                                   0x0);
 392 }
 393
 394 /* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
 395 whose bits might be modified in interrupt context, or whose software copy
 396 might need to be read in interrupt context.
 397 */
 398 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
 399                                             enum ni_gpct_register
 400                                             register_index)
 401 {
 402         struct ni_gpct_device *counter_dev = counter->counter_dev;
 403         unsigned long flags;
 404         unsigned value;
 405
 406         BUG_ON(register_index >= NITIO_NUM_REGS);
 407         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 408         value = counter_dev->regs[register_index];
 409         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 410         return value;
 411 }
 412
 413 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
 414 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
 415                         unsigned int gate_source);
 416
 417 #endif /* _COMEDI_NI_TIO_INTERNAL_H */