drivers/staging/comedi/drivers/ni_tio_internal.h

   1 /*
   2     drivers/ni_tio_internal.h
   3     Header file for NI general purpose counter support code (ni_tio.c and
   4     ni_tiocmd.c)
   5
   6     COMEDI - Linux Control and Measurement Device Interface
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18
  19 #ifndef _COMEDI_NI_TIO_INTERNAL_H
  20 #define _COMEDI_NI_TIO_INTERNAL_H
  21
  22 #include "ni_tio.h"
  23
  24 #define NITIO_AUTO_INC_REG(x)           (NITIO_G0_AUTO_INC + (x))
  25 #define NITIO_CMD_REG(x)                (NITIO_G0_CMD + (x))
  26 #define NITIO_SW_SAVE_REG(x)            (NITIO_G0_SW_SAVE + (x))
  27 #define NITIO_MODE_REG(x)               (NITIO_G0_MODE + (x))
  28 #define NITIO_LOADA_REG(x)              (NITIO_G0_LOADA + (x))
  29 #define NITIO_LOADB_REG(x)              (NITIO_G0_LOADB + (x))
  30 #define NITIO_INPUT_SEL_REG(x)          (NITIO_G0_INPUT_SEL + (x))
  31 #define NITIO_CNT_MODE_REG(x)           (NITIO_G0_CNT_MODE + (x))
  32 #define NITIO_GATE2_REG(x)              (NITIO_G0_GATE2 + (x))
  33 #define NITIO_SHARED_STATUS_REG(x)      (NITIO_G01_STATUS + ((x) / 2))
  34 #define NITIO_RESET_REG(x)              (NITIO_G01_RESET + ((x) / 2))
  35 #define NITIO_STATUS1_REG(x)            (NITIO_G01_STATUS1 + ((x) / 2))
  36 #define NITIO_STATUS2_REG(x)            (NITIO_G01_STATUS2 + ((x) / 2))
  37 #define NITIO_DMA_CFG_REG(x)            (NITIO_G0_DMA_CFG + (x))
  38 #define NITIO_DMA_STATUS_REG(x)         (NITIO_G0_DMA_STATUS + (x))
  39 #define NITIO_ABZ_REG(x)                (NITIO_G0_ABZ + (x))
  40 #define NITIO_INT_ACK_REG(x)            (NITIO_G0_INT_ACK + (x))
  41 #define NITIO_STATUS_REG(x)             (NITIO_G0_STATUS + (x))
  42 #define NITIO_INT_ENA_REG(x)            (NITIO_G0_INT_ENA + (x))
  43
  44 enum Gi_Auto_Increment_Reg_Bits {
  45         Gi_Auto_Increment_Mask = 0xff
  46 };
  47
  48 #define Gi_Up_Down_Shift 5
  49 enum Gi_Command_Reg_Bits {
  50         Gi_Arm_Bit = 0x1,
  51         Gi_Save_Trace_Bit = 0x2,
  52         Gi_Load_Bit = 0x4,
  53         Gi_Disarm_Bit = 0x10,
  54         Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
  55         Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
  56         Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
  57         Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
  58         Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
  59         Gi_Write_Switch_Bit = 0x80,
  60         Gi_Synchronize_Gate_Bit = 0x100,
  61         Gi_Little_Big_Endian_Bit = 0x200,
  62         Gi_Bank_Switch_Start_Bit = 0x400,
  63         Gi_Bank_Switch_Mode_Bit = 0x800,
  64         Gi_Bank_Switch_Enable_Bit = 0x1000,
  65         Gi_Arm_Copy_Bit = 0x2000,
  66         Gi_Save_Trace_Copy_Bit = 0x4000,
  67         Gi_Disarm_Copy_Bit = 0x8000
  68 };
  69
  70 #define Gi_Index_Phase_Bitshift 5
  71 #define Gi_HW_Arm_Select_Shift 8
  72 enum Gi_Counting_Mode_Reg_Bits {
  73         Gi_Counting_Mode_Mask = 0x7,
  74         Gi_Counting_Mode_Normal_Bits = 0x0,
  75         Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
  76         Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
  77         Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
  78         Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
  79         Gi_Counting_Mode_Sync_Source_Bits = 0x6,
  80         Gi_Index_Mode_Bit = 0x10,
  81         Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
  82         Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
  83         Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
  84         Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
  85         Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
  86         /* from m-series example code, not documented in 660x register level
  87          * manual */
  88         Gi_HW_Arm_Enable_Bit = 0x80,
  89         /* from m-series example code, not documented in 660x register level
  90          * manual */
  91         Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
  92         Gi_660x_Prescale_X8_Bit = 0x1000,
  93         Gi_M_Series_Prescale_X8_Bit = 0x2000,
  94         Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
  95         /* must be set for clocks over 40MHz, which includes synchronous
  96          * counting and quadrature modes */
  97         Gi_660x_Alternate_Sync_Bit = 0x2000,
  98         Gi_M_Series_Alternate_Sync_Bit = 0x4000,
  99         /* from m-series example code, not documented in 660x register level
 100          * manual */
 101         Gi_660x_Prescale_X2_Bit = 0x4000,
 102         Gi_M_Series_Prescale_X2_Bit = 0x8000,
 103 };
 104
 105 #define Gi_Source_Select_Shift 2
 106 #define Gi_Gate_Select_Shift 7
 107 enum Gi_Input_Select_Bits {
 108         Gi_Read_Acknowledges_Irq = 0x1, /*  not present on 660x */
 109         Gi_Write_Acknowledges_Irq = 0x2,        /*  not present on 660x */
 110         Gi_Source_Select_Mask = 0x7c,
 111         Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
 112         Gi_Gate_Select_Load_Source_Bit = 0x1000,
 113         Gi_Or_Gate_Bit = 0x2000,
 114         Gi_Output_Polarity_Bit = 0x4000,        /* set to invert */
 115         Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
 116 };
 117
 118 enum Gi_Mode_Bits {
 119         Gi_Gating_Mode_Mask = 0x3,
 120         Gi_Gating_Disabled_Bits = 0x0,
 121         Gi_Level_Gating_Bits = 0x1,
 122         Gi_Rising_Edge_Gating_Bits = 0x2,
 123         Gi_Falling_Edge_Gating_Bits = 0x3,
 124         Gi_Gate_On_Both_Edges_Bit = 0x4,        /* used in conjunction with
 125                                                  * rising edge gating mode */
 126         Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
 127         Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
 128         Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
 129         Gi_Edge_Gate_Starts_Bits = 0x10,
 130         Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
 131         Gi_Stop_Mode_Mask = 0x60,
 132         Gi_Stop_on_Gate_Bits = 0x00,
 133         Gi_Stop_on_Gate_or_TC_Bits = 0x20,
 134         Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
 135         Gi_Load_Source_Select_Bit = 0x80,
 136         Gi_Output_Mode_Mask = 0x300,
 137         Gi_Output_TC_Pulse_Bits = 0x100,
 138         Gi_Output_TC_Toggle_Bits = 0x200,
 139         Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
 140         Gi_Counting_Once_Mask = 0xc00,
 141         Gi_No_Hardware_Disarm_Bits = 0x000,
 142         Gi_Disarm_at_TC_Bits = 0x400,
 143         Gi_Disarm_at_Gate_Bits = 0x800,
 144         Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
 145         Gi_Loading_On_TC_Bit = 0x1000,
 146         Gi_Gate_Polarity_Bit = 0x2000,
 147         Gi_Loading_On_Gate_Bit = 0x4000,
 148         Gi_Reload_Source_Switching_Bit = 0x8000
 149 };
 150
 151 #define Gi_Second_Gate_Select_Shift 7
 152 /*FIXME: m-series has a second gate subselect bit */
 153 /*FIXME: m-series second gate sources are undocumented (by NI)*/
 154 enum Gi_Second_Gate_Bits {
 155         Gi_Second_Gate_Mode_Bit = 0x1,
 156         Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
 157         Gi_Second_Gate_Polarity_Bit = 0x2000,
 158         Gi_Second_Gate_Subselect_Bit = 0x4000,  /* m-series only */
 159         Gi_Source_Subselect_Bit = 0x8000        /* m-series only */
 160 };
 161 static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
 162 {
 163         return (second_gate_select << Gi_Second_Gate_Select_Shift) &
 164             Gi_Second_Gate_Select_Mask;
 165 }
 166
 167 enum Gxx_Status_Bits {
 168         G0_Save_Bit = 0x1,
 169         G1_Save_Bit = 0x2,
 170         G0_Counting_Bit = 0x4,
 171         G1_Counting_Bit = 0x8,
 172         G0_Next_Load_Source_Bit = 0x10,
 173         G1_Next_Load_Source_Bit = 0x20,
 174         G0_Stale_Data_Bit = 0x40,
 175         G1_Stale_Data_Bit = 0x80,
 176         G0_Armed_Bit = 0x100,
 177         G1_Armed_Bit = 0x200,
 178         G0_No_Load_Between_Gates_Bit = 0x400,
 179         G1_No_Load_Between_Gates_Bit = 0x800,
 180         G0_TC_Error_Bit = 0x1000,
 181         G1_TC_Error_Bit = 0x2000,
 182         G0_Gate_Error_Bit = 0x4000,
 183         G1_Gate_Error_Bit = 0x8000
 184 };
 185 static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
 186 {
 187         if (counter_index % 2)
 188                 return G1_Counting_Bit;
 189         return G0_Counting_Bit;
 190 }
 191
 192 static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
 193 {
 194         if (counter_index % 2)
 195                 return G1_Armed_Bit;
 196         return G0_Armed_Bit;
 197 }
 198
 199 static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
 200                                                            counter_index)
 201 {
 202         if (counter_index % 2)
 203                 return G1_Next_Load_Source_Bit;
 204         return G0_Next_Load_Source_Bit;
 205 }
 206
 207 static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
 208 {
 209         if (counter_index % 2)
 210                 return G1_Stale_Data_Bit;
 211         return G0_Stale_Data_Bit;
 212 }
 213
 214 static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
 215 {
 216         if (counter_index % 2)
 217                 return G1_TC_Error_Bit;
 218         return G0_TC_Error_Bit;
 219 }
 220
 221 static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
 222 {
 223         if (counter_index % 2)
 224                 return G1_Gate_Error_Bit;
 225         return G0_Gate_Error_Bit;
 226 }
 227
 228 /* joint reset register bits */
 229 static inline unsigned Gi_Reset_Bit(unsigned counter_index)
 230 {
 231         return 0x1 << (2 + (counter_index % 2));
 232 }
 233
 234 enum Gxx_Joint_Status2_Bits {
 235         G0_Output_Bit = 0x1,
 236         G1_Output_Bit = 0x2,
 237         G0_HW_Save_Bit = 0x1000,
 238         G1_HW_Save_Bit = 0x2000,
 239         G0_Permanent_Stale_Bit = 0x4000,
 240         G1_Permanent_Stale_Bit = 0x8000
 241 };
 242 static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
 243                                                                  counter_index)
 244 {
 245         if (counter_index % 2)
 246                 return G1_Permanent_Stale_Bit;
 247         return G0_Permanent_Stale_Bit;
 248 }
 249
 250 enum Gi_DMA_Config_Reg_Bits {
 251         Gi_DMA_Enable_Bit = 0x1,
 252         Gi_DMA_Write_Bit = 0x2,
 253         Gi_DMA_Int_Bit = 0x4
 254 };
 255
 256 enum Gi_DMA_Status_Reg_Bits {
 257         Gi_DMA_Readbank_Bit = 0x2000,
 258         Gi_DRQ_Error_Bit = 0x4000,
 259         Gi_DRQ_Status_Bit = 0x8000
 260 };
 261
 262 enum G02_Interrupt_Acknowledge_Bits {
 263         G0_Gate_Error_Confirm_Bit = 0x20,
 264         G0_TC_Error_Confirm_Bit = 0x40
 265 };
 266 enum G13_Interrupt_Acknowledge_Bits {
 267         G1_Gate_Error_Confirm_Bit = 0x2,
 268         G1_TC_Error_Confirm_Bit = 0x4
 269 };
 270 static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
 271 {
 272         if (counter_index % 2)
 273                 return G1_Gate_Error_Confirm_Bit;
 274         return G0_Gate_Error_Confirm_Bit;
 275 }
 276
 277 static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
 278 {
 279         if (counter_index % 2)
 280                 return G1_TC_Error_Confirm_Bit;
 281         return G0_TC_Error_Confirm_Bit;
 282 }
 283
 284 /* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
 285 enum Gxx_Interrupt_Acknowledge_Bits {
 286         Gi_TC_Interrupt_Ack_Bit = 0x4000,
 287         Gi_Gate_Interrupt_Ack_Bit = 0x8000
 288 };
 289
 290 enum Gi_Status_Bits {
 291         Gi_Gate_Interrupt_Bit = 0x4,
 292         Gi_TC_Bit = 0x8,
 293         Gi_Interrupt_Bit = 0x8000
 294 };
 295
 296 enum G02_Interrupt_Enable_Bits {
 297         G0_TC_Interrupt_Enable_Bit = 0x40,
 298         G0_Gate_Interrupt_Enable_Bit = 0x100
 299 };
 300 enum G13_Interrupt_Enable_Bits {
 301         G1_TC_Interrupt_Enable_Bit = 0x200,
 302         G1_Gate_Interrupt_Enable_Bit = 0x400
 303 };
 304 static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
 305 {
 306         unsigned bit;
 307
 308         if (counter_index % 2)
 309                 bit = G1_Gate_Interrupt_Enable_Bit;
 310         else
 311                 bit = G0_Gate_Interrupt_Enable_Bit;
 312         return bit;
 313 }
 314
 315 static inline void write_register(struct ni_gpct *counter, unsigned bits,
 316                                   enum ni_gpct_register reg)
 317 {
 318         BUG_ON(reg >= NITIO_NUM_REGS);
 319         counter->counter_dev->write_register(counter, bits, reg);
 320 }
 321
 322 static inline unsigned read_register(struct ni_gpct *counter,
 323                                      enum ni_gpct_register reg)
 324 {
 325         BUG_ON(reg >= NITIO_NUM_REGS);
 326         return counter->counter_dev->read_register(counter, reg);
 327 }
 328
 329 static inline int ni_tio_counting_mode_registers_present(const struct
 330                                                          ni_gpct_device
 331                                                          *counter_dev)
 332 {
 333         switch (counter_dev->variant) {
 334         case ni_gpct_variant_e_series:
 335                 return 0;
 336                 break;
 337         case ni_gpct_variant_m_series:
 338         case ni_gpct_variant_660x:
 339                 return 1;
 340                 break;
 341         default:
 342                 BUG();
 343                 break;
 344         }
 345         return 0;
 346 }
 347
 348 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
 349                                              enum ni_gpct_register
 350                                              register_index, unsigned bit_mask,
 351                                              unsigned bit_values,
 352                                              unsigned transient_bit_values)
 353 {
 354         struct ni_gpct_device *counter_dev = counter->counter_dev;
 355         unsigned long flags;
 356
 357         BUG_ON(register_index >= NITIO_NUM_REGS);
 358         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 359         counter_dev->regs[register_index] &= ~bit_mask;
 360         counter_dev->regs[register_index] |= (bit_values & bit_mask);
 361         write_register(counter,
 362                        counter_dev->regs[register_index] | transient_bit_values,
 363                        register_index);
 364         mmiowb();
 365         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 366 }
 367
 368 /* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
 369  * twiddled in interrupt context, or whose software copy may be read in
 370  * interrupt context.
 371  */
 372 static inline void ni_tio_set_bits(struct ni_gpct *counter,
 373                                    enum ni_gpct_register register_index,
 374                                    unsigned bit_mask, unsigned bit_values)
 375 {
 376         ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
 377                                   0x0);
 378 }
 379
 380 /* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
 381 whose bits might be modified in interrupt context, or whose software copy
 382 might need to be read in interrupt context.
 383 */
 384 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
 385                                             enum ni_gpct_register
 386                                             register_index)
 387 {
 388         struct ni_gpct_device *counter_dev = counter->counter_dev;
 389         unsigned long flags;
 390         unsigned value;
 391
 392         BUG_ON(register_index >= NITIO_NUM_REGS);
 393         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 394         value = counter_dev->regs[register_index];
 395         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 396         return value;
 397 }
 398
 399 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
 400 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
 401                         unsigned int gate_source);
 402
 403 #endif /* _COMEDI_NI_TIO_INTERNAL_H */