drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         The PCI-MIO E series driver was originally written by
  26         Tomasz Motylewski <...>, and ported to comedi by ds.
  27
  28         References for specifications:
  29
  30            321747b.pdf  Register Level Programmer Manual (obsolete)
  31            321747c.pdf  Register Level Programmer Manual (new)
  32            DAQ-STC reference manual
  33
  34         Other possibly relevant info:
  35
  36            320517c.pdf  User manual (obsolete)
  37            320517f.pdf  User manual (new)
  38            320889a.pdf  delete
  39            320906c.pdf  maximum signal ratings
  40            321066a.pdf  about 16x
  41            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  42            321808a.pdf  about at-mio-16e-10 rev P
  43            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  44            321838a.pdf  about at-mio-16de-10 rev N
  45
  46         ISSUES:
  47
  48 */
  49
  50 /* #define USE_KMALLOC */
  51
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 #include "mite.h"
  55
  56 #include "comedi_fc.h"
  57 #include "../comedidev.h"
  58
  59
  60 #define PCI_MITE_SIZE           4096
  61 #define PCI_DAQ_SIZE            4096
  62 #define PCI_DAQ_SIZE_660X       8192
  63
  64 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  65
  66 struct mite_struct *mite_alloc(struct pci_dev *pcidev)
  67 {
  68         struct mite_struct *mite;
  69         unsigned int i;
  70
  71         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  72         if (mite) {
  73                 spin_lock_init(&mite->lock);
  74                 mite->pcidev = pcidev;
  75                 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  76                         mite->channels[i].mite = mite;
  77                         mite->channels[i].channel = i;
  78                         mite->channels[i].done = 1;
  79                 }
  80         }
  81         return mite;
  82 }
  83 EXPORT_SYMBOL(mite_alloc);
  84
  85 static void dump_chip_signature(u32 csigr_bits)
  86 {
  87         pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
  88                 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
  89                 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
  90         pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
  91                 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
  92                 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
  93 }
  94
  95 static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
  96 {
  97         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
  98         unsigned empty_count = (fcr_bits >> 16) & 0xff;
  99         unsigned full_count = fcr_bits & 0xff;
 100         return empty_count + full_count;
 101 }
 102
 103 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
 104 {
 105         unsigned long length;
 106         resource_size_t addr;
 107         int i;
 108         u32 csigr_bits;
 109         unsigned unknown_dma_burst_bits;
 110
 111         if (comedi_pci_enable(mite->pcidev, "mite")) {
 112                 dev_err(&mite->pcidev->dev,
 113                         "error enabling mite and requesting io regions\n");
 114                 return -EIO;
 115         }
 116         pci_set_master(mite->pcidev);
 117
 118         addr = pci_resource_start(mite->pcidev, 0);
 119         mite->mite_phys_addr = addr;
 120         mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
 121         if (!mite->mite_io_addr) {
 122                 dev_err(&mite->pcidev->dev,
 123                         "Failed to remap mite io memory address\n");
 124                 return -ENOMEM;
 125         }
 126
 127         addr = pci_resource_start(mite->pcidev, 1);
 128         mite->daq_phys_addr = addr;
 129         length = pci_resource_len(mite->pcidev, 1);
 130         /*
 131          * In case of a 660x board, DAQ size is 8k instead of 4k
 132          * (see as shown by lspci output)
 133          */
 134         mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
 135         if (!mite->daq_io_addr) {
 136                 dev_err(&mite->pcidev->dev,
 137                         "Failed to remap daq io memory address\n");
 138                 return -ENOMEM;
 139         }
 140
 141         if (use_iodwbsr_1) {
 142                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 143                 dev_info(&mite->pcidev->dev,
 144                          "using I/O Window Base Size register 1\n");
 145                 writel(mite->daq_phys_addr | WENAB |
 146                        MITE_IODWBSR_1_WSIZE_bits(length),
 147                        mite->mite_io_addr + MITE_IODWBSR_1);
 148                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 149         } else {
 150                 writel(mite->daq_phys_addr | WENAB,
 151                        mite->mite_io_addr + MITE_IODWBSR);
 152         }
 153         /*
 154          * make sure dma bursts work. I got this from running a bus analyzer
 155          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 156          * of 0x61f and bursts worked. 6281 powered up with register value of
 157          * 0x1f and bursts didn't work. The NI windows driver reads the
 158          * register, then does a bitwise-or of 0x600 with it and writes it back.
 159          */
 160         unknown_dma_burst_bits =
 161             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 162         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 163         writel(unknown_dma_burst_bits,
 164                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 165
 166         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 167         mite->num_channels = mite_csigr_dmac(csigr_bits);
 168         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 169                 dev_warn(&mite->pcidev->dev,
 170                          "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
 171                          mite->num_channels, MAX_MITE_DMA_CHANNELS);
 172                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 173         }
 174         dump_chip_signature(csigr_bits);
 175         for (i = 0; i < mite->num_channels; i++) {
 176                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 177                 /* disable interrupts */
 178                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 179                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 180                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 181                        mite->mite_io_addr + MITE_CHCR(i));
 182         }
 183         mite->fifo_size = mite_fifo_size(mite, 0);
 184         dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
 185         return 0;
 186 }
 187 EXPORT_SYMBOL(mite_setup2);
 188
 189 int mite_setup(struct mite_struct *mite)
 190 {
 191         return mite_setup2(mite, 0);
 192 }
 193 EXPORT_SYMBOL(mite_setup);
 194
 195 void mite_unsetup(struct mite_struct *mite)
 196 {
 197         /* unsigned long offset, start, length; */
 198
 199         if (!mite)
 200                 return;
 201
 202         if (mite->mite_io_addr) {
 203                 iounmap(mite->mite_io_addr);
 204                 mite->mite_io_addr = NULL;
 205         }
 206         if (mite->daq_io_addr) {
 207                 iounmap(mite->daq_io_addr);
 208                 mite->daq_io_addr = NULL;
 209         }
 210         if (mite->mite_phys_addr) {
 211                 comedi_pci_disable(mite->pcidev);
 212                 mite->mite_phys_addr = 0;
 213         }
 214 }
 215 EXPORT_SYMBOL(mite_unsetup);
 216
 217 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
 218 {
 219         struct mite_dma_descriptor_ring *ring =
 220             kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
 221
 222         if (ring == NULL)
 223                 return ring;
 224         ring->hw_dev = get_device(&mite->pcidev->dev);
 225         if (ring->hw_dev == NULL) {
 226                 kfree(ring);
 227                 return NULL;
 228         }
 229         ring->n_links = 0;
 230         ring->descriptors = NULL;
 231         ring->descriptors_dma_addr = 0;
 232         return ring;
 233 };
 234 EXPORT_SYMBOL(mite_alloc_ring);
 235
 236 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
 237 {
 238         if (ring) {
 239                 if (ring->descriptors) {
 240                         dma_free_coherent(ring->hw_dev,
 241                                           ring->n_links *
 242                                           sizeof(struct mite_dma_descriptor),
 243                                           ring->descriptors,
 244                                           ring->descriptors_dma_addr);
 245                 }
 246                 put_device(ring->hw_dev);
 247                 kfree(ring);
 248         }
 249 };
 250 EXPORT_SYMBOL(mite_free_ring);
 251
 252 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 253                                                    struct
 254                                                    mite_dma_descriptor_ring
 255                                                    *ring, unsigned min_channel,
 256                                                    unsigned max_channel)
 257 {
 258         int i;
 259         unsigned long flags;
 260         struct mite_channel *channel = NULL;
 261
 262         /* spin lock so mite_release_channel can be called safely
 263          * from interrupts
 264          */
 265         spin_lock_irqsave(&mite->lock, flags);
 266         for (i = min_channel; i <= max_channel; ++i) {
 267                 if (mite->channel_allocated[i] == 0) {
 268                         mite->channel_allocated[i] = 1;
 269                         channel = &mite->channels[i];
 270                         channel->ring = ring;
 271                         break;
 272                 }
 273         }
 274         spin_unlock_irqrestore(&mite->lock, flags);
 275         return channel;
 276 }
 277 EXPORT_SYMBOL(mite_request_channel_in_range);
 278
 279 void mite_release_channel(struct mite_channel *mite_chan)
 280 {
 281         struct mite_struct *mite = mite_chan->mite;
 282         unsigned long flags;
 283
 284         /*  spin lock to prevent races with mite_request_channel */
 285         spin_lock_irqsave(&mite->lock, flags);
 286         if (mite->channel_allocated[mite_chan->channel]) {
 287                 mite_dma_disarm(mite_chan);
 288                 mite_dma_reset(mite_chan);
 289         /*
 290          * disable all channel's interrupts (do it after disarm/reset so
 291          * MITE_CHCR reg isn't changed while dma is still active!)
 292          */
 293                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 294                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 295                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 296                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 297                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 298                 mite->channel_allocated[mite_chan->channel] = 0;
 299                 mite_chan->ring = NULL;
 300                 mmiowb();
 301         }
 302         spin_unlock_irqrestore(&mite->lock, flags);
 303 }
 304 EXPORT_SYMBOL(mite_release_channel);
 305
 306 void mite_dma_arm(struct mite_channel *mite_chan)
 307 {
 308         struct mite_struct *mite = mite_chan->mite;
 309         int chor;
 310         unsigned long flags;
 311
 312         MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
 313         /*
 314          * memory barrier is intended to insure any twiddling with the buffer
 315          * is done before writing to the mite to arm dma transfer
 316          */
 317         smp_mb();
 318         /* arm */
 319         chor = CHOR_START;
 320         spin_lock_irqsave(&mite->lock, flags);
 321         mite_chan->done = 0;
 322         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 323         mmiowb();
 324         spin_unlock_irqrestore(&mite->lock, flags);
 325 /*       mite_dma_tcr(mite, channel); */
 326 }
 327 EXPORT_SYMBOL(mite_dma_arm);
 328
 329 /**************************************/
 330
 331 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 332                     struct comedi_async *async)
 333 {
 334         unsigned int n_links;
 335         int i;
 336
 337         if (ring->descriptors) {
 338                 dma_free_coherent(ring->hw_dev,
 339                                   ring->n_links *
 340                                   sizeof(struct mite_dma_descriptor),
 341                                   ring->descriptors,
 342                                   ring->descriptors_dma_addr);
 343         }
 344         ring->descriptors = NULL;
 345         ring->descriptors_dma_addr = 0;
 346         ring->n_links = 0;
 347
 348         if (async->prealloc_bufsz == 0)
 349                 return 0;
 350
 351         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 352
 353         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 354
 355         ring->descriptors =
 356             dma_alloc_coherent(ring->hw_dev,
 357                                n_links * sizeof(struct mite_dma_descriptor),
 358                                &ring->descriptors_dma_addr, GFP_KERNEL);
 359         if (!ring->descriptors) {
 360                 dev_err(async->subdevice->device->class_dev,
 361                         "mite: ring buffer allocation failed\n");
 362                 return -ENOMEM;
 363         }
 364         ring->n_links = n_links;
 365
 366         for (i = 0; i < n_links; i++) {
 367                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 368                 ring->descriptors[i].addr =
 369                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 370                 ring->descriptors[i].next =
 371                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 372                                                               1) *
 373                                 sizeof(struct mite_dma_descriptor));
 374         }
 375         ring->descriptors[n_links - 1].next =
 376             cpu_to_le32(ring->descriptors_dma_addr);
 377         /*
 378          * barrier is meant to insure that all the writes to the dma descriptors
 379          * have completed before the dma controller is commanded to read them
 380          */
 381         smp_wmb();
 382         return 0;
 383 }
 384 EXPORT_SYMBOL(mite_buf_change);
 385
 386 void mite_prep_dma(struct mite_channel *mite_chan,
 387                    unsigned int num_device_bits, unsigned int num_memory_bits)
 388 {
 389         unsigned int chor, chcr, mcr, dcr, lkcr;
 390         struct mite_struct *mite = mite_chan->mite;
 391
 392         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 393
 394         /* reset DMA and FIFO */
 395         chor = CHOR_DMARESET | CHOR_FRESET;
 396         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 397
 398         /* short link chaining mode */
 399         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 400             CHCR_BURSTEN;
 401         /*
 402          * Link Complete Interrupt: interrupt every time a link
 403          * in MITE_RING is completed. This can generate a lot of
 404          * extra interrupts, but right now we update the values
 405          * of buf_int_ptr and buf_int_count at each interrupt. A
 406          * better method is to poll the MITE before each user
 407          * "read()" to calculate the number of bytes available.
 408          */
 409         chcr |= CHCR_SET_LC_IE;
 410         if (num_memory_bits == 32 && num_device_bits == 16) {
 411                 /*
 412                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 413                  * samples into the fifo in the right order. Tested doing 32 bit
 414                  * memory to 16 bit device transfers to the analog out of a
 415                  * pxi-6281, which has mite version = 1, type = 4. This also
 416                  * works for dma reads from the counters on e-series boards.
 417                  */
 418                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 419         }
 420         if (mite_chan->dir == COMEDI_INPUT)
 421                 chcr |= CHCR_DEV_TO_MEM;
 422
 423         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 424
 425         /* to/from memory */
 426         mcr = CR_RL(64) | CR_ASEQUP;
 427         switch (num_memory_bits) {
 428         case 8:
 429                 mcr |= CR_PSIZE8;
 430                 break;
 431         case 16:
 432                 mcr |= CR_PSIZE16;
 433                 break;
 434         case 32:
 435                 mcr |= CR_PSIZE32;
 436                 break;
 437         default:
 438                 pr_warn("bug! invalid mem bit width for dma transfer\n");
 439                 break;
 440         }
 441         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 442
 443         /* from/to device */
 444         dcr = CR_RL(64) | CR_ASEQUP;
 445         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 446         switch (num_device_bits) {
 447         case 8:
 448                 dcr |= CR_PSIZE8;
 449                 break;
 450         case 16:
 451                 dcr |= CR_PSIZE16;
 452                 break;
 453         case 32:
 454                 dcr |= CR_PSIZE32;
 455                 break;
 456         default:
 457                 pr_warn("bug! invalid dev bit width for dma transfer\n");
 458                 break;
 459         }
 460         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 461
 462         /* reset the DAR */
 463         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 464
 465         /* the link is 32bits */
 466         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 467         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 468
 469         /* starting address for link chaining */
 470         writel(mite_chan->ring->descriptors_dma_addr,
 471                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 472
 473         MDPRINTK("exit mite_prep_dma\n");
 474 }
 475 EXPORT_SYMBOL(mite_prep_dma);
 476
 477 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 478 {
 479         struct mite_struct *mite = mite_chan->mite;
 480         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 481 }
 482
 483 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 484 {
 485         struct mite_struct *mite = mite_chan->mite;
 486         return readl(mite->mite_io_addr +
 487                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 488 }
 489 EXPORT_SYMBOL(mite_bytes_in_transit);
 490
 491 /* returns lower bound for number of bytes transferred from device to memory */
 492 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 493 {
 494         u32 device_byte_count;
 495
 496         device_byte_count = mite_device_bytes_transferred(mite_chan);
 497         return device_byte_count - mite_bytes_in_transit(mite_chan);
 498 }
 499 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
 500
 501 /* returns upper bound for number of bytes transferred from device to memory */
 502 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 503 {
 504         u32 in_transit_count;
 505
 506         in_transit_count = mite_bytes_in_transit(mite_chan);
 507         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 508 }
 509 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
 510
 511 /* returns lower bound for number of bytes read from memory to device */
 512 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 513 {
 514         u32 device_byte_count;
 515
 516         device_byte_count = mite_device_bytes_transferred(mite_chan);
 517         return device_byte_count + mite_bytes_in_transit(mite_chan);
 518 }
 519 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
 520
 521 /* returns upper bound for number of bytes read from memory to device */
 522 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 523 {
 524         u32 in_transit_count;
 525
 526         in_transit_count = mite_bytes_in_transit(mite_chan);
 527         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 528 }
 529 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
 530
 531 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 532 {
 533         struct mite_struct *mite = mite_chan->mite;
 534         int tcr;
 535         int lkar;
 536
 537         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 538         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 539         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 540                  lkar, tcr);
 541
 542         return tcr;
 543 }
 544 EXPORT_SYMBOL(mite_dma_tcr);
 545
 546 void mite_dma_disarm(struct mite_channel *mite_chan)
 547 {
 548         struct mite_struct *mite = mite_chan->mite;
 549         unsigned chor;
 550
 551         /* disarm */
 552         chor = CHOR_ABORT;
 553         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 554 }
 555 EXPORT_SYMBOL(mite_dma_disarm);
 556
 557 int mite_sync_input_dma(struct mite_channel *mite_chan,
 558                         struct comedi_async *async)
 559 {
 560         int count;
 561         unsigned int nbytes, old_alloc_count;
 562         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 563
 564         old_alloc_count = async->buf_write_alloc_count;
 565         /* write alloc as much as we can */
 566         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 567
 568         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 569         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 570                   old_alloc_count) > 0) {
 571                 dev_warn(async->subdevice->device->class_dev,
 572                          "mite: DMA overwrite of free area\n");
 573                 async->events |= COMEDI_CB_OVERFLOW;
 574                 return -1;
 575         }
 576
 577         count = nbytes - async->buf_write_count;
 578         /* it's possible count will be negative due to
 579          * conservative value returned by mite_bytes_written_to_memory_lb */
 580         if (count <= 0)
 581                 return 0;
 582
 583         comedi_buf_write_free(async, count);
 584
 585         async->scan_progress += count;
 586         if (async->scan_progress >= bytes_per_scan) {
 587                 async->scan_progress %= bytes_per_scan;
 588                 async->events |= COMEDI_CB_EOS;
 589         }
 590         async->events |= COMEDI_CB_BLOCK;
 591         return 0;
 592 }
 593 EXPORT_SYMBOL(mite_sync_input_dma);
 594
 595 int mite_sync_output_dma(struct mite_channel *mite_chan,
 596                          struct comedi_async *async)
 597 {
 598         int count;
 599         u32 nbytes_ub, nbytes_lb;
 600         unsigned int old_alloc_count;
 601         u32 stop_count =
 602             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 603
 604         old_alloc_count = async->buf_read_alloc_count;
 605         /*  read alloc as much as we can */
 606         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 607         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 608         if (async->cmd.stop_src == TRIG_COUNT &&
 609             (int)(nbytes_lb - stop_count) > 0)
 610                 nbytes_lb = stop_count;
 611         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 612         if (async->cmd.stop_src == TRIG_COUNT &&
 613             (int)(nbytes_ub - stop_count) > 0)
 614                 nbytes_ub = stop_count;
 615         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 616                 dev_warn(async->subdevice->device->class_dev,
 617                          "mite: DMA underrun\n");
 618                 async->events |= COMEDI_CB_OVERFLOW;
 619                 return -1;
 620         }
 621         count = nbytes_lb - async->buf_read_count;
 622         if (count <= 0)
 623                 return 0;
 624
 625         if (count) {
 626                 comedi_buf_read_free(async, count);
 627                 async->events |= COMEDI_CB_BLOCK;
 628         }
 629         return 0;
 630 }
 631 EXPORT_SYMBOL(mite_sync_output_dma);
 632
 633 unsigned mite_get_status(struct mite_channel *mite_chan)
 634 {
 635         struct mite_struct *mite = mite_chan->mite;
 636         unsigned status;
 637         unsigned long flags;
 638
 639         spin_lock_irqsave(&mite->lock, flags);
 640         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 641         if (status & CHSR_DONE) {
 642                 mite_chan->done = 1;
 643                 writel(CHOR_CLRDONE,
 644                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 645         }
 646         mmiowb();
 647         spin_unlock_irqrestore(&mite->lock, flags);
 648         return status;
 649 }
 650 EXPORT_SYMBOL(mite_get_status);
 651
 652 int mite_done(struct mite_channel *mite_chan)
 653 {
 654         struct mite_struct *mite = mite_chan->mite;
 655         unsigned long flags;
 656         int done;
 657
 658         mite_get_status(mite_chan);
 659         spin_lock_irqsave(&mite->lock, flags);
 660         done = mite_chan->done;
 661         spin_unlock_irqrestore(&mite->lock, flags);
 662         return done;
 663 }
 664 EXPORT_SYMBOL(mite_done);
 665
 666 #ifdef DEBUG_MITE
 667
 668 /* names of bits in mite registers */
 669
 670 static const char *const mite_CHOR_strings[] = {
 671         "start", "cont", "stop", "abort",
 672         "freset", "clrlc", "clrrb", "clrdone",
 673         "clr_lpause", "set_lpause", "clr_send_tc",
 674         "set_send_tc", "12", "13", "14",
 675         "15", "16", "17", "18",
 676         "19", "20", "21", "22",
 677         "23", "24", "25", "26",
 678         "27", "28", "29", "30",
 679         "dmareset",
 680 };
 681
 682 static const char *const mite_CHCR_strings[] = {
 683         "continue", "ringbuff", "2", "3",
 684         "4", "5", "6", "7",
 685         "8", "9", "10", "11",
 686         "12", "13", "bursten", "fifodis",
 687         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 688         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 689         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 690         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 691 };
 692
 693 static const char *const mite_MCR_strings[] = {
 694         "amdevice", "1", "2", "3",
 695         "4", "5", "portio", "portvxi",
 696         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 697         "12", "13", "blocken", "berhand",
 698         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 699         "rd512", "rl1", "rl2", "rl8",
 700         "24", "25", "26", "27",
 701         "28", "29", "30", "stopen",
 702 };
 703
 704 static const char *const mite_DCR_strings[] = {
 705         "amdevice", "1", "2", "3",
 706         "4", "5", "portio", "portvxi",
 707         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 708         "aseqxp8", "13", "blocken", "berhand",
 709         "reqsintlim", "reqs1", "reqs2", "rd32",
 710         "rd512", "rl1", "rl2", "rl8",
 711         "23", "24", "25", "27",
 712         "28", "wsdevc", "wsdevs", "rwdevpack",
 713 };
 714
 715 static const char *const mite_LKCR_strings[] = {
 716         "amdevice", "1", "2", "3",
 717         "4", "5", "portio", "portvxi",
 718         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 719         "12", "13", "14", "berhand",
 720         "16", "17", "18", "rd32",
 721         "rd512", "rl1", "rl2", "rl8",
 722         "24", "25", "26", "27",
 723         "28", "29", "30", "chngend",
 724 };
 725
 726 static const char *const mite_CHSR_strings[] = {
 727         "d.err0", "d.err1", "m.err0", "m.err1",
 728         "l.err0", "l.err1", "drq0", "drq1",
 729         "end", "xferr", "operr0", "operr1",
 730         "stops", "habort", "sabort", "error",
 731         "16", "conts_rb", "18", "linkc",
 732         "20", "drdy", "22", "mrdy",
 733         "24", "done", "26", "sars",
 734         "28", "lpauses", "30", "int",
 735 };
 736
 737 static void mite_decode(const char *const *bit_str, unsigned int bits)
 738 {
 739         int i;
 740
 741         for (i = 31; i >= 0; i--) {
 742                 if (bits & (1 << i))
 743                         pr_debug(" %s\n", bit_str[i]);
 744         }
 745 }
 746
 747 void mite_dump_regs(struct mite_channel *mite_chan)
 748 {
 749         void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
 750         unsigned int offset;
 751         unsigned int value;
 752         int channel = mite_chan->channel;
 753
 754         pr_debug("mite_dump_regs ch%i\n", channel);
 755         pr_debug("mite address is  =%p\n", mite_io_addr);
 756
 757         offset = MITE_CHOR(channel);
 758         value = readl(mite_io_addr + offset);
 759         pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
 760         mite_decode(mite_CHOR_strings, value);
 761         offset = MITE_CHCR(channel);
 762         value = readl(mite_io_addr + offset);
 763         pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
 764         mite_decode(mite_CHCR_strings, value);
 765         offset = MITE_TCR(channel);
 766         value = readl(mite_io_addr + offset);
 767         pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
 768         offset = MITE_MCR(channel);
 769         value = readl(mite_io_addr + offset);
 770         pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
 771         mite_decode(mite_MCR_strings, value);
 772         offset = MITE_MAR(channel);
 773         value = readl(mite_io_addr + offset);
 774         pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
 775         offset = MITE_DCR(channel);
 776         value = readl(mite_io_addr + offset);
 777         pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
 778         mite_decode(mite_DCR_strings, value);
 779         offset = MITE_DAR(channel);
 780         value = readl(mite_io_addr + offset);
 781         pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
 782         offset = MITE_LKCR(channel);
 783         value = readl(mite_io_addr + offset);
 784         pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
 785         mite_decode(mite_LKCR_strings, value);
 786         offset = MITE_LKAR(channel);
 787         value = readl(mite_io_addr + offset);
 788         pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
 789         offset = MITE_CHSR(channel);
 790         value = readl(mite_io_addr + offset);
 791         pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
 792         mite_decode(mite_CHSR_strings, value);
 793         offset = MITE_FCR(channel);
 794         value = readl(mite_io_addr + offset);
 795         pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
 796 }
 797 EXPORT_SYMBOL(mite_dump_regs);
 798 #endif
 799
 800 static int __init mite_module_init(void)
 801 {
 802         return 0;
 803 }
 804
 805 static void __exit mite_module_exit(void)
 806 {
 807 }
 808
 809 module_init(mite_module_init);
 810 module_exit(mite_module_exit);
 811
 812 MODULE_AUTHOR("Comedi http://www.comedi.org");
 813 MODULE_DESCRIPTION("Comedi low-level driver");
 814 MODULE_LICENSE("GPL");