3 comedi/drivers/me_daq.c
5 Hardware driver for Meilhaus data acquisition cards:
7 ME-2000i, ME-2600i, ME-3000vm1
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
37 Configuration options:
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
42 If bus/slot is not specified, the first available PCI
45 The 2600 requires a firmware upload, which can be accomplished
46 using the -i or --init-data option of comedi_config.
48 found in the comedi_nonfree_firmware tarball available
49 from http://www.comedi.org
53 #include <linux/interrupt.h>
54 #include <linux/sched.h>
55 #include "../comedidev.h"
57 /*#include "me2600_fw.h" */
59 #define ME_DRIVER_NAME "me_daq"
61 #define PCI_VENDOR_ID_MEILHAUS 0x1402
62 #define ME2000_DEVICE_ID 0x2000
63 #define ME2600_DEVICE_ID 0x2600
65 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
66 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
68 #define ME_CONTROL_1 0x0000 /* - | W */
69 #define INTERRUPT_ENABLE (1<<15)
70 #define COUNTER_B_IRQ (1<<12)
71 #define COUNTER_A_IRQ (1<<11)
72 #define CHANLIST_READY_IRQ (1<<10)
73 #define EXT_IRQ (1<<9)
74 #define ADFIFO_HALFFULL_IRQ (1<<8)
75 #define SCAN_COUNT_ENABLE (1<<5)
76 #define SIMULTANEOUS_ENABLE (1<<4)
77 #define TRIGGER_FALLING_EDGE (1<<3)
78 #define CONTINUOUS_MODE (1<<2)
79 #define DISABLE_ADC (0<<0)
80 #define SOFTWARE_TRIGGERED_ADC (1<<0)
81 #define SCAN_TRIGGERED_ADC (2<<0)
82 #define EXT_TRIGGERED_ADC (3<<0)
83 #define ME_ADC_START 0x0000 /* R | - */
84 #define ME_CONTROL_2 0x0002 /* - | W */
85 #define ENABLE_ADFIFO (1<<10)
86 #define ENABLE_CHANLIST (1<<9)
87 #define ENABLE_PORT_B (1<<7)
88 #define ENABLE_PORT_A (1<<6)
89 #define ENABLE_COUNTER_B (1<<4)
90 #define ENABLE_COUNTER_A (1<<3)
91 #define ENABLE_DAC (1<<1)
92 #define BUFFERED_DAC (1<<0)
93 #define ME_DAC_UPDATE 0x0002 /* R | - */
94 #define ME_STATUS 0x0004 /* R | - */
95 #define COUNTER_B_IRQ_PENDING (1<<12)
96 #define COUNTER_A_IRQ_PENDING (1<<11)
97 #define CHANLIST_READY_IRQ_PENDING (1<<10)
98 #define EXT_IRQ_PENDING (1<<9)
99 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
100 #define ADFIFO_FULL (1<<4)
101 #define ADFIFO_HALFFULL (1<<3)
102 #define ADFIFO_EMPTY (1<<2)
103 #define CHANLIST_FULL (1<<1)
104 #define FST_ACTIVE (1<<0)
105 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
106 #define ME_DIO_PORT_A 0x0006 /* R | W */
107 #define ME_DIO_PORT_B 0x0008 /* R | W */
108 #define ME_TIMER_DATA_0 0x000A /* - | W */
109 #define ME_TIMER_DATA_1 0x000C /* - | W */
110 #define ME_TIMER_DATA_2 0x000E /* - | W */
111 #define ME_CHANNEL_LIST 0x0010 /* - | W */
112 #define ADC_UNIPOLAR (1<<6)
113 #define ADC_GAIN_0 (0<<4)
114 #define ADC_GAIN_1 (1<<4)
115 #define ADC_GAIN_2 (2<<4)
116 #define ADC_GAIN_3 (3<<4)
117 #define ME_READ_AD_FIFO 0x0010 /* R | - */
118 #define ME_DAC_CONTROL 0x0012 /* - | W */
119 #define DAC_UNIPOLAR_D (0<<4)
120 #define DAC_BIPOLAR_D (1<<4)
121 #define DAC_UNIPOLAR_C (0<<5)
122 #define DAC_BIPOLAR_C (1<<5)
123 #define DAC_UNIPOLAR_B (0<<6)
124 #define DAC_BIPOLAR_B (1<<6)
125 #define DAC_UNIPOLAR_A (0<<7)
126 #define DAC_BIPOLAR_A (1<<7)
127 #define DAC_GAIN_0_D (0<<8)
128 #define DAC_GAIN_1_D (1<<8)
129 #define DAC_GAIN_0_C (0<<9)
130 #define DAC_GAIN_1_C (1<<9)
131 #define DAC_GAIN_0_B (0<<10)
132 #define DAC_GAIN_1_B (1<<10)
133 #define DAC_GAIN_0_A (0<<11)
134 #define DAC_GAIN_1_A (1<<11)
135 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
136 #define ME_DAC_DATA_A 0x0014 /* - | W */
137 #define ME_DAC_DATA_B 0x0016 /* - | W */
138 #define ME_DAC_DATA_C 0x0018 /* - | W */
139 #define ME_DAC_DATA_D 0x001A /* - | W */
140 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
141 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
142 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
143 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
144 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
145 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
147 static const struct comedi_lrange me2000_ai_range = {
161 static const struct comedi_lrange me2600_ai_range = {
175 static const struct comedi_lrange me2600_ao_range = {
184 /* Board specification structure */
186 const char *name; /* driver name */
188 int ao_channel_nbr; /* DA config */
190 int ao_resolution_mask;
191 const struct comedi_lrange *ao_range_list;
192 int ai_channel_nbr; /* AD config */
194 int ai_resolution_mask;
195 const struct comedi_lrange *ai_range_list;
196 int dio_channel_nbr; /* DIO config */
199 static const struct me_board me_boards[] = {
202 .name = ME_DRIVER_NAME,
203 .device_id = ME2600_DEVICE_ID,
207 .ao_resolution_mask = 0x0fff,
208 .ao_range_list = &me2600_ao_range,
209 .ai_channel_nbr = 16,
212 .ai_resolution_mask = 0x0fff,
213 .ai_range_list = &me2600_ai_range,
214 .dio_channel_nbr = 32,
218 .name = ME_DRIVER_NAME,
219 .device_id = ME2000_DEVICE_ID,
223 .ao_resolution_mask = 0,
224 .ao_range_list = NULL,
225 .ai_channel_nbr = 16,
228 .ai_resolution_mask = 0x0fff,
229 .ai_range_list = &me2000_ai_range,
230 .dio_channel_nbr = 32,
234 /* Private data structure */
235 struct me_private_data {
236 void __iomem *plx_regbase; /* PLX configuration base address */
237 void __iomem *me_regbase; /* Base address of the Meilhaus card */
238 unsigned long plx_regbase_size; /* Size of PLX configuration space */
239 unsigned long me_regbase_size; /* Size of Meilhaus space */
241 unsigned short control_1; /* Mirror of CONTROL_1 register */
242 unsigned short control_2; /* Mirror of CONTROL_2 register */
243 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
244 int ao_readback[4]; /* Mirror of analog output data */
247 #define dev_private ((struct me_private_data *)dev->private)
250 * ------------------------------------------------------------------
254 * ------------------------------------------------------------------
256 static inline void sleep(unsigned sec)
258 current->state = TASK_INTERRUPTIBLE;
259 schedule_timeout(sec * HZ);
263 * ------------------------------------------------------------------
265 * DIGITAL INPUT/OUTPUT SECTION
267 * ------------------------------------------------------------------
269 static int me_dio_insn_config(struct comedi_device *dev,
270 struct comedi_subdevice *s,
271 struct comedi_insn *insn, unsigned int *data)
274 int mask = 1 << CR_CHAN(insn->chanspec);
277 if (mask & 0x0000ffff) { /* Port A in use */
281 dev_private->control_2 |= ENABLE_PORT_A;
282 writew(dev_private->control_2,
283 dev_private->me_regbase + ME_CONTROL_2);
284 } else { /* Port B in use */
289 dev_private->control_2 |= ENABLE_PORT_B;
290 writew(dev_private->control_2,
291 dev_private->me_regbase + ME_CONTROL_2);
295 /* Config port as output */
298 /* Config port as input */
305 /* Digital instant input/outputs */
306 static int me_dio_insn_bits(struct comedi_device *dev,
307 struct comedi_subdevice *s,
308 struct comedi_insn *insn, unsigned int *data)
310 unsigned int mask = data[0];
312 s->state |= (mask & data[1]);
315 if (mask & 0x0000ffff) { /* Port A */
316 writew((s->state & 0xffff),
317 dev_private->me_regbase + ME_DIO_PORT_A);
319 data[1] &= ~0x0000ffff;
320 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
323 if (mask & 0xffff0000) { /* Port B */
324 writew(((s->state >> 16) & 0xffff),
325 dev_private->me_regbase + ME_DIO_PORT_B);
327 data[1] &= ~0xffff0000;
328 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
335 * ------------------------------------------------------------------
337 * ANALOG INPUT SECTION
339 * ------------------------------------------------------------------
342 /* Analog instant input */
343 static int me_ai_insn_read(struct comedi_device *dev,
344 struct comedi_subdevice *subdevice,
345 struct comedi_insn *insn, unsigned int *data)
347 unsigned short value;
348 int chan = CR_CHAN((&insn->chanspec)[0]);
349 int rang = CR_RANGE((&insn->chanspec)[0]);
350 int aref = CR_AREF((&insn->chanspec)[0]);
353 /* stop any running conversion */
354 dev_private->control_1 &= 0xFFFC;
355 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
357 /* clear chanlist and ad fifo */
358 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
359 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
361 /* reset any pending interrupt */
362 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
364 /* enable the chanlist and ADC fifo */
365 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
366 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
368 /* write to channel list fifo */
369 /* b3:b0 are the channel number */
371 /* b5:b4 are the channel gain */
372 value |= (rang & 0x03) << 4;
373 /* b6 channel polarity */
374 value |= (rang & 0x04) << 4;
375 /* b7 single or differential */
376 value |= ((aref & AREF_DIFF) ? 0x80 : 0);
377 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
379 /* set ADC mode to software trigger */
380 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
381 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
383 /* start conversion by reading from ADC_START */
384 readw(dev_private->me_regbase + ME_ADC_START);
386 /* wait for ADC fifo not empty flag */
387 for (i = 100000; i > 0; i--)
388 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
391 /* get value from ADC fifo */
394 (readw(dev_private->me_regbase +
395 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
397 printk(KERN_ERR "comedi%d: Cannot get single value\n",
402 /* stop any running conversion */
403 dev_private->control_1 &= 0xFFFC;
404 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
410 * ------------------------------------------------------------------
412 * HARDWARE TRIGGERED ANALOG INPUT SECTION
414 * ------------------------------------------------------------------
417 /* Cancel analog input autoscan */
418 static int me_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
420 /* disable interrupts */
422 /* stop any running conversion */
423 dev_private->control_1 &= 0xFFFC;
424 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
429 /* Test analog input command */
430 static int me_ai_do_cmd_test(struct comedi_device *dev,
431 struct comedi_subdevice *s, struct comedi_cmd *cmd)
436 /* Analog input command */
437 static int me_ai_do_cmd(struct comedi_device *dev,
438 struct comedi_subdevice *subdevice)
444 * ------------------------------------------------------------------
446 * ANALOG OUTPUT SECTION
448 * ------------------------------------------------------------------
451 /* Analog instant output */
452 static int me_ao_insn_write(struct comedi_device *dev,
453 struct comedi_subdevice *s,
454 struct comedi_insn *insn, unsigned int *data)
461 dev_private->control_2 |= ENABLE_DAC;
462 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
464 /* and set DAC to "buffered" mode */
465 dev_private->control_2 |= BUFFERED_DAC;
466 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
468 /* Set dac-control register */
469 for (i = 0; i < insn->n; i++) {
470 chan = CR_CHAN((&insn->chanspec)[i]);
471 rang = CR_RANGE((&insn->chanspec)[i]);
473 /* clear bits for this channel */
474 dev_private->dac_control &= ~(0x0880 >> chan);
476 dev_private->dac_control |=
477 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
479 dev_private->dac_control |=
480 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
482 writew(dev_private->dac_control,
483 dev_private->me_regbase + ME_DAC_CONTROL);
485 /* Update dac-control register */
486 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
488 /* Set data register */
489 for (i = 0; i < insn->n; i++) {
490 chan = CR_CHAN((&insn->chanspec)[i]);
491 writew((data[0] & s->maxdata),
492 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
493 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
496 /* Update dac with data registers */
497 readw(dev_private->me_regbase + ME_DAC_UPDATE);
502 /* Analog output readback */
503 static int me_ao_insn_read(struct comedi_device *dev,
504 struct comedi_subdevice *s, struct comedi_insn *insn,
509 for (i = 0; i < insn->n; i++) {
511 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
518 * ------------------------------------------------------------------
520 * INITIALISATION SECTION
522 * ------------------------------------------------------------------
525 /* Xilinx firmware download for card: ME-2600i */
526 static int me2600_xilinx_download(struct comedi_device *dev,
527 unsigned char *me2600_firmware,
531 unsigned int file_length;
534 /* disable irq's on PLX */
535 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
537 /* First, make a dummy read to reset xilinx */
538 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
540 /* Wait until reset is over */
543 /* Write a dummy value to Xilinx */
544 writeb(0x00, dev_private->me_regbase + 0x0);
548 * Format of the firmware
549 * Build longs from the byte-wise coded header
550 * Byte 1-3: length of the array
553 * Byte 12-15: reserved
557 file_length = (((unsigned int)me2600_firmware[0] & 0xff) << 24) +
558 (((unsigned int)me2600_firmware[1] & 0xff) << 16) +
559 (((unsigned int)me2600_firmware[2] & 0xff) << 8) +
560 ((unsigned int)me2600_firmware[3] & 0xff);
563 * Loop for writing firmware byte by byte to xilinx
564 * Firmware data start at offfset 16
566 for (i = 0; i < file_length; i++)
567 writeb((me2600_firmware[16 + i] & 0xff),
568 dev_private->me_regbase + 0x0);
570 /* Write 5 dummy values to xilinx */
571 for (i = 0; i < 5; i++)
572 writeb(0x00, dev_private->me_regbase + 0x0);
574 /* Test if there was an error during download -> INTB was thrown */
575 value = readl(dev_private->plx_regbase + PLX_INTCSR);
577 /* Disable interrupt */
578 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
579 printk(KERN_ERR "comedi%d: Xilinx download failed\n",
584 /* Wait until the Xilinx is ready for real work */
587 /* Enable PLX-Interrupts */
588 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
594 static int me_reset(struct comedi_device *dev)
597 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
598 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
599 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
600 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
602 /* Save values in the board context */
603 dev_private->dac_control = 0;
604 dev_private->control_1 = 0;
605 dev_private->control_2 = 0;
610 static struct pci_dev *me_find_pci_dev(struct comedi_device *dev,
611 struct comedi_devconfig *it)
613 const struct me_board *board;
614 struct pci_dev *pcidev = NULL;
615 int bus = it->options[0];
616 int slot = it->options[1];
619 for_each_pci_dev(pcidev) {
621 if (pcidev->bus->number != bus ||
622 PCI_SLOT(pcidev->devfn) != slot)
625 if (pcidev->vendor != PCI_VENDOR_ID_MEILHAUS)
628 for (i = 0; i < ARRAY_SIZE(me_boards); i++) {
629 board = &me_boards[i];
630 if (board->device_id != pcidev->device)
633 dev->board_ptr = board;
637 dev_err(dev->class_dev,
638 "No supported board found! (req. bus %d, slot %d)\n",
643 static int me_attach(struct comedi_device *dev, struct comedi_devconfig *it)
645 struct pci_dev *pci_device;
646 struct comedi_subdevice *subdevice;
647 struct me_board *board;
648 resource_size_t plx_regbase_tmp;
649 unsigned long plx_regbase_size_tmp;
650 resource_size_t me_regbase_tmp;
651 unsigned long me_regbase_size_tmp;
652 resource_size_t swap_regbase_tmp;
653 unsigned long swap_regbase_size_tmp;
654 resource_size_t regbase_tmp;
657 /* Allocate private memory */
658 if (alloc_private(dev, sizeof(struct me_private_data)) < 0)
661 pci_device = me_find_pci_dev(dev, it);
664 comedi_set_hw_dev(dev, &pci_device->dev);
665 board = (struct me_board *)dev->board_ptr;
667 /* Enable PCI device and request PCI regions */
668 if (comedi_pci_enable(pci_device, ME_DRIVER_NAME) < 0) {
669 printk(KERN_ERR "comedi%d: Failed to enable PCI device and "
670 "request regions\n", dev->minor);
674 /* Set data in device structure */
675 dev->board_name = board->name;
677 /* Read PLX register base address [PCI_BASE_ADDRESS #0]. */
678 plx_regbase_tmp = pci_resource_start(pci_device, 0);
679 plx_regbase_size_tmp = pci_resource_len(pci_device, 0);
680 dev_private->plx_regbase =
681 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
682 dev_private->plx_regbase_size = plx_regbase_size_tmp;
683 if (!dev_private->plx_regbase) {
684 printk("comedi%d: Failed to remap I/O memory\n", dev->minor);
688 /* Read Swap base address [PCI_BASE_ADDRESS #5]. */
690 swap_regbase_tmp = pci_resource_start(pci_device, 5);
691 swap_regbase_size_tmp = pci_resource_len(pci_device, 5);
693 if (!swap_regbase_tmp)
694 printk(KERN_ERR "comedi%d: Swap not present\n", dev->minor);
696 /*---------------------------------------------- Workaround start ---*/
697 if (plx_regbase_tmp & 0x0080) {
698 printk(KERN_ERR "comedi%d: PLX-Bug detected\n", dev->minor);
700 if (swap_regbase_tmp) {
701 regbase_tmp = plx_regbase_tmp;
702 plx_regbase_tmp = swap_regbase_tmp;
703 swap_regbase_tmp = regbase_tmp;
705 result = pci_write_config_dword(pci_device,
708 if (result != PCIBIOS_SUCCESSFUL)
711 result = pci_write_config_dword(pci_device,
714 if (result != PCIBIOS_SUCCESSFUL)
717 plx_regbase_tmp -= 0x80;
718 result = pci_write_config_dword(pci_device,
721 if (result != PCIBIOS_SUCCESSFUL)
725 /*--------------------------------------------- Workaround end -----*/
727 /* Read Meilhaus register base address [PCI_BASE_ADDRESS #2]. */
729 me_regbase_tmp = pci_resource_start(pci_device, 2);
730 me_regbase_size_tmp = pci_resource_len(pci_device, 2);
731 dev_private->me_regbase_size = me_regbase_size_tmp;
732 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
733 if (!dev_private->me_regbase) {
734 printk(KERN_ERR "comedi%d: Failed to remap I/O memory\n",
738 /* Download firmware and reset card */
739 if (board->device_id == ME2600_DEVICE_ID) {
740 unsigned char *aux_data;
743 aux_data = comedi_aux_data(it->options, 0);
744 aux_len = it->options[COMEDI_DEVCONF_AUX_DATA_LENGTH];
746 if (!aux_data || aux_len < 1) {
747 comedi_error(dev, "You must provide me2600 firmware "
748 "using the --init-data option of "
752 me2600_xilinx_download(dev, aux_data, aux_len);
757 error = comedi_alloc_subdevices(dev, 3);
761 subdevice = dev->subdevices + 0;
762 subdevice->type = COMEDI_SUBD_AI;
763 subdevice->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
764 subdevice->n_chan = board->ai_channel_nbr;
765 subdevice->maxdata = board->ai_resolution_mask;
766 subdevice->len_chanlist = board->ai_channel_nbr;
767 subdevice->range_table = board->ai_range_list;
768 subdevice->cancel = me_ai_cancel;
769 subdevice->insn_read = me_ai_insn_read;
770 subdevice->do_cmdtest = me_ai_do_cmd_test;
771 subdevice->do_cmd = me_ai_do_cmd;
773 subdevice = dev->subdevices + 1;
774 subdevice->type = COMEDI_SUBD_AO;
775 subdevice->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
776 subdevice->n_chan = board->ao_channel_nbr;
777 subdevice->maxdata = board->ao_resolution_mask;
778 subdevice->len_chanlist = board->ao_channel_nbr;
779 subdevice->range_table = board->ao_range_list;
780 subdevice->insn_read = me_ao_insn_read;
781 subdevice->insn_write = me_ao_insn_write;
783 subdevice = dev->subdevices + 2;
784 subdevice->type = COMEDI_SUBD_DIO;
785 subdevice->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
786 subdevice->n_chan = board->dio_channel_nbr;
787 subdevice->maxdata = 1;
788 subdevice->len_chanlist = board->dio_channel_nbr;
789 subdevice->range_table = &range_digital;
790 subdevice->insn_bits = me_dio_insn_bits;
791 subdevice->insn_config = me_dio_insn_config;
792 subdevice->io_bits = 0;
794 printk(KERN_INFO "comedi%d: " ME_DRIVER_NAME " attached.\n",
799 static void me_detach(struct comedi_device *dev)
801 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
804 if (dev_private->me_regbase) {
806 iounmap(dev_private->me_regbase);
808 if (dev_private->plx_regbase)
809 iounmap(dev_private->plx_regbase);
812 if (dev_private->plx_regbase_size)
813 comedi_pci_disable(pcidev);
818 static struct comedi_driver me_daq_driver = {
819 .driver_name = "me_daq",
820 .module = THIS_MODULE,
825 static int __devinit me_daq_pci_probe(struct pci_dev *dev,
826 const struct pci_device_id *ent)
828 return comedi_pci_auto_config(dev, &me_daq_driver);
831 static void __devexit me_daq_pci_remove(struct pci_dev *dev)
833 comedi_pci_auto_unconfig(dev);
836 static DEFINE_PCI_DEVICE_TABLE(me_daq_pci_table) = {
837 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID) },
838 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID) },
841 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
843 static struct pci_driver me_daq_pci_driver = {
845 .id_table = me_daq_pci_table,
846 .probe = me_daq_pci_probe,
847 .remove = __devexit_p(me_daq_pci_remove),
849 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
851 MODULE_AUTHOR("Comedi http://www.comedi.org");
852 MODULE_DESCRIPTION("Comedi low-level driver");
853 MODULE_LICENSE("GPL");