drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31
  32     You should have received a copy of the GNU General Public License
  33     along with this program; if not, write to the Free Software
  34     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35
  36 ************************************************************************/
  37
  38 /*
  39  * Driver: cb_pcidas64
  40  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  41  *   with the PLX 9080 PCI controller
  42  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  43  * Status: works
  44  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  45  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  46  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  47  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  48  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  49  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  50  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  51  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  52  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  53  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  54  *
  55  * Configuration options:
  56  *   None.
  57  *
  58  * Manual attachment of PCI cards with the comedi_config utility is not
  59  * supported by this driver; they are attached automatically.
  60  *
  61  * These boards may be autocalibrated with the comedi_calibrate utility.
  62  *
  63  * To select the bnc trigger input on the 4020 (instead of the dio input),
  64  * specify a nonzero channel in the chanspec.  If you wish to use an external
  65  * master clock on the 4020, you may do so by setting the scan_begin_src
  66  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  67  * to configure the divisor to use for the external clock.
  68  *
  69  * Some devices are not identified because the PCI device IDs are not yet
  70  * known. If you have such a board, please let the maintainers know.
  71  */
  72
  73 /*
  74
  75 TODO:
  76         make it return error if user attempts an ai command that uses the
  77         external queue, and an ao command simultaneously user counter subdevice
  78         there are a number of boards this driver will support when they are
  79         fully released, but does not yet since the pci device id numbers
  80         are not yet available.
  81
  82         support prescaled 100khz clock for slow pacing (not available on 6000
  83         series?)
  84
  85         make ao fifo size adjustable like ai fifo
  86 */
  87
  88 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  89
  90 #include "../comedidev.h"
  91 #include <linux/delay.h>
  92 #include <linux/interrupt.h>
  93
  94 #include "8253.h"
  95 #include "8255.h"
  96 #include "plx9080.h"
  97 #include "comedi_fc.h"
  98
  99 #undef PCIDAS64_DEBUG           /*  disable debugging code */
 100 /* #define PCIDAS64_DEBUG         enable debugging code */
 101
 102 #ifdef PCIDAS64_DEBUG
 103 #define DEBUG_PRINT(format, args...)  pr_debug(format, ## args)
 104 #else
 105 #define DEBUG_PRINT(format, args...)  no_printk(format, ## args)
 106 #endif
 107
 108 #define TIMER_BASE 25           /*  40MHz master clock */
 109 /* 100kHz 'prescaled' clock for slow acquisition,
 110  * maybe I'll support this someday */
 111 #define PRESCALED_TIMER_BASE    10000
 112 #define DMA_BUFFER_SIZE 0x1000
 113
 114 /* maximum value that can be loaded into board's 24-bit counters*/
 115 static const int max_counter_value = 0xffffff;
 116
 117 /* PCI-DAS64xxx base addresses */
 118
 119 /* indices of base address regions */
 120 enum base_address_regions {
 121         PLX9080_BADDRINDEX = 0,
 122         MAIN_BADDRINDEX = 2,
 123         DIO_COUNTER_BADDRINDEX = 3,
 124 };
 125
 126 /* devpriv->main_iobase registers */
 127 enum write_only_registers {
 128         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 129         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 130         DAQ_SYNC_REG = 0xc,
 131         DAQ_ATRIG_LOW_4020_REG = 0xc,
 132         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 133         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 134         CALIBRATION_REG = 0x14,
 135         /*  lower 16 bits of adc sample interval counter */
 136         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 137         /*  upper 8 bits of adc sample interval counter */
 138         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 139         /*  lower 16 bits of delay interval counter */
 140         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 141         /*  upper 8 bits of delay interval counter */
 142         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 143         /*  lower 16 bits of hardware conversion/scan counter */
 144         ADC_COUNT_LOWER_REG = 0x1e,
 145         /*  upper 8 bits of hardware conversion/scan counter */
 146         ADC_COUNT_UPPER_REG = 0x20,
 147         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 148         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 149         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 150         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 151         ADC_BUFFER_CLEAR_REG = 0x2a,
 152         /*  high channel for internal queue, use adc_chan_bits() inline above */
 153         ADC_QUEUE_HIGH_REG = 0x2c,
 154         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 155         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 156         /*  lower 16 bits of dac sample interval counter */
 157         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 158         /*  upper 8 bits of dac sample interval counter */
 159         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 160         DAC_SELECT_REG = 0x60,
 161         DAC_START_REG = 0x64,
 162         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 163 };
 164
 165 static inline unsigned int dac_convert_reg(unsigned int channel)
 166 {
 167         return 0x70 + (2 * (channel & 0x1));
 168 }
 169
 170 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 171 {
 172         return 0x70 + (4 * (channel & 0x1));
 173 }
 174
 175 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 176 {
 177         return 0x72 + (4 * (channel & 0x1));
 178 }
 179
 180 enum read_only_registers {
 181         /*  hardware status register,
 182          *  reading this apparently clears pending interrupts as well */
 183         HW_STATUS_REG = 0x0,
 184         PIPE1_READ_REG = 0x4,
 185         ADC_READ_PNTR_REG = 0x8,
 186         LOWER_XFER_REG = 0x10,
 187         ADC_WRITE_PNTR_REG = 0xc,
 188         PREPOST_REG = 0x14,
 189 };
 190
 191 enum read_write_registers {
 192         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 193         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 194         ADC_QUEUE_FIFO_REG = 0x100,
 195         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 196         /* dac data fifo, has weird interactions with external channel queue */
 197         DAC_FIFO_REG = 0x300,
 198 };
 199
 200 /* devpriv->dio_counter_iobase registers */
 201 enum dio_counter_registers {
 202         DIO_8255_OFFSET = 0x0,
 203         DO_REG = 0x20,
 204         DI_REG = 0x28,
 205         DIO_DIRECTION_60XX_REG = 0x40,
 206         DIO_DATA_60XX_REG = 0x48,
 207 };
 208
 209 /* bit definitions for write-only registers */
 210
 211 enum intr_enable_contents {
 212         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 213         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 214         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 215         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 216         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 217         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 218         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 219         DAC_INTR_SRC_MASK = 0x30,
 220         DAC_INTR_QEMPTY_BITS = 0x0,
 221         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 222         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 223         EN_DAC_DONE_INTR_BIT = 0x80,
 224         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 225         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 226         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 227         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 228         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 229 };
 230
 231 enum hw_config_contents {
 232         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 233         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 234         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 235         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 236         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 237         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 238         SLOW_DAC_BIT = 0x400,
 239         /*  bit with unknown function yet given as default value in pci-das64
 240          *  manual */
 241         HW_CONFIG_DUMMY_BITS = 0x2000,
 242         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 243         DMA_CH_SELECT_BIT = 0x8000,
 244         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 245         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 246         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 247 };
 248 #define DAC_FIFO_SIZE 0x2000
 249
 250 enum daq_atrig_low_4020_contents {
 251         /*  use trig/ext clk bnc input for analog gate signal */
 252         EXT_AGATE_BNC_BIT = 0x8000,
 253         /*  use trig/ext clk bnc input for external stop trigger signal */
 254         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 255         /*  use trig/ext clk bnc input for external start trigger signal */
 256         EXT_START_TRIG_BNC_BIT = 0x2000,
 257 };
 258
 259 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 260 {
 261         return threshold & 0xfff;
 262 }
 263
 264 enum adc_control0_contents {
 265         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 266         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 267         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 268         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 269         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 270         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 271         ADC_START_TRIG_SOFT_BITS = 0x10,
 272         ADC_START_TRIG_EXT_BITS = 0x20,
 273         ADC_START_TRIG_ANALOG_BITS = 0x30,
 274         ADC_START_TRIG_MASK = 0x30,
 275         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 276         /*  external pacing uses falling edge */
 277         ADC_EXT_CONV_FALLING_BIT = 0x800,
 278         /*  enable hardware scan counter */
 279         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 280         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 281         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 282 };
 283
 284 enum adc_control1_contents {
 285         /*  should be set for boards with > 16 channels */
 286         ADC_QUEUE_CONFIG_BIT = 0x1,
 287         CONVERT_POLARITY_BIT = 0x10,
 288         EOC_POLARITY_BIT = 0x20,
 289         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 290         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 291         RETRIGGER_BIT = 0x800,
 292         ADC_LO_CHANNEL_4020_MASK = 0x300,
 293         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 294         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 295         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 296         CHANNEL_MODE_4020_MASK = 0x3000,
 297         ADC_MODE_MASK = 0xf000,
 298 };
 299
 300 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 301 {
 302         return (channel & 0x3) << 8;
 303 };
 304
 305 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 306 {
 307         return (channel & 0x3) << 10;
 308 };
 309
 310 static inline uint16_t adc_mode_bits(unsigned int mode)
 311 {
 312         return (mode & 0xf) << 12;
 313 };
 314
 315 enum calibration_contents {
 316         SELECT_8800_BIT = 0x1,
 317         SELECT_8402_64XX_BIT = 0x2,
 318         SELECT_1590_60XX_BIT = 0x2,
 319         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 320         SERIAL_DATA_IN_BIT = 0x80,
 321         SERIAL_CLOCK_BIT = 0x100,
 322         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 323         CAL_GAIN_BIT = 0x800,
 324 };
 325
 326 /* calibration sources for 6025 are:
 327  *  0 : ground
 328  *  1 : 10V
 329  *  2 : 5V
 330  *  3 : 0.5V
 331  *  4 : 0.05V
 332  *  5 : ground
 333  *  6 : dac channel 0
 334  *  7 : dac channel 1
 335  */
 336
 337 static inline uint16_t adc_src_bits(unsigned int source)
 338 {
 339         return (source & 0xf) << 3;
 340 };
 341
 342 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 343 {
 344         return (channel & 0x3) << 8;
 345 };
 346
 347 enum adc_queue_load_contents {
 348         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 349         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 350         /*  non-referenced single-ended (common-mode input) */
 351         ADC_COMMON_BIT = 0x2000,
 352         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 353         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 354 };
 355
 356 static inline uint16_t adc_chan_bits(unsigned int channel)
 357 {
 358         return channel & 0x3f;
 359 };
 360
 361 enum dac_control0_contents {
 362         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 363         DAC_CYCLIC_STOP_BIT = 0x4000,
 364         DAC_WAVEFORM_MODE_BIT = 0x100,
 365         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 366         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 367         WAVEFORM_TRIG_MASK = 0x30,
 368         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 369         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 370         WAVEFORM_TRIG_EXT_BITS = 0x20,
 371         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 372         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 373         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 374         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 375         WAVEFORM_GATE_SELECT_BIT = 0x1,
 376 };
 377
 378 enum dac_control1_contents {
 379         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 380         DAC1_EXT_REF_BIT = 0x200,
 381         DAC0_EXT_REF_BIT = 0x100,
 382         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 383         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 384         DAC_SW_GATE_BIT = 0x20,
 385         DAC1_UNIPOLAR_BIT = 0x8,
 386         DAC0_UNIPOLAR_BIT = 0x2,
 387 };
 388
 389 /* bit definitions for read-only registers */
 390 enum hw_status_contents {
 391         DAC_UNDERRUN_BIT = 0x1,
 392         ADC_OVERRUN_BIT = 0x2,
 393         DAC_ACTIVE_BIT = 0x4,
 394         ADC_ACTIVE_BIT = 0x8,
 395         DAC_INTR_PENDING_BIT = 0x10,
 396         ADC_INTR_PENDING_BIT = 0x20,
 397         DAC_DONE_BIT = 0x40,
 398         ADC_DONE_BIT = 0x80,
 399         EXT_INTR_PENDING_BIT = 0x100,
 400         ADC_STOP_BIT = 0x200,
 401 };
 402
 403 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 404 {
 405         return (hw_status_bits >> 10) & 0x3;
 406 };
 407
 408 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 409 {
 410         return (prepost_bits >> 6) & 0x3;
 411 }
 412
 413 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 414 {
 415         return (prepost_bits >> 12) & 0x3;
 416 }
 417
 418 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 419 {
 420         return (prepost_bits >> 14) & 0x3;
 421 }
 422
 423 /* I2C addresses for 4020 */
 424 enum i2c_addresses {
 425         RANGE_CAL_I2C_ADDR = 0x20,
 426         CALDAC0_I2C_ADDR = 0xc,
 427         CALDAC1_I2C_ADDR = 0xd,
 428 };
 429
 430 enum range_cal_i2c_contents {
 431         /*  bits that set what source the adc converter measures */
 432         ADC_SRC_4020_MASK = 0x70,
 433         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 434         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 435 };
 436
 437 static inline uint8_t adc_src_4020_bits(unsigned int source)
 438 {
 439         return (source << 4) & ADC_SRC_4020_MASK;
 440 };
 441
 442 static inline uint8_t attenuate_bit(unsigned int channel)
 443 {
 444         /*  attenuate channel (+-5V input range) */
 445         return 1 << (channel & 0x3);
 446 };
 447
 448 /* analog input ranges for 64xx boards */
 449 static const struct comedi_lrange ai_ranges_64xx = {
 450         8,
 451         {
 452          BIP_RANGE(10),
 453          BIP_RANGE(5),
 454          BIP_RANGE(2.5),
 455          BIP_RANGE(1.25),
 456          UNI_RANGE(10),
 457          UNI_RANGE(5),
 458          UNI_RANGE(2.5),
 459          UNI_RANGE(1.25)
 460          }
 461 };
 462
 463 /* analog input ranges for 60xx boards */
 464 static const struct comedi_lrange ai_ranges_60xx = {
 465         4,
 466         {
 467          BIP_RANGE(10),
 468          BIP_RANGE(5),
 469          BIP_RANGE(0.5),
 470          BIP_RANGE(0.05),
 471          }
 472 };
 473
 474 /* analog input ranges for 6030, etc boards */
 475 static const struct comedi_lrange ai_ranges_6030 = {
 476         14,
 477         {
 478          BIP_RANGE(10),
 479          BIP_RANGE(5),
 480          BIP_RANGE(2),
 481          BIP_RANGE(1),
 482          BIP_RANGE(0.5),
 483          BIP_RANGE(0.2),
 484          BIP_RANGE(0.1),
 485          UNI_RANGE(10),
 486          UNI_RANGE(5),
 487          UNI_RANGE(2),
 488          UNI_RANGE(1),
 489          UNI_RANGE(0.5),
 490          UNI_RANGE(0.2),
 491          UNI_RANGE(0.1),
 492          }
 493 };
 494
 495 /* analog input ranges for 6052, etc boards */
 496 static const struct comedi_lrange ai_ranges_6052 = {
 497         15,
 498         {
 499          BIP_RANGE(10),
 500          BIP_RANGE(5),
 501          BIP_RANGE(2.5),
 502          BIP_RANGE(1),
 503          BIP_RANGE(0.5),
 504          BIP_RANGE(0.25),
 505          BIP_RANGE(0.1),
 506          BIP_RANGE(0.05),
 507          UNI_RANGE(10),
 508          UNI_RANGE(5),
 509          UNI_RANGE(2),
 510          UNI_RANGE(1),
 511          UNI_RANGE(0.5),
 512          UNI_RANGE(0.2),
 513          UNI_RANGE(0.1),
 514          }
 515 };
 516
 517 /* analog input ranges for 4020 board */
 518 static const struct comedi_lrange ai_ranges_4020 = {
 519         2,
 520         {
 521          BIP_RANGE(5),
 522          BIP_RANGE(1),
 523          }
 524 };
 525
 526 /* analog output ranges */
 527 static const struct comedi_lrange ao_ranges_64xx = {
 528         4,
 529         {
 530          BIP_RANGE(5),
 531          BIP_RANGE(10),
 532          UNI_RANGE(5),
 533          UNI_RANGE(10),
 534          }
 535 };
 536
 537 static const int ao_range_code_64xx[] = {
 538         0x0,
 539         0x1,
 540         0x2,
 541         0x3,
 542 };
 543
 544 static const struct comedi_lrange ao_ranges_60xx = {
 545         1,
 546         {
 547          BIP_RANGE(10),
 548          }
 549 };
 550
 551 static const int ao_range_code_60xx[] = {
 552         0x0,
 553 };
 554
 555 static const struct comedi_lrange ao_ranges_6030 = {
 556         2,
 557         {
 558          BIP_RANGE(10),
 559          UNI_RANGE(10),
 560          }
 561 };
 562
 563 static const int ao_range_code_6030[] = {
 564         0x0,
 565         0x2,
 566 };
 567
 568 static const struct comedi_lrange ao_ranges_4020 = {
 569         2,
 570         {
 571          BIP_RANGE(5),
 572          BIP_RANGE(10),
 573          }
 574 };
 575
 576 static const int ao_range_code_4020[] = {
 577         0x1,
 578         0x0,
 579 };
 580
 581 enum register_layout {
 582         LAYOUT_60XX,
 583         LAYOUT_64XX,
 584         LAYOUT_4020,
 585 };
 586
 587 struct hw_fifo_info {
 588         unsigned int num_segments;
 589         unsigned int max_segment_length;
 590         unsigned int sample_packing_ratio;
 591         uint16_t fifo_size_reg_mask;
 592 };
 593
 594 struct pcidas64_board {
 595         const char *name;
 596         int device_id;          /*  pci device id */
 597         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 598         int ai_bits;            /*  analog input resolution */
 599         int ai_speed;           /*  fastest conversion period in ns */
 600         const struct comedi_lrange *ai_range_table;
 601         int ao_nchan;           /*  number of analog out channels */
 602         int ao_bits;            /*  analog output resolution */
 603         int ao_scan_speed;      /*  analog output scan speed */
 604         const struct comedi_lrange *ao_range_table;
 605         const int *ao_range_code;
 606         const struct hw_fifo_info *const ai_fifo;
 607         /*  different board families have slightly different registers */
 608         enum register_layout layout;
 609         unsigned has_8255:1;
 610 };
 611
 612 static const struct hw_fifo_info ai_fifo_4020 = {
 613         .num_segments = 2,
 614         .max_segment_length = 0x8000,
 615         .sample_packing_ratio = 2,
 616         .fifo_size_reg_mask = 0x7f,
 617 };
 618
 619 static const struct hw_fifo_info ai_fifo_64xx = {
 620         .num_segments = 4,
 621         .max_segment_length = 0x800,
 622         .sample_packing_ratio = 1,
 623         .fifo_size_reg_mask = 0x3f,
 624 };
 625
 626 static const struct hw_fifo_info ai_fifo_60xx = {
 627         .num_segments = 4,
 628         .max_segment_length = 0x800,
 629         .sample_packing_ratio = 1,
 630         .fifo_size_reg_mask = 0x7f,
 631 };
 632
 633 /* maximum number of dma transfers we will chain together into a ring
 634  * (and the maximum number of dma buffers we maintain) */
 635 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 636 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 637 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 638 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 639 {
 640         if (board->layout == LAYOUT_4020)
 641                 return MAX_AI_DMA_RING_COUNT;
 642         else
 643                 return MIN_AI_DMA_RING_COUNT;
 644 }
 645
 646 static const int bytes_in_sample = 2;
 647
 648 static const struct pcidas64_board pcidas64_boards[] = {
 649         {
 650          .name = "pci-das6402/16",
 651          .device_id = 0x1d,
 652          .ai_se_chans = 64,
 653          .ai_bits = 16,
 654          .ai_speed = 5000,
 655          .ao_nchan = 2,
 656          .ao_bits = 16,
 657          .ao_scan_speed = 10000,
 658          .layout = LAYOUT_64XX,
 659          .ai_range_table = &ai_ranges_64xx,
 660          .ao_range_table = &ao_ranges_64xx,
 661          .ao_range_code = ao_range_code_64xx,
 662          .ai_fifo = &ai_fifo_64xx,
 663          .has_8255 = 1,
 664          },
 665         {
 666          .name = "pci-das6402/12",      /*  XXX check */
 667          .device_id = 0x1e,
 668          .ai_se_chans = 64,
 669          .ai_bits = 12,
 670          .ai_speed = 5000,
 671          .ao_nchan = 2,
 672          .ao_bits = 12,
 673          .ao_scan_speed = 10000,
 674          .layout = LAYOUT_64XX,
 675          .ai_range_table = &ai_ranges_64xx,
 676          .ao_range_table = &ao_ranges_64xx,
 677          .ao_range_code = ao_range_code_64xx,
 678          .ai_fifo = &ai_fifo_64xx,
 679          .has_8255 = 1,
 680          },
 681         {
 682          .name = "pci-das64/m1/16",
 683          .device_id = 0x35,
 684          .ai_se_chans = 64,
 685          .ai_bits = 16,
 686          .ai_speed = 1000,
 687          .ao_nchan = 2,
 688          .ao_bits = 16,
 689          .ao_scan_speed = 10000,
 690          .layout = LAYOUT_64XX,
 691          .ai_range_table = &ai_ranges_64xx,
 692          .ao_range_table = &ao_ranges_64xx,
 693          .ao_range_code = ao_range_code_64xx,
 694          .ai_fifo = &ai_fifo_64xx,
 695          .has_8255 = 1,
 696          },
 697         {
 698          .name = "pci-das64/m2/16",
 699          .device_id = 0x36,
 700          .ai_se_chans = 64,
 701          .ai_bits = 16,
 702          .ai_speed = 500,
 703          .ao_nchan = 2,
 704          .ao_bits = 16,
 705          .ao_scan_speed = 10000,
 706          .layout = LAYOUT_64XX,
 707          .ai_range_table = &ai_ranges_64xx,
 708          .ao_range_table = &ao_ranges_64xx,
 709          .ao_range_code = ao_range_code_64xx,
 710          .ai_fifo = &ai_fifo_64xx,
 711          .has_8255 = 1,
 712          },
 713         {
 714          .name = "pci-das64/m3/16",
 715          .device_id = 0x37,
 716          .ai_se_chans = 64,
 717          .ai_bits = 16,
 718          .ai_speed = 333,
 719          .ao_nchan = 2,
 720          .ao_bits = 16,
 721          .ao_scan_speed = 10000,
 722          .layout = LAYOUT_64XX,
 723          .ai_range_table = &ai_ranges_64xx,
 724          .ao_range_table = &ao_ranges_64xx,
 725          .ao_range_code = ao_range_code_64xx,
 726          .ai_fifo = &ai_fifo_64xx,
 727          .has_8255 = 1,
 728          },
 729         {
 730          .name = "pci-das6013",
 731          .device_id = 0x78,
 732          .ai_se_chans = 16,
 733          .ai_bits = 16,
 734          .ai_speed = 5000,
 735          .ao_nchan = 0,
 736          .ao_bits = 16,
 737          .layout = LAYOUT_60XX,
 738          .ai_range_table = &ai_ranges_60xx,
 739          .ao_range_table = &ao_ranges_60xx,
 740          .ao_range_code = ao_range_code_60xx,
 741          .ai_fifo = &ai_fifo_60xx,
 742          .has_8255 = 0,
 743          },
 744         {
 745          .name = "pci-das6014",
 746          .device_id = 0x79,
 747          .ai_se_chans = 16,
 748          .ai_bits = 16,
 749          .ai_speed = 5000,
 750          .ao_nchan = 2,
 751          .ao_bits = 16,
 752          .ao_scan_speed = 100000,
 753          .layout = LAYOUT_60XX,
 754          .ai_range_table = &ai_ranges_60xx,
 755          .ao_range_table = &ao_ranges_60xx,
 756          .ao_range_code = ao_range_code_60xx,
 757          .ai_fifo = &ai_fifo_60xx,
 758          .has_8255 = 0,
 759          },
 760         {
 761          .name = "pci-das6023",
 762          .device_id = 0x5d,
 763          .ai_se_chans = 16,
 764          .ai_bits = 12,
 765          .ai_speed = 5000,
 766          .ao_nchan = 0,
 767          .ao_scan_speed = 100000,
 768          .layout = LAYOUT_60XX,
 769          .ai_range_table = &ai_ranges_60xx,
 770          .ao_range_table = &ao_ranges_60xx,
 771          .ao_range_code = ao_range_code_60xx,
 772          .ai_fifo = &ai_fifo_60xx,
 773          .has_8255 = 1,
 774          },
 775         {
 776          .name = "pci-das6025",
 777          .device_id = 0x5e,
 778          .ai_se_chans = 16,
 779          .ai_bits = 12,
 780          .ai_speed = 5000,
 781          .ao_nchan = 2,
 782          .ao_bits = 12,
 783          .ao_scan_speed = 100000,
 784          .layout = LAYOUT_60XX,
 785          .ai_range_table = &ai_ranges_60xx,
 786          .ao_range_table = &ao_ranges_60xx,
 787          .ao_range_code = ao_range_code_60xx,
 788          .ai_fifo = &ai_fifo_60xx,
 789          .has_8255 = 1,
 790          },
 791         {
 792          .name = "pci-das6030",
 793          .device_id = 0x5f,
 794          .ai_se_chans = 16,
 795          .ai_bits = 16,
 796          .ai_speed = 10000,
 797          .ao_nchan = 2,
 798          .ao_bits = 16,
 799          .ao_scan_speed = 10000,
 800          .layout = LAYOUT_60XX,
 801          .ai_range_table = &ai_ranges_6030,
 802          .ao_range_table = &ao_ranges_6030,
 803          .ao_range_code = ao_range_code_6030,
 804          .ai_fifo = &ai_fifo_60xx,
 805          .has_8255 = 0,
 806          },
 807         {
 808          .name = "pci-das6031",
 809          .device_id = 0x60,
 810          .ai_se_chans = 64,
 811          .ai_bits = 16,
 812          .ai_speed = 10000,
 813          .ao_nchan = 2,
 814          .ao_bits = 16,
 815          .ao_scan_speed = 10000,
 816          .layout = LAYOUT_60XX,
 817          .ai_range_table = &ai_ranges_6030,
 818          .ao_range_table = &ao_ranges_6030,
 819          .ao_range_code = ao_range_code_6030,
 820          .ai_fifo = &ai_fifo_60xx,
 821          .has_8255 = 0,
 822          },
 823         {
 824          .name = "pci-das6032",
 825          .device_id = 0x61,
 826          .ai_se_chans = 16,
 827          .ai_bits = 16,
 828          .ai_speed = 10000,
 829          .ao_nchan = 0,
 830          .layout = LAYOUT_60XX,
 831          .ai_range_table = &ai_ranges_6030,
 832          .ai_fifo = &ai_fifo_60xx,
 833          .has_8255 = 0,
 834          },
 835         {
 836          .name = "pci-das6033",
 837          .device_id = 0x62,
 838          .ai_se_chans = 64,
 839          .ai_bits = 16,
 840          .ai_speed = 10000,
 841          .ao_nchan = 0,
 842          .layout = LAYOUT_60XX,
 843          .ai_range_table = &ai_ranges_6030,
 844          .ai_fifo = &ai_fifo_60xx,
 845          .has_8255 = 0,
 846          },
 847         {
 848          .name = "pci-das6034",
 849          .device_id = 0x63,
 850          .ai_se_chans = 16,
 851          .ai_bits = 16,
 852          .ai_speed = 5000,
 853          .ao_nchan = 0,
 854          .ao_scan_speed = 0,
 855          .layout = LAYOUT_60XX,
 856          .ai_range_table = &ai_ranges_60xx,
 857          .ai_fifo = &ai_fifo_60xx,
 858          .has_8255 = 0,
 859          },
 860         {
 861          .name = "pci-das6035",
 862          .device_id = 0x64,
 863          .ai_se_chans = 16,
 864          .ai_bits = 16,
 865          .ai_speed = 5000,
 866          .ao_nchan = 2,
 867          .ao_bits = 12,
 868          .ao_scan_speed = 100000,
 869          .layout = LAYOUT_60XX,
 870          .ai_range_table = &ai_ranges_60xx,
 871          .ao_range_table = &ao_ranges_60xx,
 872          .ao_range_code = ao_range_code_60xx,
 873          .ai_fifo = &ai_fifo_60xx,
 874          .has_8255 = 0,
 875          },
 876         {
 877          .name = "pci-das6036",
 878          .device_id = 0x6f,
 879          .ai_se_chans = 16,
 880          .ai_bits = 16,
 881          .ai_speed = 5000,
 882          .ao_nchan = 2,
 883          .ao_bits = 16,
 884          .ao_scan_speed = 100000,
 885          .layout = LAYOUT_60XX,
 886          .ai_range_table = &ai_ranges_60xx,
 887          .ao_range_table = &ao_ranges_60xx,
 888          .ao_range_code = ao_range_code_60xx,
 889          .ai_fifo = &ai_fifo_60xx,
 890          .has_8255 = 0,
 891          },
 892         {
 893          .name = "pci-das6040",
 894          .device_id = 0x65,
 895          .ai_se_chans = 16,
 896          .ai_bits = 12,
 897          .ai_speed = 2000,
 898          .ao_nchan = 2,
 899          .ao_bits = 12,
 900          .ao_scan_speed = 1000,
 901          .layout = LAYOUT_60XX,
 902          .ai_range_table = &ai_ranges_6052,
 903          .ao_range_table = &ao_ranges_6030,
 904          .ao_range_code = ao_range_code_6030,
 905          .ai_fifo = &ai_fifo_60xx,
 906          .has_8255 = 0,
 907          },
 908         {
 909          .name = "pci-das6052",
 910          .device_id = 0x66,
 911          .ai_se_chans = 16,
 912          .ai_bits = 16,
 913          .ai_speed = 3333,
 914          .ao_nchan = 2,
 915          .ao_bits = 16,
 916          .ao_scan_speed = 3333,
 917          .layout = LAYOUT_60XX,
 918          .ai_range_table = &ai_ranges_6052,
 919          .ao_range_table = &ao_ranges_6030,
 920          .ao_range_code = ao_range_code_6030,
 921          .ai_fifo = &ai_fifo_60xx,
 922          .has_8255 = 0,
 923          },
 924         {
 925          .name = "pci-das6070",
 926          .device_id = 0x67,
 927          .ai_se_chans = 16,
 928          .ai_bits = 12,
 929          .ai_speed = 800,
 930          .ao_nchan = 2,
 931          .ao_bits = 12,
 932          .ao_scan_speed = 1000,
 933          .layout = LAYOUT_60XX,
 934          .ai_range_table = &ai_ranges_6052,
 935          .ao_range_table = &ao_ranges_6030,
 936          .ao_range_code = ao_range_code_6030,
 937          .ai_fifo = &ai_fifo_60xx,
 938          .has_8255 = 0,
 939          },
 940         {
 941          .name = "pci-das6071",
 942          .device_id = 0x68,
 943          .ai_se_chans = 64,
 944          .ai_bits = 12,
 945          .ai_speed = 800,
 946          .ao_nchan = 2,
 947          .ao_bits = 12,
 948          .ao_scan_speed = 1000,
 949          .layout = LAYOUT_60XX,
 950          .ai_range_table = &ai_ranges_6052,
 951          .ao_range_table = &ao_ranges_6030,
 952          .ao_range_code = ao_range_code_6030,
 953          .ai_fifo = &ai_fifo_60xx,
 954          .has_8255 = 0,
 955          },
 956         {
 957          .name = "pci-das4020/12",
 958          .device_id = 0x52,
 959          .ai_se_chans = 4,
 960          .ai_bits = 12,
 961          .ai_speed = 50,
 962          .ao_bits = 12,
 963          .ao_nchan = 2,
 964          .ao_scan_speed = 0,    /*  no hardware pacing on ao */
 965          .layout = LAYOUT_4020,
 966          .ai_range_table = &ai_ranges_4020,
 967          .ao_range_table = &ao_ranges_4020,
 968          .ao_range_code = ao_range_code_4020,
 969          .ai_fifo = &ai_fifo_4020,
 970          .has_8255 = 1,
 971          },
 972 #if 0
 973         {
 974          .name = "pci-das6402/16/jr",
 975          .device_id = 0         /*  XXX, */
 976          .ai_se_chans = 64,
 977          .ai_bits = 16,
 978          .ai_speed = 5000,
 979          .ao_nchan = 0,
 980          .ao_scan_speed = 10000,
 981          .layout = LAYOUT_64XX,
 982          .ai_range_table = &ai_ranges_64xx,
 983          .ai_fifo = ai_fifo_64xx,
 984          .has_8255 = 1,
 985          },
 986         {
 987          .name = "pci-das64/m1/16/jr",
 988          .device_id = 0         /*  XXX, */
 989          .ai_se_chans = 64,
 990          .ai_bits = 16,
 991          .ai_speed = 1000,
 992          .ao_nchan = 0,
 993          .ao_scan_speed = 10000,
 994          .layout = LAYOUT_64XX,
 995          .ai_range_table = &ai_ranges_64xx,
 996          .ai_fifo = ai_fifo_64xx,
 997          .has_8255 = 1,
 998          },
 999         {
1000          .name = "pci-das64/m2/16/jr",
1001          .device_id = 0         /*  XXX, */
1002          .ai_se_chans = 64,
1003          .ai_bits = 16,
1004          .ai_speed = 500,
1005          .ao_nchan = 0,
1006          .ao_scan_speed = 10000,
1007          .layout = LAYOUT_64XX,
1008          .ai_range_table = &ai_ranges_64xx,
1009          .ai_fifo = ai_fifo_64xx,
1010          .has_8255 = 1,
1011          },
1012         {
1013          .name = "pci-das64/m3/16/jr",
1014          .device_id = 0         /*  XXX, */
1015          .ai_se_chans = 64,
1016          .ai_bits = 16,
1017          .ai_speed = 333,
1018          .ao_nchan = 0,
1019          .ao_scan_speed = 10000,
1020          .layout = LAYOUT_64XX,
1021          .ai_range_table = &ai_ranges_64xx,
1022          .ai_fifo = ai_fifo_64xx,
1023          .has_8255 = 1,
1024          },
1025         {
1026          .name = "pci-das64/m1/14",
1027          .device_id = 0,        /*  XXX */
1028          .ai_se_chans = 64,
1029          .ai_bits = 14,
1030          .ai_speed = 1000,
1031          .ao_nchan = 2,
1032          .ao_scan_speed = 10000,
1033          .layout = LAYOUT_64XX,
1034          .ai_range_table = &ai_ranges_64xx,
1035          .ai_fifo = ai_fifo_64xx,
1036          .has_8255 = 1,
1037          },
1038         {
1039          .name = "pci-das64/m2/14",
1040          .device_id = 0,        /*  XXX */
1041          .ai_se_chans = 64,
1042          .ai_bits = 14,
1043          .ai_speed = 500,
1044          .ao_nchan = 2,
1045          .ao_scan_speed = 10000,
1046          .layout = LAYOUT_64XX,
1047          .ai_range_table = &ai_ranges_64xx,
1048          .ai_fifo = ai_fifo_64xx,
1049          .has_8255 = 1,
1050          },
1051         {
1052          .name = "pci-das64/m3/14",
1053          .device_id = 0,        /*  XXX */
1054          .ai_se_chans = 64,
1055          .ai_bits = 14,
1056          .ai_speed = 333,
1057          .ao_nchan = 2,
1058          .ao_scan_speed = 10000,
1059          .layout = LAYOUT_64XX,
1060          .ai_range_table = &ai_ranges_64xx,
1061          .ai_fifo = ai_fifo_64xx,
1062          .has_8255 = 1,
1063          },
1064 #endif
1065 };
1066
1067 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1068                                               int use_differential)
1069 {
1070         const struct pcidas64_board *thisboard = comedi_board(dev);
1071
1072         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1073             (thisboard->layout == LAYOUT_60XX && use_differential))
1074                 return ADC_SE_DIFF_BIT;
1075         else
1076                 return 0;
1077 };
1078
1079 struct ext_clock_info {
1080         /*  master clock divisor to use for scans with external master clock */
1081         unsigned int divisor;
1082         /*  chanspec for master clock input when used as scan begin src */
1083         unsigned int chanspec;
1084 };
1085
1086 /* this structure is for data unique to this hardware driver. */
1087 struct pcidas64_private {
1088         /*  base addresses (physical) */
1089         resource_size_t plx9080_phys_iobase;
1090         resource_size_t main_phys_iobase;
1091         resource_size_t dio_counter_phys_iobase;
1092         /*  base addresses (ioremapped) */
1093         void __iomem *plx9080_iobase;
1094         void __iomem *main_iobase;
1095         void __iomem *dio_counter_iobase;
1096         /*  local address (used by dma controller) */
1097         uint32_t local0_iobase;
1098         uint32_t local1_iobase;
1099         /*  number of analog input samples remaining */
1100         volatile unsigned int ai_count;
1101         /*  dma buffers for analog input */
1102         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1103         /*  physical addresses of ai dma buffers */
1104         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1105         /*  array of ai dma descriptors read by plx9080,
1106          *  allocated to get proper alignment */
1107         struct plx_dma_desc *ai_dma_desc;
1108         /*  physical address of ai dma descriptor array */
1109         dma_addr_t ai_dma_desc_bus_addr;
1110         /*  index of the ai dma descriptor/buffer
1111          *  that is currently being used */
1112         volatile unsigned int ai_dma_index;
1113         /*  dma buffers for analog output */
1114         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1115         /*  physical addresses of ao dma buffers */
1116         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1117         struct plx_dma_desc *ao_dma_desc;
1118         dma_addr_t ao_dma_desc_bus_addr;
1119         /*  keeps track of buffer where the next ao sample should go */
1120         volatile unsigned int ao_dma_index;
1121         /*  number of analog output samples remaining */
1122         volatile unsigned long ao_count;
1123         /*  remember what the analog outputs are set to, to allow readback */
1124         volatile unsigned int ao_value[2];
1125         unsigned int hw_revision;       /*  stc chip hardware revision number */
1126         /*  last bits sent to INTR_ENABLE_REG register */
1127         volatile unsigned int intr_enable_bits;
1128         /*  last bits sent to ADC_CONTROL1_REG register */
1129         volatile uint16_t adc_control1_bits;
1130         /*  last bits sent to FIFO_SIZE_REG register */
1131         volatile uint16_t fifo_size_bits;
1132         /*  last bits sent to HW_CONFIG_REG register */
1133         volatile uint16_t hw_config_bits;
1134         volatile uint16_t dac_control1_bits;
1135         /*  last bits written to plx9080 control register */
1136         volatile uint32_t plx_control_bits;
1137         /*  last bits written to plx interrupt control and status register */
1138         volatile uint32_t plx_intcsr_bits;
1139         /*  index of calibration source readable through ai ch0 */
1140         volatile int calibration_source;
1141         /*  bits written to i2c calibration/range register */
1142         volatile uint8_t i2c_cal_range_bits;
1143         /*  configure digital triggers to trigger on falling edge */
1144         volatile unsigned int ext_trig_falling;
1145         /*  states of various devices stored to enable read-back */
1146         unsigned int ad8402_state[2];
1147         unsigned int caldac_state[8];
1148         volatile short ai_cmd_running;
1149         unsigned int ai_fifo_segment_length;
1150         struct ext_clock_info ext_clock;
1151         short ao_bounce_buffer[DAC_FIFO_SIZE];
1152 };
1153
1154 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1155                                        unsigned int range_index)
1156 {
1157         const struct pcidas64_board *thisboard = comedi_board(dev);
1158         const struct comedi_krange *range =
1159                 &thisboard->ai_range_table->range[range_index];
1160         unsigned int bits = 0;
1161
1162         switch (range->max) {
1163         case 10000000:
1164                 bits = 0x000;
1165                 break;
1166         case 5000000:
1167                 bits = 0x100;
1168                 break;
1169         case 2000000:
1170         case 2500000:
1171                 bits = 0x200;
1172                 break;
1173         case 1000000:
1174         case 1250000:
1175                 bits = 0x300;
1176                 break;
1177         case 500000:
1178                 bits = 0x400;
1179                 break;
1180         case 200000:
1181         case 250000:
1182                 bits = 0x500;
1183                 break;
1184         case 100000:
1185                 bits = 0x600;
1186                 break;
1187         case 50000:
1188                 bits = 0x700;
1189                 break;
1190         default:
1191                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1192                 break;
1193         }
1194         if (range->min == 0)
1195                 bits += 0x900;
1196         return bits;
1197 }
1198
1199 static unsigned int hw_revision(const struct comedi_device *dev,
1200                                 uint16_t hw_status_bits)
1201 {
1202         const struct pcidas64_board *thisboard = comedi_board(dev);
1203
1204         if (thisboard->layout == LAYOUT_4020)
1205                 return (hw_status_bits >> 13) & 0x7;
1206
1207         return (hw_status_bits >> 12) & 0xf;
1208 }
1209
1210 static void set_dac_range_bits(struct comedi_device *dev,
1211                                volatile uint16_t *bits, unsigned int channel,
1212                                unsigned int range)
1213 {
1214         const struct pcidas64_board *thisboard = comedi_board(dev);
1215         unsigned int code = thisboard->ao_range_code[range];
1216
1217         if (channel > 1)
1218                 comedi_error(dev, "bug! bad channel?");
1219         if (code & ~0x3)
1220                 comedi_error(dev, "bug! bad range code?");
1221
1222         *bits &= ~(0x3 << (2 * channel));
1223         *bits |= code << (2 * channel);
1224 };
1225
1226 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1227 {
1228         return board->ao_nchan && board->layout != LAYOUT_4020;
1229 }
1230
1231 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1232 {
1233         struct pcidas64_private *devpriv = dev->private;
1234         unsigned long flags;
1235
1236         /*  spinlock for plx dma control/status reg */
1237         spin_lock_irqsave(&dev->spinlock, flags);
1238
1239         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1240
1241         spin_unlock_irqrestore(&dev->spinlock, flags);
1242 }
1243
1244 static void disable_plx_interrupts(struct comedi_device *dev)
1245 {
1246         struct pcidas64_private *devpriv = dev->private;
1247
1248         devpriv->plx_intcsr_bits = 0;
1249         writel(devpriv->plx_intcsr_bits,
1250                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1251 }
1252
1253 static void disable_ai_interrupts(struct comedi_device *dev)
1254 {
1255         struct pcidas64_private *devpriv = dev->private;
1256         unsigned long flags;
1257
1258         spin_lock_irqsave(&dev->spinlock, flags);
1259         devpriv->intr_enable_bits &=
1260                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1261                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1262                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1263         writew(devpriv->intr_enable_bits,
1264                devpriv->main_iobase + INTR_ENABLE_REG);
1265         spin_unlock_irqrestore(&dev->spinlock, flags);
1266
1267         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1268 }
1269
1270 static void enable_ai_interrupts(struct comedi_device *dev,
1271                                  const struct comedi_cmd *cmd)
1272 {
1273         const struct pcidas64_board *thisboard = comedi_board(dev);
1274         struct pcidas64_private *devpriv = dev->private;
1275         uint32_t bits;
1276         unsigned long flags;
1277
1278         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1279                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1280         /*  Use pio transfer and interrupt on end of conversion
1281          *  if TRIG_WAKE_EOS flag is set. */
1282         if (cmd->flags & TRIG_WAKE_EOS) {
1283                 /*  4020 doesn't support pio transfers except for fifo dregs */
1284                 if (thisboard->layout != LAYOUT_4020)
1285                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1286         }
1287         spin_lock_irqsave(&dev->spinlock, flags);
1288         devpriv->intr_enable_bits |= bits;
1289         writew(devpriv->intr_enable_bits,
1290                devpriv->main_iobase + INTR_ENABLE_REG);
1291         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1292         spin_unlock_irqrestore(&dev->spinlock, flags);
1293 }
1294
1295 /* initialize plx9080 chip */
1296 static void init_plx9080(struct comedi_device *dev)
1297 {
1298         const struct pcidas64_board *thisboard = comedi_board(dev);
1299         struct pcidas64_private *devpriv = dev->private;
1300         uint32_t bits;
1301         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1302
1303         devpriv->plx_control_bits =
1304                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1305
1306         /*  plx9080 dump */
1307         DEBUG_PRINT(" plx interrupt status 0x%x\n",
1308                     readl(plx_iobase + PLX_INTRCS_REG));
1309         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1310         DEBUG_PRINT(" plx control reg 0x%x\n", devpriv->plx_control_bits);
1311         DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1312                     readl(plx_iobase + PLX_MARB_REG));
1313         DEBUG_PRINT(" plx region0 reg 0x%x\n",
1314                     readl(plx_iobase + PLX_REGION0_REG));
1315         DEBUG_PRINT(" plx region1 reg 0x%x\n",
1316                     readl(plx_iobase + PLX_REGION1_REG));
1317
1318         DEBUG_PRINT(" plx revision 0x%x\n",
1319                     readl(plx_iobase + PLX_REVISION_REG));
1320         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1321                     readl(plx_iobase + PLX_DMA0_MODE_REG));
1322         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1323                     readl(plx_iobase + PLX_DMA1_MODE_REG));
1324         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1325                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1326         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1327                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1328         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1329                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1330         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1331                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1332         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1333                     readb(plx_iobase + PLX_DMA0_CS_REG));
1334         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1335                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1336         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1337
1338 #ifdef __BIG_ENDIAN
1339         bits = BIGEND_DMA0 | BIGEND_DMA1;
1340 #else
1341         bits = 0;
1342 #endif
1343         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1344
1345         disable_plx_interrupts(dev);
1346
1347         abort_dma(dev, 0);
1348         abort_dma(dev, 1);
1349
1350         /*  configure dma0 mode */
1351         bits = 0;
1352         /*  enable ready input, not sure if this is necessary */
1353         bits |= PLX_DMA_EN_READYIN_BIT;
1354         /*  enable bterm, not sure if this is necessary */
1355         bits |= PLX_EN_BTERM_BIT;
1356         /*  enable dma chaining */
1357         bits |= PLX_EN_CHAIN_BIT;
1358         /*  enable interrupt on dma done
1359          *  (probably don't need this, since chain never finishes) */
1360         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1361         /*  don't increment local address during transfers
1362          *  (we are transferring from a fixed fifo register) */
1363         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1364         /*  route dma interrupt to pci bus */
1365         bits |= PLX_DMA_INTR_PCI_BIT;
1366         /*  enable demand mode */
1367         bits |= PLX_DEMAND_MODE_BIT;
1368         /*  enable local burst mode */
1369         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1370         /*  4020 uses 32 bit dma */
1371         if (thisboard->layout == LAYOUT_4020)
1372                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1373         else            /*  localspace0 bus is 16 bits wide */
1374                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1375         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1376         if (ao_cmd_is_supported(thisboard))
1377                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1378
1379         /*  enable interrupts on plx 9080 */
1380         devpriv->plx_intcsr_bits |=
1381             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1382             ICS_DMA0_E | ICS_DMA1_E;
1383         writel(devpriv->plx_intcsr_bits,
1384                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1385 }
1386
1387 static void disable_ai_pacing(struct comedi_device *dev)
1388 {
1389         struct pcidas64_private *devpriv = dev->private;
1390         unsigned long flags;
1391
1392         disable_ai_interrupts(dev);
1393
1394         spin_lock_irqsave(&dev->spinlock, flags);
1395         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1396         writew(devpriv->adc_control1_bits,
1397                devpriv->main_iobase + ADC_CONTROL1_REG);
1398         spin_unlock_irqrestore(&dev->spinlock, flags);
1399
1400         /* disable pacing, triggering, etc */
1401         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1402                devpriv->main_iobase + ADC_CONTROL0_REG);
1403 }
1404
1405 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1406                                       unsigned int num_entries)
1407 {
1408         const struct pcidas64_board *thisboard = comedi_board(dev);
1409         struct pcidas64_private *devpriv = dev->private;
1410         static const int increment_size = 0x100;
1411         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1412         unsigned int num_increments;
1413         uint16_t bits;
1414
1415         if (num_entries < increment_size)
1416                 num_entries = increment_size;
1417         if (num_entries > fifo->max_segment_length)
1418                 num_entries = fifo->max_segment_length;
1419
1420         /*  1 == 256 entries, 2 == 512 entries, etc */
1421         num_increments = (num_entries + increment_size / 2) / increment_size;
1422
1423         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1424         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1425         devpriv->fifo_size_bits |= bits;
1426         writew(devpriv->fifo_size_bits,
1427                devpriv->main_iobase + FIFO_SIZE_REG);
1428
1429         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1430
1431         DEBUG_PRINT("set hardware fifo segment length to %i\n",
1432                     devpriv->ai_fifo_segment_length);
1433
1434         return devpriv->ai_fifo_segment_length;
1435 }
1436
1437 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1438 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1439 {
1440         const struct pcidas64_board *thisboard = comedi_board(dev);
1441         unsigned int num_fifo_entries;
1442         int retval;
1443         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1444
1445         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1446
1447         retval = set_ai_fifo_segment_length(dev,
1448                                             num_fifo_entries /
1449                                             fifo->num_segments);
1450         if (retval < 0)
1451                 return retval;
1452
1453         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1454
1455         DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
1456
1457         return num_samples;
1458 }
1459
1460 /* query length of fifo */
1461 static unsigned int ai_fifo_size(struct comedi_device *dev)
1462 {
1463         const struct pcidas64_board *thisboard = comedi_board(dev);
1464         struct pcidas64_private *devpriv = dev->private;
1465
1466         return devpriv->ai_fifo_segment_length *
1467                thisboard->ai_fifo->num_segments *
1468                thisboard->ai_fifo->sample_packing_ratio;
1469 }
1470
1471 static void init_stc_registers(struct comedi_device *dev)
1472 {
1473         const struct pcidas64_board *thisboard = comedi_board(dev);
1474         struct pcidas64_private *devpriv = dev->private;
1475         uint16_t bits;
1476         unsigned long flags;
1477
1478         spin_lock_irqsave(&dev->spinlock, flags);
1479
1480         /*  bit should be set for 6025,
1481          *  although docs say boards with <= 16 chans should be cleared XXX */
1482         if (1)
1483                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1484         writew(devpriv->adc_control1_bits,
1485                devpriv->main_iobase + ADC_CONTROL1_REG);
1486
1487         /*  6402/16 manual says this register must be initialized to 0xff? */
1488         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1489
1490         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1491         if (thisboard->layout == LAYOUT_4020)
1492                 bits |= INTERNAL_CLOCK_4020_BITS;
1493         devpriv->hw_config_bits |= bits;
1494         writew(devpriv->hw_config_bits,
1495                devpriv->main_iobase + HW_CONFIG_REG);
1496
1497         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1498         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1499
1500         spin_unlock_irqrestore(&dev->spinlock, flags);
1501
1502         /*  set fifos to maximum size */
1503         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1504         set_ai_fifo_segment_length(dev,
1505                                    thisboard->ai_fifo->max_segment_length);
1506
1507         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1508         devpriv->intr_enable_bits =
1509                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1510                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1511         writew(devpriv->intr_enable_bits,
1512                devpriv->main_iobase + INTR_ENABLE_REG);
1513
1514         disable_ai_pacing(dev);
1515 };
1516
1517 static int alloc_and_init_dma_members(struct comedi_device *dev)
1518 {
1519         const struct pcidas64_board *thisboard = comedi_board(dev);
1520         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1521         struct pcidas64_private *devpriv = dev->private;
1522         int i;
1523
1524         /*  alocate pci dma buffers */
1525         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1526                 devpriv->ai_buffer[i] =
1527                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1528                                              &devpriv->ai_buffer_bus_addr[i]);
1529                 if (devpriv->ai_buffer[i] == NULL)
1530                         return -ENOMEM;
1531
1532         }
1533         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1534                 if (ao_cmd_is_supported(thisboard)) {
1535                         devpriv->ao_buffer[i] =
1536                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1537                                                      &devpriv->
1538                                                       ao_buffer_bus_addr[i]);
1539                         if (devpriv->ao_buffer[i] == NULL)
1540                                 return -ENOMEM;
1541
1542                 }
1543         }
1544         /*  allocate dma descriptors */
1545         devpriv->ai_dma_desc =
1546                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1547                                      ai_dma_ring_count(thisboard),
1548                                      &devpriv->ai_dma_desc_bus_addr);
1549         if (devpriv->ai_dma_desc == NULL)
1550                 return -ENOMEM;
1551
1552         DEBUG_PRINT("ai dma descriptors start at bus addr 0x%llx\n",
1553                     (unsigned long long)devpriv->ai_dma_desc_bus_addr);
1554         if (ao_cmd_is_supported(thisboard)) {
1555                 devpriv->ao_dma_desc =
1556                         pci_alloc_consistent(pcidev,
1557                                              sizeof(struct plx_dma_desc) *
1558                                              AO_DMA_RING_COUNT,
1559                                              &devpriv->ao_dma_desc_bus_addr);
1560                 if (devpriv->ao_dma_desc == NULL)
1561                         return -ENOMEM;
1562
1563                 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%llx\n",
1564                             (unsigned long long)devpriv->ao_dma_desc_bus_addr);
1565         }
1566         /*  initialize dma descriptors */
1567         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1568                 devpriv->ai_dma_desc[i].pci_start_addr =
1569                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1570                 if (thisboard->layout == LAYOUT_4020)
1571                         devpriv->ai_dma_desc[i].local_start_addr =
1572                                 cpu_to_le32(devpriv->local1_iobase +
1573                                             ADC_FIFO_REG);
1574                 else
1575                         devpriv->ai_dma_desc[i].local_start_addr =
1576                                 cpu_to_le32(devpriv->local0_iobase +
1577                                             ADC_FIFO_REG);
1578                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1579                 devpriv->ai_dma_desc[i].next =
1580                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1581                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1582                                      sizeof(devpriv->ai_dma_desc[0])) |
1583                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1584                                     PLX_XFER_LOCAL_TO_PCI);
1585         }
1586         if (ao_cmd_is_supported(thisboard)) {
1587                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1588                         devpriv->ao_dma_desc[i].pci_start_addr =
1589                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1590                         devpriv->ao_dma_desc[i].local_start_addr =
1591                                 cpu_to_le32(devpriv->local0_iobase +
1592                                             DAC_FIFO_REG);
1593                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1594                         devpriv->ao_dma_desc[i].next =
1595                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1596                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1597                                              sizeof(devpriv->ao_dma_desc[0])) |
1598                                             PLX_DESC_IN_PCI_BIT |
1599                                             PLX_INTR_TERM_COUNT);
1600                 }
1601         }
1602         return 0;
1603 }
1604
1605 static inline void warn_external_queue(struct comedi_device *dev)
1606 {
1607         comedi_error(dev,
1608                      "AO command and AI external channel queue cannot be used simultaneously.");
1609         comedi_error(dev,
1610                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1611 }
1612
1613 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1614 static const int i2c_high_udelay = 1000;
1615 static const int i2c_low_udelay = 10;
1616
1617 /* set i2c data line high or low */
1618 static void i2c_set_sda(struct comedi_device *dev, int state)
1619 {
1620         struct pcidas64_private *devpriv = dev->private;
1621         static const int data_bit = CTL_EE_W;
1622         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1623                                          PLX_CONTROL_REG;
1624
1625         if (state) {
1626                 /*  set data line high */
1627                 devpriv->plx_control_bits &= ~data_bit;
1628                 writel(devpriv->plx_control_bits, plx_control_addr);
1629                 udelay(i2c_high_udelay);
1630         } else {                /*  set data line low */
1631
1632                 devpriv->plx_control_bits |= data_bit;
1633                 writel(devpriv->plx_control_bits, plx_control_addr);
1634                 udelay(i2c_low_udelay);
1635         }
1636 }
1637
1638 /* set i2c clock line high or low */
1639 static void i2c_set_scl(struct comedi_device *dev, int state)
1640 {
1641         struct pcidas64_private *devpriv = dev->private;
1642         static const int clock_bit = CTL_USERO;
1643         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1644                                          PLX_CONTROL_REG;
1645
1646         if (state) {
1647                 /*  set clock line high */
1648                 devpriv->plx_control_bits &= ~clock_bit;
1649                 writel(devpriv->plx_control_bits, plx_control_addr);
1650                 udelay(i2c_high_udelay);
1651         } else {                /*  set clock line low */
1652
1653                 devpriv->plx_control_bits |= clock_bit;
1654                 writel(devpriv->plx_control_bits, plx_control_addr);
1655                 udelay(i2c_low_udelay);
1656         }
1657 }
1658
1659 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1660 {
1661         uint8_t bit;
1662         unsigned int num_bits = 8;
1663
1664         DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
1665
1666         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1667                 i2c_set_scl(dev, 0);
1668                 if ((byte & bit))
1669                         i2c_set_sda(dev, 1);
1670                 else
1671                         i2c_set_sda(dev, 0);
1672                 i2c_set_scl(dev, 1);
1673         }
1674 }
1675
1676 /* we can't really read the lines, so fake it */
1677 static int i2c_read_ack(struct comedi_device *dev)
1678 {
1679         i2c_set_scl(dev, 0);
1680         i2c_set_sda(dev, 1);
1681         i2c_set_scl(dev, 1);
1682
1683         return 0;               /*  return fake acknowledge bit */
1684 }
1685
1686 /* send start bit */
1687 static void i2c_start(struct comedi_device *dev)
1688 {
1689         i2c_set_scl(dev, 1);
1690         i2c_set_sda(dev, 1);
1691         i2c_set_sda(dev, 0);
1692 }
1693
1694 /* send stop bit */
1695 static void i2c_stop(struct comedi_device *dev)
1696 {
1697         i2c_set_scl(dev, 0);
1698         i2c_set_sda(dev, 0);
1699         i2c_set_scl(dev, 1);
1700         i2c_set_sda(dev, 1);
1701 }
1702
1703 static void i2c_write(struct comedi_device *dev, unsigned int address,
1704                       const uint8_t *data, unsigned int length)
1705 {
1706         struct pcidas64_private *devpriv = dev->private;
1707         unsigned int i;
1708         uint8_t bitstream;
1709         static const int read_bit = 0x1;
1710
1711         /* XXX need mutex to prevent simultaneous attempts to access
1712          * eeprom and i2c bus */
1713
1714         /*  make sure we dont send anything to eeprom */
1715         devpriv->plx_control_bits &= ~CTL_EE_CS;
1716
1717         i2c_stop(dev);
1718         i2c_start(dev);
1719
1720         /*  send address and write bit */
1721         bitstream = (address << 1) & ~read_bit;
1722         i2c_write_byte(dev, bitstream);
1723
1724         /*  get acknowledge */
1725         if (i2c_read_ack(dev) != 0) {
1726                 comedi_error(dev, "i2c write failed: no acknowledge");
1727                 i2c_stop(dev);
1728                 return;
1729         }
1730         /*  write data bytes */
1731         for (i = 0; i < length; i++) {
1732                 i2c_write_byte(dev, data[i]);
1733                 if (i2c_read_ack(dev) != 0) {
1734                         comedi_error(dev, "i2c write failed: no acknowledge");
1735                         i2c_stop(dev);
1736                         return;
1737                 }
1738         }
1739         i2c_stop(dev);
1740 }
1741
1742 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1743                     struct comedi_insn *insn, unsigned int *data)
1744 {
1745         const struct pcidas64_board *thisboard = comedi_board(dev);
1746         struct pcidas64_private *devpriv = dev->private;
1747         unsigned int bits = 0, n, i;
1748         unsigned int channel, range, aref;
1749         unsigned long flags;
1750         static const int timeout = 100;
1751
1752         DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1753         channel = CR_CHAN(insn->chanspec);
1754         range = CR_RANGE(insn->chanspec);
1755         aref = CR_AREF(insn->chanspec);
1756
1757         /*  disable card's analog input interrupt sources and pacing */
1758         /*  4020 generates dac done interrupts even though they are disabled */
1759         disable_ai_pacing(dev);
1760
1761         spin_lock_irqsave(&dev->spinlock, flags);
1762         if (insn->chanspec & CR_ALT_FILTER)
1763                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1764         else
1765                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1766         writew(devpriv->adc_control1_bits,
1767                devpriv->main_iobase + ADC_CONTROL1_REG);
1768         spin_unlock_irqrestore(&dev->spinlock, flags);
1769
1770         if (thisboard->layout != LAYOUT_4020) {
1771                 /*  use internal queue */
1772                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1773                 writew(devpriv->hw_config_bits,
1774                        devpriv->main_iobase + HW_CONFIG_REG);
1775
1776                 /*  ALT_SOURCE is internal calibration reference */
1777                 if (insn->chanspec & CR_ALT_SOURCE) {
1778                         unsigned int cal_en_bit;
1779
1780                         DEBUG_PRINT("reading calibration source\n");
1781                         if (thisboard->layout == LAYOUT_60XX)
1782                                 cal_en_bit = CAL_EN_60XX_BIT;
1783                         else
1784                                 cal_en_bit = CAL_EN_64XX_BIT;
1785                         /*  select internal reference source to connect
1786                          *  to channel 0 */
1787                         writew(cal_en_bit |
1788                                adc_src_bits(devpriv->calibration_source),
1789                                devpriv->main_iobase + CALIBRATION_REG);
1790                 } else {
1791                         /*  make sure internal calibration source
1792                          *  is turned off */
1793                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1794                 }
1795                 /*  load internal queue */
1796                 bits = 0;
1797                 /*  set gain */
1798                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1799                 /*  set single-ended / differential */
1800                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1801                 if (aref == AREF_COMMON)
1802                         bits |= ADC_COMMON_BIT;
1803                 bits |= adc_chan_bits(channel);
1804                 /*  set stop channel */
1805                 writew(adc_chan_bits(channel),
1806                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1807                 /*  set start channel, and rest of settings */
1808                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1809         } else {
1810                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1811
1812                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1813                 if (insn->chanspec & CR_ALT_SOURCE) {
1814                         DEBUG_PRINT("reading calibration source\n");
1815                         devpriv->i2c_cal_range_bits |=
1816                                 adc_src_4020_bits(devpriv->calibration_source);
1817                 } else {        /* select BNC inputs */
1818                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1819                 }
1820                 /*  select range */
1821                 if (range == 0)
1822                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1823                 else
1824                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1825                 /*  update calibration/range i2c register only if necessary,
1826                  *  as it is very slow */
1827                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1828                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1829                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1830                                   sizeof(i2c_data));
1831                 }
1832
1833                 /* 4020 manual asks that sample interval register to be set
1834                  * before writing to convert register.
1835                  * Using somewhat arbitrary setting of 4 master clock ticks
1836                  * = 0.1 usec */
1837                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1838                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1839         }
1840
1841         for (n = 0; n < insn->n; n++) {
1842
1843                 /*  clear adc buffer (inside loop for 4020 sake) */
1844                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1845
1846                 /* trigger conversion, bits sent only matter for 4020 */
1847                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1848                        devpriv->main_iobase + ADC_CONVERT_REG);
1849
1850                 /*  wait for data */
1851                 for (i = 0; i < timeout; i++) {
1852                         bits = readw(devpriv->main_iobase + HW_STATUS_REG);
1853                         DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1854                         if (thisboard->layout == LAYOUT_4020) {
1855                                 if (readw(devpriv->main_iobase +
1856                                           ADC_WRITE_PNTR_REG))
1857                                         break;
1858                         } else {
1859                                 if (pipe_full_bits(bits))
1860                                         break;
1861                         }
1862                         udelay(1);
1863                 }
1864                 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1865                 if (i == timeout) {
1866                         comedi_error(dev, " analog input read insn timed out");
1867                         dev_info(dev->class_dev, "status 0x%x\n", bits);
1868                         return -ETIME;
1869                 }
1870                 if (thisboard->layout == LAYOUT_4020)
1871                         data[n] = readl(devpriv->dio_counter_iobase +
1872                                         ADC_FIFO_REG) & 0xffff;
1873                 else
1874                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1875         }
1876
1877         return n;
1878 }
1879
1880 static int ai_config_calibration_source(struct comedi_device *dev,
1881                                         unsigned int *data)
1882 {
1883         const struct pcidas64_board *thisboard = comedi_board(dev);
1884         struct pcidas64_private *devpriv = dev->private;
1885         unsigned int source = data[1];
1886         int num_calibration_sources;
1887
1888         if (thisboard->layout == LAYOUT_60XX)
1889                 num_calibration_sources = 16;
1890         else
1891                 num_calibration_sources = 8;
1892         if (source >= num_calibration_sources) {
1893                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1894                         source);
1895                 return -EINVAL;
1896         }
1897
1898         DEBUG_PRINT("setting calibration source to %i\n", source);
1899         devpriv->calibration_source = source;
1900
1901         return 2;
1902 }
1903
1904 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1905 {
1906         const struct pcidas64_board *thisboard = comedi_board(dev);
1907         int fifo_size;
1908         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1909         unsigned int block_size, requested_block_size;
1910         int retval;
1911
1912         requested_block_size = data[1];
1913
1914         if (requested_block_size) {
1915                 fifo_size = requested_block_size * fifo->num_segments /
1916                             bytes_in_sample;
1917
1918                 retval = set_ai_fifo_size(dev, fifo_size);
1919                 if (retval < 0)
1920                         return retval;
1921
1922         }
1923
1924         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1925
1926         data[1] = block_size;
1927
1928         return 2;
1929 }
1930
1931 static int ai_config_master_clock_4020(struct comedi_device *dev,
1932                                        unsigned int *data)
1933 {
1934         struct pcidas64_private *devpriv = dev->private;
1935         unsigned int divisor = data[4];
1936         int retval = 0;
1937
1938         if (divisor < 2) {
1939                 divisor = 2;
1940                 retval = -EAGAIN;
1941         }
1942
1943         switch (data[1]) {
1944         case COMEDI_EV_SCAN_BEGIN:
1945                 devpriv->ext_clock.divisor = divisor;
1946                 devpriv->ext_clock.chanspec = data[2];
1947                 break;
1948         default:
1949                 return -EINVAL;
1950                 break;
1951         }
1952
1953         data[4] = divisor;
1954
1955         return retval ? retval : 5;
1956 }
1957
1958 /* XXX could add support for 60xx series */
1959 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1960 {
1961         const struct pcidas64_board *thisboard = comedi_board(dev);
1962
1963         switch (thisboard->layout) {
1964         case LAYOUT_4020:
1965                 return ai_config_master_clock_4020(dev, data);
1966                 break;
1967         default:
1968                 return -EINVAL;
1969                 break;
1970         }
1971
1972         return -EINVAL;
1973 }
1974
1975 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1976                           struct comedi_insn *insn, unsigned int *data)
1977 {
1978         int id = data[0];
1979
1980         switch (id) {
1981         case INSN_CONFIG_ALT_SOURCE:
1982                 return ai_config_calibration_source(dev, data);
1983                 break;
1984         case INSN_CONFIG_BLOCK_SIZE:
1985                 return ai_config_block_size(dev, data);
1986                 break;
1987         case INSN_CONFIG_TIMER_1:
1988                 return ai_config_master_clock(dev, data);
1989                 break;
1990         default:
1991                 return -EINVAL;
1992                 break;
1993         }
1994         return -EINVAL;
1995 }
1996
1997 /* Gets nearest achievable timing given master clock speed, does not
1998  * take into account possible minimum/maximum divisor values.  Used
1999  * by other timing checking functions. */
2000 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
2001 {
2002         unsigned int divisor;
2003
2004         switch (flags & TRIG_ROUND_MASK) {
2005         case TRIG_ROUND_UP:
2006                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2007                 break;
2008         case TRIG_ROUND_DOWN:
2009                 divisor = ns / TIMER_BASE;
2010                 break;
2011         case TRIG_ROUND_NEAREST:
2012         default:
2013                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2014                 break;
2015         }
2016         return divisor;
2017 }
2018
2019 /* utility function that rounds desired timing to an achievable time, and
2020  * sets cmd members appropriately.
2021  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
2022  */
2023 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2024 {
2025         const struct pcidas64_board *thisboard = comedi_board(dev);
2026         unsigned int convert_divisor = 0, scan_divisor;
2027         static const int min_convert_divisor = 3;
2028         static const int max_convert_divisor =
2029                 max_counter_value + min_convert_divisor;
2030         static const int min_scan_divisor_4020 = 2;
2031         unsigned long long max_scan_divisor, min_scan_divisor;
2032
2033         if (cmd->convert_src == TRIG_TIMER) {
2034                 if (thisboard->layout == LAYOUT_4020) {
2035                         cmd->convert_arg = 0;
2036                 } else {
2037                         convert_divisor = get_divisor(cmd->convert_arg,
2038                                                       cmd->flags);
2039                         if (convert_divisor > max_convert_divisor)
2040                                 convert_divisor = max_convert_divisor;
2041                         if (convert_divisor < min_convert_divisor)
2042                                 convert_divisor = min_convert_divisor;
2043                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2044                 }
2045         } else if (cmd->convert_src == TRIG_NOW) {
2046                 cmd->convert_arg = 0;
2047         }
2048
2049         if (cmd->scan_begin_src == TRIG_TIMER) {
2050                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2051                 if (cmd->convert_src == TRIG_TIMER) {
2052                         /*  XXX check for integer overflows */
2053                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2054                         max_scan_divisor =
2055                                 (convert_divisor * cmd->chanlist_len - 1) +
2056                                 max_counter_value;
2057                 } else {
2058                         min_scan_divisor = min_scan_divisor_4020;
2059                         max_scan_divisor = max_counter_value + min_scan_divisor;
2060                 }
2061                 if (scan_divisor > max_scan_divisor)
2062                         scan_divisor = max_scan_divisor;
2063                 if (scan_divisor < min_scan_divisor)
2064                         scan_divisor = min_scan_divisor;
2065                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2066         }
2067
2068         return;
2069 }
2070
2071 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2072                       struct comedi_cmd *cmd)
2073 {
2074         const struct pcidas64_board *thisboard = comedi_board(dev);
2075         int err = 0;
2076         unsigned int tmp_arg, tmp_arg2;
2077         int i;
2078         int aref;
2079         unsigned int triggers;
2080
2081         /* Step 1 : check if triggers are trivially valid */
2082
2083         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2084
2085         triggers = TRIG_TIMER;
2086         if (thisboard->layout == LAYOUT_4020)
2087                 triggers |= TRIG_OTHER;
2088         else
2089                 triggers |= TRIG_FOLLOW;
2090         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2091
2092         triggers = TRIG_TIMER;
2093         if (thisboard->layout == LAYOUT_4020)
2094                 triggers |= TRIG_NOW;
2095         else
2096                 triggers |= TRIG_EXT;
2097         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2098         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2099         err |= cfc_check_trigger_src(&cmd->stop_src,
2100                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2101
2102         if (err)
2103                 return 1;
2104
2105         /* Step 2a : make sure trigger sources are unique */
2106
2107         err |= cfc_check_trigger_is_unique(cmd->start_src);
2108         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2109         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2110         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2111
2112         /* Step 2b : and mutually compatible */
2113
2114         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2115                 err |= -EINVAL;
2116         if (cmd->stop_src != TRIG_COUNT &&
2117             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2118                 err |= -EINVAL;
2119
2120         if (err)
2121                 return 2;
2122
2123         /* Step 3: check if arguments are trivially valid */
2124
2125         if (cmd->convert_src == TRIG_TIMER) {
2126                 if (thisboard->layout == LAYOUT_4020) {
2127                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2128                 } else {
2129                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2130                                                          thisboard->ai_speed);
2131                         /* if scans are timed faster than conversion rate allows */
2132                         if (cmd->scan_begin_src == TRIG_TIMER)
2133                                 err |= cfc_check_trigger_arg_min(
2134                                                 &cmd->scan_begin_arg,
2135                                                 cmd->convert_arg *
2136                                                 cmd->chanlist_len);
2137                 }
2138         }
2139
2140         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2141         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2142
2143         switch (cmd->stop_src) {
2144         case TRIG_EXT:
2145                 break;
2146         case TRIG_COUNT:
2147                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2148                 break;
2149         case TRIG_NONE:
2150                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2151                 break;
2152         default:
2153                 break;
2154         }
2155
2156         if (err)
2157                 return 3;
2158
2159         /* step 4: fix up any arguments */
2160
2161         if (cmd->convert_src == TRIG_TIMER) {
2162                 tmp_arg = cmd->convert_arg;
2163                 tmp_arg2 = cmd->scan_begin_arg;
2164                 check_adc_timing(dev, cmd);
2165                 if (tmp_arg != cmd->convert_arg)
2166                         err++;
2167                 if (tmp_arg2 != cmd->scan_begin_arg)
2168                         err++;
2169         }
2170
2171         if (err)
2172                 return 4;
2173
2174         /*  make sure user is doesn't change analog reference mid chanlist */
2175         if (cmd->chanlist) {
2176                 aref = CR_AREF(cmd->chanlist[0]);
2177                 for (i = 1; i < cmd->chanlist_len; i++) {
2178                         if (aref != CR_AREF(cmd->chanlist[i])) {
2179                                 comedi_error(dev,
2180                                              "all elements in chanlist must use the same analog reference");
2181                                 err++;
2182                                 break;
2183                         }
2184                 }
2185                 /*  check 4020 chanlist */
2186                 if (thisboard->layout == LAYOUT_4020) {
2187                         unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2188                         for (i = 1; i < cmd->chanlist_len; i++) {
2189                                 if (CR_CHAN(cmd->chanlist[i]) !=
2190                                     first_channel + i) {
2191                                         comedi_error(dev,
2192                                                      "chanlist must use consecutive channels");
2193                                         err++;
2194                                         break;
2195                                 }
2196                         }
2197                         if (cmd->chanlist_len == 3) {
2198                                 comedi_error(dev,
2199                                              "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2200                                 err++;
2201                         }
2202                 }
2203         }
2204
2205         if (err)
2206                 return 5;
2207
2208         return 0;
2209 }
2210
2211 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2212 {
2213 /* disable for now until I work out a race */
2214         return 0;
2215
2216         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2217                 return 1;
2218         else
2219                 return 0;
2220 }
2221
2222 static void setup_sample_counters(struct comedi_device *dev,
2223                                   struct comedi_cmd *cmd)
2224 {
2225         struct pcidas64_private *devpriv = dev->private;
2226
2227         if (cmd->stop_src == TRIG_COUNT) {
2228                 /*  set software count */
2229                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2230         }
2231         /*  load hardware conversion counter */
2232         if (use_hw_sample_counter(cmd)) {
2233                 writew(cmd->stop_arg & 0xffff,
2234                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2235                 writew((cmd->stop_arg >> 16) & 0xff,
2236                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2237         } else {
2238                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2239         }
2240 }
2241
2242 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2243 {
2244         const struct pcidas64_board *thisboard = comedi_board(dev);
2245         struct pcidas64_private *devpriv = dev->private;
2246         unsigned int num_samples;
2247
2248         num_samples = devpriv->ai_fifo_segment_length *
2249                       thisboard->ai_fifo->sample_packing_ratio;
2250         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2251                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2252
2253         return num_samples;
2254 }
2255
2256 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2257                                         const struct comedi_cmd *cmd)
2258 {
2259         /*  supposed to load counter with desired divisor minus 3 */
2260         return cmd->convert_arg / TIMER_BASE - 3;
2261 }
2262
2263 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2264                                      struct comedi_cmd *cmd)
2265 {
2266         uint32_t count;
2267
2268         /*  figure out how long we need to delay at end of scan */
2269         switch (cmd->scan_begin_src) {
2270         case TRIG_TIMER:
2271                 count = (cmd->scan_begin_arg -
2272                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2273                         TIMER_BASE;
2274                 break;
2275         case TRIG_FOLLOW:
2276                 count = cmd->convert_arg / TIMER_BASE;
2277                 break;
2278         default:
2279                 return 0;
2280                 break;
2281         }
2282         return count - 3;
2283 }
2284
2285 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2286                                         struct comedi_cmd *cmd)
2287 {
2288         struct pcidas64_private *devpriv = dev->private;
2289         unsigned int divisor;
2290
2291         switch (cmd->scan_begin_src) {
2292         case TRIG_TIMER:
2293                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2294                 break;
2295         case TRIG_OTHER:
2296                 divisor = devpriv->ext_clock.divisor;
2297                 break;
2298         default:                /*  should never happen */
2299                 comedi_error(dev, "bug! failed to set ai pacing!");
2300                 divisor = 1000;
2301                 break;
2302         }
2303
2304         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2305         return divisor - 2;
2306 }
2307
2308 static void select_master_clock_4020(struct comedi_device *dev,
2309                                      const struct comedi_cmd *cmd)
2310 {
2311         struct pcidas64_private *devpriv = dev->private;
2312
2313         /*  select internal/external master clock */
2314         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2315         if (cmd->scan_begin_src == TRIG_OTHER) {
2316                 int chanspec = devpriv->ext_clock.chanspec;
2317
2318                 if (CR_CHAN(chanspec))
2319                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2320                 else
2321                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2322         } else {
2323                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2324         }
2325         writew(devpriv->hw_config_bits,
2326                devpriv->main_iobase + HW_CONFIG_REG);
2327 }
2328
2329 static void select_master_clock(struct comedi_device *dev,
2330                                 const struct comedi_cmd *cmd)
2331 {
2332         const struct pcidas64_board *thisboard = comedi_board(dev);
2333
2334         switch (thisboard->layout) {
2335         case LAYOUT_4020:
2336                 select_master_clock_4020(dev, cmd);
2337                 break;
2338         default:
2339                 break;
2340         }
2341 }
2342
2343 static inline void dma_start_sync(struct comedi_device *dev,
2344                                   unsigned int channel)
2345 {
2346         struct pcidas64_private *devpriv = dev->private;
2347         unsigned long flags;
2348
2349         /*  spinlock for plx dma control/status reg */
2350         spin_lock_irqsave(&dev->spinlock, flags);
2351         if (channel)
2352                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2353                        PLX_CLEAR_DMA_INTR_BIT,
2354                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2355         else
2356                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2357                        PLX_CLEAR_DMA_INTR_BIT,
2358                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2359         spin_unlock_irqrestore(&dev->spinlock, flags);
2360 }
2361
2362 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2363 {
2364         const struct pcidas64_board *thisboard = comedi_board(dev);
2365         struct pcidas64_private *devpriv = dev->private;
2366         uint32_t convert_counter = 0, scan_counter = 0;
2367
2368         check_adc_timing(dev, cmd);
2369
2370         select_master_clock(dev, cmd);
2371
2372         if (thisboard->layout == LAYOUT_4020) {
2373                 convert_counter = ai_convert_counter_4020(dev, cmd);
2374         } else {
2375                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2376                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2377         }
2378
2379         /*  load lower 16 bits of convert interval */
2380         writew(convert_counter & 0xffff,
2381                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2382         DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2383         /*  load upper 8 bits of convert interval */
2384         writew((convert_counter >> 16) & 0xff,
2385                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2386         /*  load lower 16 bits of scan delay */
2387         writew(scan_counter & 0xffff,
2388                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2389         /*  load upper 8 bits of scan delay */
2390         writew((scan_counter >> 16) & 0xff,
2391                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2392         DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2393 }
2394
2395 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2396 {
2397         int i;
2398
2399         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2400                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2401                     CR_CHAN(cmd->chanlist[i]) + 1)
2402                         return 0;
2403                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2404                     CR_RANGE(cmd->chanlist[i]))
2405                         return 0;
2406                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2407                         return 0;
2408         }
2409         return 1;
2410 }
2411
2412 static int setup_channel_queue(struct comedi_device *dev,
2413                                const struct comedi_cmd *cmd)
2414 {
2415         const struct pcidas64_board *thisboard = comedi_board(dev);
2416         struct pcidas64_private *devpriv = dev->private;
2417         unsigned short bits;
2418         int i;
2419
2420         if (thisboard->layout != LAYOUT_4020) {
2421                 if (use_internal_queue_6xxx(cmd)) {
2422                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2423                         writew(devpriv->hw_config_bits,
2424                                devpriv->main_iobase + HW_CONFIG_REG);
2425                         bits = 0;
2426                         /*  set channel */
2427                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2428                         /*  set gain */
2429                         bits |= ai_range_bits_6xxx(dev,
2430                                                    CR_RANGE(cmd->chanlist[0]));
2431                         /*  set single-ended / differential */
2432                         bits |= se_diff_bit_6xxx(dev,
2433                                                  CR_AREF(cmd->chanlist[0]) ==
2434                                                  AREF_DIFF);
2435                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2436                                 bits |= ADC_COMMON_BIT;
2437                         /*  set stop channel */
2438                         writew(adc_chan_bits
2439                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2440                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2441                         /*  set start channel, and rest of settings */
2442                         writew(bits,
2443                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2444                 } else {
2445                         /*  use external queue */
2446                         if (dev->write_subdev && dev->write_subdev->busy) {
2447                                 warn_external_queue(dev);
2448                                 return -EBUSY;
2449                         }
2450                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2451                         writew(devpriv->hw_config_bits,
2452                                devpriv->main_iobase + HW_CONFIG_REG);
2453                         /*  clear DAC buffer to prevent weird interactions */
2454                         writew(0,
2455                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2456                         /*  clear queue pointer */
2457                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2458                         /*  load external queue */
2459                         for (i = 0; i < cmd->chanlist_len; i++) {
2460                                 bits = 0;
2461                                 /*  set channel */
2462                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2463                                                               chanlist[i]));
2464                                 /*  set gain */
2465                                 bits |= ai_range_bits_6xxx(dev,
2466                                                            CR_RANGE(cmd->
2467                                                                     chanlist
2468                                                                     [i]));
2469                                 /*  set single-ended / differential */
2470                                 bits |= se_diff_bit_6xxx(dev,
2471                                                          CR_AREF(cmd->
2472                                                                  chanlist[i]) ==
2473                                                          AREF_DIFF);
2474                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2475                                         bits |= ADC_COMMON_BIT;
2476                                 /*  mark end of queue */
2477                                 if (i == cmd->chanlist_len - 1)
2478                                         bits |= QUEUE_EOSCAN_BIT |
2479                                                 QUEUE_EOSEQ_BIT;
2480                                 writew(bits,
2481                                        devpriv->main_iobase +
2482                                        ADC_QUEUE_FIFO_REG);
2483                                 DEBUG_PRINT(
2484                                             "wrote 0x%x to external channel queue\n",
2485                                             bits);
2486                         }
2487                         /* doing a queue clear is not specified in board docs,
2488                          * but required for reliable operation */
2489                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2490                         /*  prime queue holding register */
2491                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2492                 }
2493         } else {
2494                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2495
2496                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2497                 /* select BNC inputs */
2498                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2499                 /*  select ranges */
2500                 for (i = 0; i < cmd->chanlist_len; i++) {
2501                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2502                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2503
2504                         if (range == 0)
2505                                 devpriv->i2c_cal_range_bits |=
2506                                         attenuate_bit(channel);
2507                         else
2508                                 devpriv->i2c_cal_range_bits &=
2509                                         ~attenuate_bit(channel);
2510                 }
2511                 /*  update calibration/range i2c register only if necessary,
2512                  *  as it is very slow */
2513                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2514                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2515                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2516                                   sizeof(i2c_data));
2517                 }
2518         }
2519         return 0;
2520 }
2521
2522 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2523                                              unsigned int dma_channel,
2524                                              unsigned int descriptor_bits)
2525 {
2526         struct pcidas64_private *devpriv = dev->private;
2527
2528         /* The transfer size, pci address, and local address registers
2529          * are supposedly unused during chained dma,
2530          * but I have found that left over values from last operation
2531          * occasionally cause problems with transfer of first dma
2532          * block.  Initializing them to zero seems to fix the problem. */
2533         if (dma_channel) {
2534                 writel(0,
2535                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2536                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2537                 writel(0,
2538                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2539                 writel(descriptor_bits,
2540                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2541         } else {
2542                 writel(0,
2543                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2544                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2545                 writel(0,
2546                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2547                 writel(descriptor_bits,
2548                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2549         }
2550 }
2551
2552 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2553 {
2554         const struct pcidas64_board *thisboard = comedi_board(dev);
2555         struct pcidas64_private *devpriv = dev->private;
2556         struct comedi_async *async = s->async;
2557         struct comedi_cmd *cmd = &async->cmd;
2558         uint32_t bits;
2559         unsigned int i;
2560         unsigned long flags;
2561         int retval;
2562
2563         disable_ai_pacing(dev);
2564         abort_dma(dev, 1);
2565
2566         retval = setup_channel_queue(dev, cmd);
2567         if (retval < 0)
2568                 return retval;
2569
2570         /*  make sure internal calibration source is turned off */
2571         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2572
2573         set_ai_pacing(dev, cmd);
2574
2575         setup_sample_counters(dev, cmd);
2576
2577         enable_ai_interrupts(dev, cmd);
2578
2579         spin_lock_irqsave(&dev->spinlock, flags);
2580         /* set mode, allow conversions through software gate */
2581         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2582         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2583         if (thisboard->layout != LAYOUT_4020) {
2584                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2585                 if (cmd->convert_src == TRIG_EXT)
2586                         /*  good old mode 13 */
2587                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2588                 else
2589                         /*  mode 8.  What else could you need? */
2590                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2591         } else {
2592                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2593                 if (cmd->chanlist_len == 4)
2594                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2595                 else if (cmd->chanlist_len == 2)
2596                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2597                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2598                 devpriv->adc_control1_bits |=
2599                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2600                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2601                 devpriv->adc_control1_bits |=
2602                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2603                                                       [cmd->chanlist_len - 1]));
2604         }
2605         writew(devpriv->adc_control1_bits,
2606                devpriv->main_iobase + ADC_CONTROL1_REG);
2607         DEBUG_PRINT("control1 bits 0x%x\n", devpriv->adc_control1_bits);
2608         spin_unlock_irqrestore(&dev->spinlock, flags);
2609
2610         /*  clear adc buffer */
2611         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2612
2613         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2614             thisboard->layout == LAYOUT_4020) {
2615                 devpriv->ai_dma_index = 0;
2616
2617                 /*  set dma transfer size */
2618                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2619                         devpriv->ai_dma_desc[i].transfer_size =
2620                                 cpu_to_le32(dma_transfer_size(dev) *
2621                                             sizeof(uint16_t));
2622
2623                 /*  give location of first dma descriptor */
2624                 load_first_dma_descriptor(dev, 1,
2625                                           devpriv->ai_dma_desc_bus_addr |
2626                                           PLX_DESC_IN_PCI_BIT |
2627                                           PLX_INTR_TERM_COUNT |
2628                                           PLX_XFER_LOCAL_TO_PCI);
2629
2630                 dma_start_sync(dev, 1);
2631         }
2632
2633         if (thisboard->layout == LAYOUT_4020) {
2634                 /* set source for external triggers */
2635                 bits = 0;
2636                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2637                         bits |= EXT_START_TRIG_BNC_BIT;
2638                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2639                         bits |= EXT_STOP_TRIG_BNC_BIT;
2640                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2641         }
2642
2643         spin_lock_irqsave(&dev->spinlock, flags);
2644
2645         /* enable pacing, triggering, etc */
2646         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2647         if (cmd->flags & TRIG_WAKE_EOS)
2648                 bits |= ADC_DMA_DISABLE_BIT;
2649         /*  set start trigger */
2650         if (cmd->start_src == TRIG_EXT) {
2651                 bits |= ADC_START_TRIG_EXT_BITS;
2652                 if (cmd->start_arg & CR_INVERT)
2653                         bits |= ADC_START_TRIG_FALLING_BIT;
2654         } else if (cmd->start_src == TRIG_NOW)
2655                 bits |= ADC_START_TRIG_SOFT_BITS;
2656         if (use_hw_sample_counter(cmd))
2657                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2658         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2659         DEBUG_PRINT("control0 bits 0x%x\n", bits);
2660
2661         devpriv->ai_cmd_running = 1;
2662
2663         spin_unlock_irqrestore(&dev->spinlock, flags);
2664
2665         /*  start acquisition */
2666         if (cmd->start_src == TRIG_NOW) {
2667                 writew(0, devpriv->main_iobase + ADC_START_REG);
2668                 DEBUG_PRINT("soft trig\n");
2669         }
2670
2671         return 0;
2672 }
2673
2674 /* read num_samples from 16 bit wide ai fifo */
2675 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2676 {
2677         struct pcidas64_private *devpriv = dev->private;
2678         struct comedi_subdevice *s = dev->read_subdev;
2679         struct comedi_async *async = s->async;
2680         struct comedi_cmd *cmd = &async->cmd;
2681         unsigned int i;
2682         uint16_t prepost_bits;
2683         int read_segment, read_index, write_segment, write_index;
2684         int num_samples;
2685
2686         do {
2687                 /*  get least significant 15 bits */
2688                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2689                              0x7fff;
2690                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2691                               0x7fff;
2692                 /* Get most significant bits (grey code).
2693                  * Different boards use different code so use a scheme
2694                  * that doesn't depend on encoding.  This read must
2695                  * occur after reading least significant 15 bits to avoid race
2696                  * with fifo switching to next segment. */
2697                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2698
2699                 /* if read and write pointers are not on the same fifo segment,
2700                  * read to the end of the read segment */
2701                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2702                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2703
2704                 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2705                             read_segment, write_segment, read_index,
2706                             write_index);
2707
2708                 if (read_segment != write_segment)
2709                         num_samples =
2710                                 devpriv->ai_fifo_segment_length - read_index;
2711                 else
2712                         num_samples = write_index - read_index;
2713
2714                 if (cmd->stop_src == TRIG_COUNT) {
2715                         if (devpriv->ai_count == 0)
2716                                 break;
2717                         if (num_samples > devpriv->ai_count)
2718                                 num_samples = devpriv->ai_count;
2719
2720                         devpriv->ai_count -= num_samples;
2721                 }
2722
2723                 if (num_samples < 0) {
2724                         dev_err(dev->class_dev,
2725                                 "cb_pcidas64: bug! num_samples < 0\n");
2726                         break;
2727                 }
2728
2729                 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2730
2731                 for (i = 0; i < num_samples; i++) {
2732                         cfc_write_to_buffer(s,
2733                                             readw(devpriv->main_iobase +
2734                                                   ADC_FIFO_REG));
2735                 }
2736
2737         } while (read_segment != write_segment);
2738 }
2739
2740 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2741  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2742  * supports the use of pio for draining the last remaining points from the
2743  * fifo when a data acquisition operation has completed).
2744  */
2745 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2746 {
2747         struct pcidas64_private *devpriv = dev->private;
2748         struct comedi_subdevice *s = dev->read_subdev;
2749         struct comedi_async *async = s->async;
2750         struct comedi_cmd *cmd = &async->cmd;
2751         unsigned int i;
2752         unsigned int max_transfer = 100000;
2753         uint32_t fifo_data;
2754         int write_code =
2755                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2756         int read_code =
2757                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2758
2759         if (cmd->stop_src == TRIG_COUNT) {
2760                 if (max_transfer > devpriv->ai_count)
2761                         max_transfer = devpriv->ai_count;
2762
2763         }
2764         for (i = 0; read_code != write_code && i < max_transfer;) {
2765                 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2766                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2767                 i++;
2768                 if (i < max_transfer) {
2769                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2770                         i++;
2771                 }
2772                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2773                             0x7fff;
2774         }
2775         devpriv->ai_count -= i;
2776 }
2777
2778 /* empty fifo */
2779 static void pio_drain_ai_fifo(struct comedi_device *dev)
2780 {
2781         const struct pcidas64_board *thisboard = comedi_board(dev);
2782
2783         if (thisboard->layout == LAYOUT_4020)
2784                 pio_drain_ai_fifo_32(dev);
2785         else
2786                 pio_drain_ai_fifo_16(dev);
2787 }
2788
2789 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2790 {
2791         const struct pcidas64_board *thisboard = comedi_board(dev);
2792         struct pcidas64_private *devpriv = dev->private;
2793         struct comedi_async *async = dev->read_subdev->async;
2794         uint32_t next_transfer_addr;
2795         int j;
2796         int num_samples = 0;
2797         void __iomem *pci_addr_reg;
2798
2799         if (channel)
2800                 pci_addr_reg =
2801                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2802         else
2803                 pci_addr_reg =
2804                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2805
2806         /*  loop until we have read all the full buffers */
2807         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2808              (next_transfer_addr <
2809               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2810               next_transfer_addr >=
2811               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2812               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2813                 /*  transfer data from dma buffer to comedi buffer */
2814                 num_samples = dma_transfer_size(dev);
2815                 if (async->cmd.stop_src == TRIG_COUNT) {
2816                         if (num_samples > devpriv->ai_count)
2817                                 num_samples = devpriv->ai_count;
2818                         devpriv->ai_count -= num_samples;
2819                 }
2820                 cfc_write_array_to_buffer(dev->read_subdev,
2821                                           devpriv->ai_buffer[devpriv->
2822                                                              ai_dma_index],
2823                                           num_samples * sizeof(uint16_t));
2824                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2825                                         ai_dma_ring_count(thisboard);
2826
2827                 DEBUG_PRINT("next buffer addr 0x%lx\n",
2828                             (unsigned long)devpriv->
2829                             ai_buffer_bus_addr[devpriv->ai_dma_index]);
2830                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2831         }
2832         /* XXX check for dma ring buffer overrun
2833          * (use end-of-chain bit to mark last unused buffer) */
2834 }
2835
2836 static void handle_ai_interrupt(struct comedi_device *dev,
2837                                 unsigned short status,
2838                                 unsigned int plx_status)
2839 {
2840         const struct pcidas64_board *thisboard = comedi_board(dev);
2841         struct pcidas64_private *devpriv = dev->private;
2842         struct comedi_subdevice *s = dev->read_subdev;
2843         struct comedi_async *async = s->async;
2844         struct comedi_cmd *cmd = &async->cmd;
2845         uint8_t dma1_status;
2846         unsigned long flags;
2847
2848         /*  check for fifo overrun */
2849         if (status & ADC_OVERRUN_BIT) {
2850                 comedi_error(dev, "fifo overrun");
2851                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2852         }
2853         /*  spin lock makes sure no one else changes plx dma control reg */
2854         spin_lock_irqsave(&dev->spinlock, flags);
2855         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2856         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2857                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2858                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2859                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2860
2861                 if (dma1_status & PLX_DMA_EN_BIT)
2862                         drain_dma_buffers(dev, 1);
2863
2864                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2865         }
2866         spin_unlock_irqrestore(&dev->spinlock, flags);
2867
2868         if (status & ADC_DONE_BIT)
2869                 DEBUG_PRINT("adc done interrupt\n");
2870
2871         /*  drain fifo with pio */
2872         if ((status & ADC_DONE_BIT) ||
2873             ((cmd->flags & TRIG_WAKE_EOS) &&
2874              (status & ADC_INTR_PENDING_BIT) &&
2875              (thisboard->layout != LAYOUT_4020))) {
2876                 DEBUG_PRINT("pio fifo drain\n");
2877                 spin_lock_irqsave(&dev->spinlock, flags);
2878                 if (devpriv->ai_cmd_running) {
2879                         spin_unlock_irqrestore(&dev->spinlock, flags);
2880                         pio_drain_ai_fifo(dev);
2881                 } else
2882                         spin_unlock_irqrestore(&dev->spinlock, flags);
2883         }
2884         /*  if we are have all the data, then quit */
2885         if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2886             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2887                 async->events |= COMEDI_CB_EOA;
2888         }
2889
2890         cfc_handle_events(dev, s);
2891 }
2892
2893 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2894 {
2895         struct pcidas64_private *devpriv = dev->private;
2896         unsigned int buffer_index;
2897
2898         if (devpriv->ao_dma_index == 0)
2899                 buffer_index = AO_DMA_RING_COUNT - 1;
2900         else
2901                 buffer_index = devpriv->ao_dma_index - 1;
2902         return buffer_index;
2903 }
2904
2905 static int last_ao_dma_load_completed(struct comedi_device *dev)
2906 {
2907         struct pcidas64_private *devpriv = dev->private;
2908         unsigned int buffer_index;
2909         unsigned int transfer_address;
2910         unsigned short dma_status;
2911
2912         buffer_index = prev_ao_dma_index(dev);
2913         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2914         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2915                 return 0;
2916
2917         transfer_address =
2918                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2919         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2920                 return 0;
2921
2922         return 1;
2923 }
2924
2925 static int ao_stopped_by_error(struct comedi_device *dev,
2926                                const struct comedi_cmd *cmd)
2927 {
2928         struct pcidas64_private *devpriv = dev->private;
2929
2930         if (cmd->stop_src == TRIG_NONE)
2931                 return 1;
2932         if (cmd->stop_src == TRIG_COUNT) {
2933                 if (devpriv->ao_count)
2934                         return 1;
2935                 if (last_ao_dma_load_completed(dev) == 0)
2936                         return 1;
2937         }
2938         return 0;
2939 }
2940
2941 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2942                                        unsigned short dma_status)
2943 {
2944         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2945             (dma_status & PLX_DMA_EN_BIT) == 0)
2946                 return 0;
2947         if (last_ao_dma_load_completed(dev))
2948                 return 0;
2949
2950         return 1;
2951 }
2952
2953 static void restart_ao_dma(struct comedi_device *dev)
2954 {
2955         struct pcidas64_private *devpriv = dev->private;
2956         unsigned int dma_desc_bits;
2957
2958         dma_desc_bits =
2959                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2960         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2961         DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
2962         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2963
2964         dma_start_sync(dev, 0);
2965 }
2966
2967 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2968                                        const struct comedi_cmd *cmd)
2969 {
2970         struct pcidas64_private *devpriv = dev->private;
2971         unsigned int num_bytes, buffer_index, prev_buffer_index;
2972         unsigned int next_bits;
2973
2974         buffer_index = devpriv->ao_dma_index;
2975         prev_buffer_index = prev_ao_dma_index(dev);
2976
2977         DEBUG_PRINT("attempting to load ao buffer %i (0x%llx)\n", buffer_index,
2978                     (unsigned long long)devpriv->ao_buffer_bus_addr[
2979                                                                 buffer_index]);
2980
2981         num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
2982         if (num_bytes > DMA_BUFFER_SIZE)
2983                 num_bytes = DMA_BUFFER_SIZE;
2984         if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
2985                 num_bytes = devpriv->ao_count;
2986         num_bytes -= num_bytes % bytes_in_sample;
2987
2988         if (num_bytes == 0)
2989                 return 0;
2990
2991         DEBUG_PRINT("loading %i bytes\n", num_bytes);
2992
2993         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
2994                                                devpriv->
2995                                                ao_buffer[buffer_index],
2996                                                num_bytes);
2997         devpriv->ao_dma_desc[buffer_index].transfer_size =
2998                 cpu_to_le32(num_bytes);
2999         /* set end of chain bit so we catch underruns */
3000         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
3001         next_bits |= PLX_END_OF_CHAIN_BIT;
3002         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3003         /* clear end of chain bit on previous buffer now that we have set it
3004          * for the last buffer */
3005         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
3006         next_bits &= ~PLX_END_OF_CHAIN_BIT;
3007         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3008
3009         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3010         devpriv->ao_count -= num_bytes;
3011
3012         return num_bytes;
3013 }
3014
3015 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3016 {
3017         struct pcidas64_private *devpriv = dev->private;
3018         unsigned int num_bytes;
3019         unsigned int next_transfer_addr;
3020         void __iomem *pci_addr_reg =
3021                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3022         unsigned int buffer_index;
3023
3024         do {
3025                 buffer_index = devpriv->ao_dma_index;
3026                 /* don't overwrite data that hasn't been transferred yet */
3027                 next_transfer_addr = readl(pci_addr_reg);
3028                 if (next_transfer_addr >=
3029                     devpriv->ao_buffer_bus_addr[buffer_index] &&
3030                     next_transfer_addr <
3031                     devpriv->ao_buffer_bus_addr[buffer_index] +
3032                     DMA_BUFFER_SIZE)
3033                         return;
3034                 num_bytes = load_ao_dma_buffer(dev, cmd);
3035         } while (num_bytes >= DMA_BUFFER_SIZE);
3036 }
3037
3038 static void handle_ao_interrupt(struct comedi_device *dev,
3039                                 unsigned short status, unsigned int plx_status)
3040 {
3041         struct pcidas64_private *devpriv = dev->private;
3042         struct comedi_subdevice *s = dev->write_subdev;
3043         struct comedi_async *async;
3044         struct comedi_cmd *cmd;
3045         uint8_t dma0_status;
3046         unsigned long flags;
3047
3048         /* board might not support ao, in which case write_subdev is NULL */
3049         if (s == NULL)
3050                 return;
3051         async = s->async;
3052         cmd = &async->cmd;
3053
3054         /*  spin lock makes sure no one else changes plx dma control reg */
3055         spin_lock_irqsave(&dev->spinlock, flags);
3056         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3057         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3058                 if ((dma0_status & PLX_DMA_EN_BIT) &&
3059                     !(dma0_status & PLX_DMA_DONE_BIT))
3060                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3061                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3062                 else
3063                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3064                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3065                 spin_unlock_irqrestore(&dev->spinlock, flags);
3066                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3067                 if (dma0_status & PLX_DMA_EN_BIT) {
3068                         load_ao_dma(dev, cmd);
3069                         /* try to recover from dma end-of-chain event */
3070                         if (ao_dma_needs_restart(dev, dma0_status))
3071                                 restart_ao_dma(dev);
3072                 }
3073                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3074         } else {
3075                 spin_unlock_irqrestore(&dev->spinlock, flags);
3076         }
3077
3078         if ((status & DAC_DONE_BIT)) {
3079                 async->events |= COMEDI_CB_EOA;
3080                 if (ao_stopped_by_error(dev, cmd))
3081                         async->events |= COMEDI_CB_ERROR;
3082                 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3083                             readl(devpriv->plx9080_iobase +
3084                                   PLX_DMA0_DESCRIPTOR_REG));
3085                 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3086                             readl(devpriv->plx9080_iobase +
3087                                   PLX_DMA0_PCI_ADDRESS_REG));
3088         }
3089         cfc_handle_events(dev, s);
3090 }
3091
3092 static irqreturn_t handle_interrupt(int irq, void *d)
3093 {
3094         struct comedi_device *dev = d;
3095         struct pcidas64_private *devpriv = dev->private;
3096         unsigned short status;
3097         uint32_t plx_status;
3098         uint32_t plx_bits;
3099
3100         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3101         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3102
3103         DEBUG_PRINT("hw status 0x%x, plx status 0x%x\n", status, plx_status);
3104
3105         /* an interrupt before all the postconfig stuff gets done could
3106          * cause a NULL dereference if we continue through the
3107          * interrupt handler */
3108         if (dev->attached == 0) {
3109                 DEBUG_PRINT("premature interrupt, ignoring\n");
3110                 return IRQ_HANDLED;
3111         }
3112         handle_ai_interrupt(dev, status, plx_status);
3113         handle_ao_interrupt(dev, status, plx_status);
3114
3115         /*  clear possible plx9080 interrupt sources */
3116         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3117                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3118                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3119                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3120         }
3121
3122         DEBUG_PRINT("exiting handler\n");
3123
3124         return IRQ_HANDLED;
3125 }
3126
3127 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3128 {
3129         struct pcidas64_private *devpriv = dev->private;
3130         unsigned long flags;
3131
3132         spin_lock_irqsave(&dev->spinlock, flags);
3133         if (devpriv->ai_cmd_running == 0) {
3134                 spin_unlock_irqrestore(&dev->spinlock, flags);
3135                 return 0;
3136         }
3137         devpriv->ai_cmd_running = 0;
3138         spin_unlock_irqrestore(&dev->spinlock, flags);
3139
3140         disable_ai_pacing(dev);
3141
3142         abort_dma(dev, 1);
3143
3144         DEBUG_PRINT("ai canceled\n");
3145         return 0;
3146 }
3147
3148 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3149                     struct comedi_insn *insn, unsigned int *data)
3150 {
3151         const struct pcidas64_board *thisboard = comedi_board(dev);
3152         struct pcidas64_private *devpriv = dev->private;
3153         int chan = CR_CHAN(insn->chanspec);
3154         int range = CR_RANGE(insn->chanspec);
3155
3156         /*  do some initializing */
3157         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3158
3159         /*  set range */
3160         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3161         writew(devpriv->dac_control1_bits,
3162                devpriv->main_iobase + DAC_CONTROL1_REG);
3163
3164         /*  write to channel */
3165         if (thisboard->layout == LAYOUT_4020) {
3166                 writew(data[0] & 0xff,
3167                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3168                 writew((data[0] >> 8) & 0xf,
3169                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3170         } else {
3171                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3172         }
3173
3174         /*  remember output value */
3175         devpriv->ao_value[chan] = data[0];
3176
3177         return 1;
3178 }
3179
3180 static int ao_readback_insn(struct comedi_device *dev,
3181                             struct comedi_subdevice *s,
3182                             struct comedi_insn *insn, unsigned int *data)
3183 {
3184         struct pcidas64_private *devpriv = dev->private;
3185
3186         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3187
3188         return 1;
3189 }
3190
3191 static void set_dac_control0_reg(struct comedi_device *dev,
3192                                  const struct comedi_cmd *cmd)
3193 {
3194         struct pcidas64_private *devpriv = dev->private;
3195         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3196                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3197
3198         if (cmd->start_src == TRIG_EXT) {
3199                 bits |= WAVEFORM_TRIG_EXT_BITS;
3200                 if (cmd->start_arg & CR_INVERT)
3201                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3202         } else {
3203                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3204         }
3205         if (cmd->scan_begin_src == TRIG_EXT) {
3206                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3207                 if (cmd->scan_begin_arg & CR_INVERT)
3208                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3209         }
3210         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3211 }
3212
3213 static void set_dac_control1_reg(struct comedi_device *dev,
3214                                  const struct comedi_cmd *cmd)
3215 {
3216         struct pcidas64_private *devpriv = dev->private;
3217         int i;
3218
3219         for (i = 0; i < cmd->chanlist_len; i++) {
3220                 int channel, range;
3221
3222                 channel = CR_CHAN(cmd->chanlist[i]);
3223                 range = CR_RANGE(cmd->chanlist[i]);
3224                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3225                                    range);
3226         }
3227         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3228         writew(devpriv->dac_control1_bits,
3229                devpriv->main_iobase + DAC_CONTROL1_REG);
3230 }
3231
3232 static void set_dac_select_reg(struct comedi_device *dev,
3233                                const struct comedi_cmd *cmd)
3234 {
3235         struct pcidas64_private *devpriv = dev->private;
3236         uint16_t bits;
3237         unsigned int first_channel, last_channel;
3238
3239         first_channel = CR_CHAN(cmd->chanlist[0]);
3240         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3241         if (last_channel < first_channel)
3242                 comedi_error(dev, "bug! last ao channel < first ao channel");
3243
3244         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3245
3246         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3247 }
3248
3249 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3250 {
3251         return get_divisor(ns, flags) - 2;
3252 }
3253
3254 static void set_dac_interval_regs(struct comedi_device *dev,
3255                                   const struct comedi_cmd *cmd)
3256 {
3257         struct pcidas64_private *devpriv = dev->private;
3258         unsigned int divisor;
3259
3260         if (cmd->scan_begin_src != TRIG_TIMER)
3261                 return;
3262
3263         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3264         if (divisor > max_counter_value) {
3265                 comedi_error(dev, "bug! ao divisor too big");
3266                 divisor = max_counter_value;
3267         }
3268         writew(divisor & 0xffff,
3269                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3270         writew((divisor >> 16) & 0xff,
3271                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3272 }
3273
3274 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3275 {
3276         struct pcidas64_private *devpriv = dev->private;
3277         unsigned int num_bytes;
3278         int i;
3279
3280         /* clear queue pointer too, since external queue has
3281          * weird interactions with ao fifo */
3282         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3283         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3284
3285         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3286         if (cmd->stop_src == TRIG_COUNT &&
3287             num_bytes / bytes_in_sample > devpriv->ao_count)
3288                 num_bytes = devpriv->ao_count * bytes_in_sample;
3289         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3290                                                devpriv->ao_bounce_buffer,
3291                                                num_bytes);
3292         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3293                 writew(devpriv->ao_bounce_buffer[i],
3294                        devpriv->main_iobase + DAC_FIFO_REG);
3295         }
3296         devpriv->ao_count -= num_bytes / bytes_in_sample;
3297         if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3298                 return 0;
3299         num_bytes = load_ao_dma_buffer(dev, cmd);
3300         if (num_bytes == 0)
3301                 return -1;
3302         if (num_bytes >= DMA_BUFFER_SIZE) ;
3303         load_ao_dma(dev, cmd);
3304
3305         dma_start_sync(dev, 0);
3306
3307         return 0;
3308 }
3309
3310 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3311 {
3312         const struct pcidas64_board *thisboard = comedi_board(dev);
3313
3314         if (dev->read_subdev->busy)
3315                 return 0;
3316         if (thisboard->layout == LAYOUT_4020)
3317                 return 0;
3318         else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3319                 return 0;
3320         return 1;
3321 }
3322
3323 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3324                       unsigned int trig_num)
3325 {
3326         struct pcidas64_private *devpriv = dev->private;
3327         struct comedi_cmd *cmd = &s->async->cmd;
3328         int retval;
3329
3330         if (trig_num != 0)
3331                 return -EINVAL;
3332
3333         retval = prep_ao_dma(dev, cmd);
3334         if (retval < 0)
3335                 return -EPIPE;
3336
3337         set_dac_control0_reg(dev, cmd);
3338
3339         if (cmd->start_src == TRIG_INT)
3340                 writew(0, devpriv->main_iobase + DAC_START_REG);
3341
3342         s->async->inttrig = NULL;
3343
3344         return 0;
3345 }
3346
3347 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3348 {
3349         struct pcidas64_private *devpriv = dev->private;
3350         struct comedi_cmd *cmd = &s->async->cmd;
3351
3352         if (external_ai_queue_in_use(dev)) {
3353                 warn_external_queue(dev);
3354                 return -EBUSY;
3355         }
3356         /* disable analog output system during setup */
3357         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3358
3359         devpriv->ao_dma_index = 0;
3360         devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3361
3362         set_dac_select_reg(dev, cmd);
3363         set_dac_interval_regs(dev, cmd);
3364         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3365                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3366
3367         set_dac_control1_reg(dev, cmd);
3368         s->async->inttrig = ao_inttrig;
3369
3370         return 0;
3371 }
3372
3373 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3374                       struct comedi_cmd *cmd)
3375 {
3376         const struct pcidas64_board *thisboard = comedi_board(dev);
3377         int err = 0;
3378         unsigned int tmp_arg;
3379         int i;
3380
3381         /* Step 1 : check if triggers are trivially valid */
3382
3383         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3384         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3385                                      TRIG_TIMER | TRIG_EXT);
3386         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3387         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3388         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3389
3390         if (err)
3391                 return 1;
3392
3393         /* Step 2a : make sure trigger sources are unique */
3394
3395         err |= cfc_check_trigger_is_unique(cmd->start_src);
3396         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3397
3398         /* Step 2b : and mutually compatible */
3399
3400         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3401                 err |= -EINVAL;
3402         if (cmd->stop_src != TRIG_COUNT &&
3403             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3404                 err |= -EINVAL;
3405
3406         if (err)
3407                 return 2;
3408
3409         /* Step 3: check if arguments are trivially valid */
3410
3411         if (cmd->scan_begin_src == TRIG_TIMER) {
3412                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3413                                                  thisboard->ao_scan_speed);
3414                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3415                     max_counter_value) {
3416                         cmd->scan_begin_arg = (max_counter_value + 2) *
3417                                               TIMER_BASE;
3418                         err |= -EINVAL;
3419                 }
3420         }
3421
3422         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3423         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3424
3425         if (err)
3426                 return 3;
3427
3428         /* step 4: fix up any arguments */
3429
3430         if (cmd->scan_begin_src == TRIG_TIMER) {
3431                 tmp_arg = cmd->scan_begin_arg;
3432                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3433                                                   cmd->flags) * TIMER_BASE;
3434                 if (tmp_arg != cmd->scan_begin_arg)
3435                         err++;
3436         }
3437
3438         if (err)
3439                 return 4;
3440
3441         if (cmd->chanlist) {
3442                 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3443                 for (i = 1; i < cmd->chanlist_len; i++) {
3444                         if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3445                                 comedi_error(dev,
3446                                              "chanlist must use consecutive channels");
3447                                 err++;
3448                                 break;
3449                         }
3450                 }
3451         }
3452
3453         if (err)
3454                 return 5;
3455
3456         return 0;
3457 }
3458
3459 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3460 {
3461         struct pcidas64_private *devpriv = dev->private;
3462
3463         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3464         abort_dma(dev, 0);
3465         return 0;
3466 }
3467
3468 static int dio_callback(int dir, int port, int data, unsigned long arg)
3469 {
3470         void __iomem *iobase = (void __iomem *)arg;
3471         if (dir) {
3472                 writeb(data, iobase + port);
3473                 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3474                 return 0;
3475         } else {
3476                 return readb(iobase + port);
3477         }
3478 }
3479
3480 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3481 {
3482         void __iomem *iobase = (void __iomem *)arg;
3483         if (dir) {
3484                 writew(data, iobase + 2 * port);
3485                 return 0;
3486         } else {
3487                 return readw(iobase + 2 * port);
3488         }
3489 }
3490
3491 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3492                     struct comedi_insn *insn, unsigned int *data)
3493 {
3494         struct pcidas64_private *devpriv = dev->private;
3495         unsigned int bits;
3496
3497         bits = readb(devpriv->dio_counter_iobase + DI_REG);
3498         bits &= 0xf;
3499         data[1] = bits;
3500         data[0] = 0;
3501
3502         return insn->n;
3503 }
3504
3505 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3506                     struct comedi_insn *insn, unsigned int *data)
3507 {
3508         struct pcidas64_private *devpriv = dev->private;
3509
3510         data[0] &= 0xf;
3511         /*  zero bits we are going to change */
3512         s->state &= ~data[0];
3513         /*  set new bits */
3514         s->state |= data[0] & data[1];
3515
3516         writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3517
3518         data[1] = s->state;
3519
3520         return insn->n;
3521 }
3522
3523 static int dio_60xx_config_insn(struct comedi_device *dev,
3524                                 struct comedi_subdevice *s,
3525                                 struct comedi_insn *insn, unsigned int *data)
3526 {
3527         struct pcidas64_private *devpriv = dev->private;
3528         unsigned int mask;
3529
3530         mask = 1 << CR_CHAN(insn->chanspec);
3531
3532         switch (data[0]) {
3533         case INSN_CONFIG_DIO_INPUT:
3534                 s->io_bits &= ~mask;
3535                 break;
3536         case INSN_CONFIG_DIO_OUTPUT:
3537                 s->io_bits |= mask;
3538                 break;
3539         case INSN_CONFIG_DIO_QUERY:
3540                 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3541                 return 2;
3542         default:
3543                 return -EINVAL;
3544         }
3545
3546         writeb(s->io_bits,
3547                devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3548
3549         return 1;
3550 }
3551
3552 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3553                           struct comedi_insn *insn, unsigned int *data)
3554 {
3555         struct pcidas64_private *devpriv = dev->private;
3556
3557         if (data[0]) {
3558                 s->state &= ~data[0];
3559                 s->state |= (data[0] & data[1]);
3560                 writeb(s->state,
3561                        devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3562         }
3563
3564         data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3565
3566         return insn->n;
3567 }
3568
3569 /* pci-6025 8800 caldac:
3570  * address 0 == dac channel 0 offset
3571  * address 1 == dac channel 0 gain
3572  * address 2 == dac channel 1 offset
3573  * address 3 == dac channel 1 gain
3574  * address 4 == fine adc offset
3575  * address 5 == coarse adc offset
3576  * address 6 == coarse adc gain
3577  * address 7 == fine adc gain
3578  */
3579 /* pci-6402/16 uses all 8 channels for dac:
3580  * address 0 == dac channel 0 fine gain
3581  * address 1 == dac channel 0 coarse gain
3582  * address 2 == dac channel 0 coarse offset
3583  * address 3 == dac channel 1 coarse offset
3584  * address 4 == dac channel 1 fine gain
3585  * address 5 == dac channel 1 coarse gain
3586  * address 6 == dac channel 0 fine offset
3587  * address 7 == dac channel 1 fine offset
3588 */
3589
3590 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3591                              uint8_t value)
3592 {
3593         struct pcidas64_private *devpriv = dev->private;
3594         static const int num_caldac_channels = 8;
3595         static const int bitstream_length = 11;
3596         unsigned int bitstream = ((address & 0x7) << 8) | value;
3597         unsigned int bit, register_bits;
3598         static const int caldac_8800_udelay = 1;
3599
3600         if (address >= num_caldac_channels) {
3601                 comedi_error(dev, "illegal caldac channel");
3602                 return -1;
3603         }
3604         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3605                 register_bits = 0;
3606                 if (bitstream & bit)
3607                         register_bits |= SERIAL_DATA_IN_BIT;
3608                 udelay(caldac_8800_udelay);
3609                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3610                 register_bits |= SERIAL_CLOCK_BIT;
3611                 udelay(caldac_8800_udelay);
3612                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3613         }
3614         udelay(caldac_8800_udelay);
3615         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3616         udelay(caldac_8800_udelay);
3617         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3618         udelay(caldac_8800_udelay);
3619         return 0;
3620 }
3621
3622 /* 4020 caldacs */
3623 static int caldac_i2c_write(struct comedi_device *dev,
3624                             unsigned int caldac_channel, unsigned int value)
3625 {
3626         uint8_t serial_bytes[3];
3627         uint8_t i2c_addr;
3628         enum pointer_bits {
3629                 /*  manual has gain and offset bits switched */
3630                 OFFSET_0_2 = 0x1,
3631                 GAIN_0_2 = 0x2,
3632                 OFFSET_1_3 = 0x4,
3633                 GAIN_1_3 = 0x8,
3634         };
3635         enum data_bits {
3636                 NOT_CLEAR_REGISTERS = 0x20,
3637         };
3638
3639         switch (caldac_channel) {
3640         case 0:         /*  chan 0 offset */
3641                 i2c_addr = CALDAC0_I2C_ADDR;
3642                 serial_bytes[0] = OFFSET_0_2;
3643                 break;
3644         case 1:         /*  chan 1 offset */
3645                 i2c_addr = CALDAC0_I2C_ADDR;
3646                 serial_bytes[0] = OFFSET_1_3;
3647                 break;
3648         case 2:         /*  chan 2 offset */
3649                 i2c_addr = CALDAC1_I2C_ADDR;
3650                 serial_bytes[0] = OFFSET_0_2;
3651                 break;
3652         case 3:         /*  chan 3 offset */
3653                 i2c_addr = CALDAC1_I2C_ADDR;
3654                 serial_bytes[0] = OFFSET_1_3;
3655                 break;
3656         case 4:         /*  chan 0 gain */
3657                 i2c_addr = CALDAC0_I2C_ADDR;
3658                 serial_bytes[0] = GAIN_0_2;
3659                 break;
3660         case 5:         /*  chan 1 gain */
3661                 i2c_addr = CALDAC0_I2C_ADDR;
3662                 serial_bytes[0] = GAIN_1_3;
3663                 break;
3664         case 6:         /*  chan 2 gain */
3665                 i2c_addr = CALDAC1_I2C_ADDR;
3666                 serial_bytes[0] = GAIN_0_2;
3667                 break;
3668         case 7:         /*  chan 3 gain */
3669                 i2c_addr = CALDAC1_I2C_ADDR;
3670                 serial_bytes[0] = GAIN_1_3;
3671                 break;
3672         default:
3673                 comedi_error(dev, "invalid caldac channel\n");
3674                 return -1;
3675                 break;
3676         }
3677         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3678         serial_bytes[2] = value & 0xff;
3679         i2c_write(dev, i2c_addr, serial_bytes, 3);
3680         return 0;
3681 }
3682
3683 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3684                          unsigned int value)
3685 {
3686         const struct pcidas64_board *thisboard = comedi_board(dev);
3687         struct pcidas64_private *devpriv = dev->private;
3688
3689         devpriv->caldac_state[channel] = value;
3690
3691         switch (thisboard->layout) {
3692         case LAYOUT_60XX:
3693         case LAYOUT_64XX:
3694                 caldac_8800_write(dev, channel, value);
3695                 break;
3696         case LAYOUT_4020:
3697                 caldac_i2c_write(dev, channel, value);
3698                 break;
3699         default:
3700                 break;
3701         }
3702 }
3703
3704 static int calib_write_insn(struct comedi_device *dev,
3705                             struct comedi_subdevice *s,
3706                             struct comedi_insn *insn, unsigned int *data)
3707 {
3708         struct pcidas64_private *devpriv = dev->private;
3709         int channel = CR_CHAN(insn->chanspec);
3710
3711         /* return immediately if setting hasn't changed, since
3712          * programming these things is slow */
3713         if (devpriv->caldac_state[channel] == data[0])
3714                 return 1;
3715
3716         caldac_write(dev, channel, data[0]);
3717
3718         return 1;
3719 }
3720
3721 static int calib_read_insn(struct comedi_device *dev,
3722                            struct comedi_subdevice *s, struct comedi_insn *insn,
3723                            unsigned int *data)
3724 {
3725         struct pcidas64_private *devpriv = dev->private;
3726         unsigned int channel = CR_CHAN(insn->chanspec);
3727
3728         data[0] = devpriv->caldac_state[channel];
3729
3730         return 1;
3731 }
3732
3733 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3734                          unsigned int value)
3735 {
3736         struct pcidas64_private *devpriv = dev->private;
3737         static const int bitstream_length = 10;
3738         unsigned int bit, register_bits;
3739         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3740         static const int ad8402_udelay = 1;
3741
3742         devpriv->ad8402_state[channel] = value;
3743
3744         register_bits = SELECT_8402_64XX_BIT;
3745         udelay(ad8402_udelay);
3746         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3747
3748         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3749                 if (bitstream & bit)
3750                         register_bits |= SERIAL_DATA_IN_BIT;
3751                 else
3752                         register_bits &= ~SERIAL_DATA_IN_BIT;
3753                 udelay(ad8402_udelay);
3754                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3755                 udelay(ad8402_udelay);
3756                 writew(register_bits | SERIAL_CLOCK_BIT,
3757                        devpriv->main_iobase + CALIBRATION_REG);
3758         }
3759
3760         udelay(ad8402_udelay);
3761         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3762 }
3763
3764 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3765 static int ad8402_write_insn(struct comedi_device *dev,
3766                              struct comedi_subdevice *s,
3767                              struct comedi_insn *insn, unsigned int *data)
3768 {
3769         struct pcidas64_private *devpriv = dev->private;
3770         int channel = CR_CHAN(insn->chanspec);
3771
3772         /* return immediately if setting hasn't changed, since
3773          * programming these things is slow */
3774         if (devpriv->ad8402_state[channel] == data[0])
3775                 return 1;
3776
3777         devpriv->ad8402_state[channel] = data[0];
3778
3779         ad8402_write(dev, channel, data[0]);
3780
3781         return 1;
3782 }
3783
3784 static int ad8402_read_insn(struct comedi_device *dev,
3785                             struct comedi_subdevice *s,
3786                             struct comedi_insn *insn, unsigned int *data)
3787 {
3788         struct pcidas64_private *devpriv = dev->private;
3789         unsigned int channel = CR_CHAN(insn->chanspec);
3790
3791         data[0] = devpriv->ad8402_state[channel];
3792
3793         return 1;
3794 }
3795
3796 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3797 {
3798         struct pcidas64_private *devpriv = dev->private;
3799         static const int bitstream_length = 11;
3800         static const int read_command = 0x6;
3801         unsigned int bitstream = (read_command << 8) | address;
3802         unsigned int bit;
3803         void __iomem * const plx_control_addr =
3804                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3805         uint16_t value;
3806         static const int value_length = 16;
3807         static const int eeprom_udelay = 1;
3808
3809         udelay(eeprom_udelay);
3810         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3811         /*  make sure we don't send anything to the i2c bus on 4020 */
3812         devpriv->plx_control_bits |= CTL_USERO;
3813         writel(devpriv->plx_control_bits, plx_control_addr);
3814         /*  activate serial eeprom */
3815         udelay(eeprom_udelay);
3816         devpriv->plx_control_bits |= CTL_EE_CS;
3817         writel(devpriv->plx_control_bits, plx_control_addr);
3818
3819         /*  write read command and desired memory address */
3820         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3821                 /*  set bit to be written */
3822                 udelay(eeprom_udelay);
3823                 if (bitstream & bit)
3824                         devpriv->plx_control_bits |= CTL_EE_W;
3825                 else
3826                         devpriv->plx_control_bits &= ~CTL_EE_W;
3827                 writel(devpriv->plx_control_bits, plx_control_addr);
3828                 /*  clock in bit */
3829                 udelay(eeprom_udelay);
3830                 devpriv->plx_control_bits |= CTL_EE_CLK;
3831                 writel(devpriv->plx_control_bits, plx_control_addr);
3832                 udelay(eeprom_udelay);
3833                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3834                 writel(devpriv->plx_control_bits, plx_control_addr);
3835         }
3836         /*  read back value from eeprom memory location */
3837         value = 0;
3838         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3839                 /*  clock out bit */
3840                 udelay(eeprom_udelay);
3841                 devpriv->plx_control_bits |= CTL_EE_CLK;
3842                 writel(devpriv->plx_control_bits, plx_control_addr);
3843                 udelay(eeprom_udelay);
3844                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3845                 writel(devpriv->plx_control_bits, plx_control_addr);
3846                 udelay(eeprom_udelay);
3847                 if (readl(plx_control_addr) & CTL_EE_R)
3848                         value |= bit;
3849         }
3850
3851         /*  deactivate eeprom serial input */
3852         udelay(eeprom_udelay);
3853         devpriv->plx_control_bits &= ~CTL_EE_CS;
3854         writel(devpriv->plx_control_bits, plx_control_addr);
3855
3856         return value;
3857 }
3858
3859 static int eeprom_read_insn(struct comedi_device *dev,
3860                             struct comedi_subdevice *s,
3861                             struct comedi_insn *insn, unsigned int *data)
3862 {
3863         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3864
3865         return 1;
3866 }
3867
3868 /* Allocate and initialize the subdevice structures.
3869  */
3870 static int setup_subdevices(struct comedi_device *dev)
3871 {
3872         const struct pcidas64_board *thisboard = comedi_board(dev);
3873         struct pcidas64_private *devpriv = dev->private;
3874         struct comedi_subdevice *s;
3875         void __iomem *dio_8255_iobase;
3876         int i;
3877         int ret;
3878
3879         ret = comedi_alloc_subdevices(dev, 10);
3880         if (ret)
3881                 return ret;
3882
3883         s = &dev->subdevices[0];
3884         /* analog input subdevice */
3885         dev->read_subdev = s;
3886         s->type = COMEDI_SUBD_AI;
3887         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3888         if (thisboard->layout == LAYOUT_60XX)
3889                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3890         else if (thisboard->layout == LAYOUT_64XX)
3891                 s->subdev_flags |= SDF_DIFF;
3892         /* XXX Number of inputs in differential mode is ignored */
3893         s->n_chan = thisboard->ai_se_chans;
3894         s->len_chanlist = 0x2000;
3895         s->maxdata = (1 << thisboard->ai_bits) - 1;
3896         s->range_table = thisboard->ai_range_table;
3897         s->insn_read = ai_rinsn;
3898         s->insn_config = ai_config_insn;
3899         s->do_cmd = ai_cmd;
3900         s->do_cmdtest = ai_cmdtest;
3901         s->cancel = ai_cancel;
3902         if (thisboard->layout == LAYOUT_4020) {
3903                 uint8_t data;
3904                 /*  set adc to read from inputs
3905                  *  (not internal calibration sources) */
3906                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3907                 /*  set channels to +-5 volt input ranges */
3908                 for (i = 0; i < s->n_chan; i++)
3909                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3910                 data = devpriv->i2c_cal_range_bits;
3911                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3912         }
3913
3914         /* analog output subdevice */
3915         s = &dev->subdevices[1];
3916         if (thisboard->ao_nchan) {
3917                 s->type = COMEDI_SUBD_AO;
3918                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3919                                   SDF_GROUND | SDF_CMD_WRITE;
3920                 s->n_chan = thisboard->ao_nchan;
3921                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3922                 s->range_table = thisboard->ao_range_table;
3923                 s->insn_read = ao_readback_insn;
3924                 s->insn_write = ao_winsn;
3925                 if (ao_cmd_is_supported(thisboard)) {
3926                         dev->write_subdev = s;
3927                         s->do_cmdtest = ao_cmdtest;
3928                         s->do_cmd = ao_cmd;
3929                         s->len_chanlist = thisboard->ao_nchan;
3930                         s->cancel = ao_cancel;
3931                 }
3932         } else {
3933                 s->type = COMEDI_SUBD_UNUSED;
3934         }
3935
3936         /*  digital input */
3937         s = &dev->subdevices[2];
3938         if (thisboard->layout == LAYOUT_64XX) {
3939                 s->type = COMEDI_SUBD_DI;
3940                 s->subdev_flags = SDF_READABLE;
3941                 s->n_chan = 4;
3942                 s->maxdata = 1;
3943                 s->range_table = &range_digital;
3944                 s->insn_bits = di_rbits;
3945         } else
3946                 s->type = COMEDI_SUBD_UNUSED;
3947
3948         /*  digital output */
3949         if (thisboard->layout == LAYOUT_64XX) {
3950                 s = &dev->subdevices[3];
3951                 s->type = COMEDI_SUBD_DO;
3952                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3953                 s->n_chan = 4;
3954                 s->maxdata = 1;
3955                 s->range_table = &range_digital;
3956                 s->insn_bits = do_wbits;
3957         } else
3958                 s->type = COMEDI_SUBD_UNUSED;
3959
3960         /* 8255 */
3961         s = &dev->subdevices[4];
3962         if (thisboard->has_8255) {
3963                 if (thisboard->layout == LAYOUT_4020) {
3964                         dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3965                         subdev_8255_init(dev, s, dio_callback_4020,
3966                                          (unsigned long)dio_8255_iobase);
3967                 } else {
3968                         dio_8255_iobase =
3969                                 devpriv->dio_counter_iobase + DIO_8255_OFFSET;
3970                         subdev_8255_init(dev, s, dio_callback,
3971                                          (unsigned long)dio_8255_iobase);
3972                 }
3973         } else
3974                 s->type = COMEDI_SUBD_UNUSED;
3975
3976         /*  8 channel dio for 60xx */
3977         s = &dev->subdevices[5];
3978         if (thisboard->layout == LAYOUT_60XX) {
3979                 s->type = COMEDI_SUBD_DIO;
3980                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3981                 s->n_chan = 8;
3982                 s->maxdata = 1;
3983                 s->range_table = &range_digital;
3984                 s->insn_config = dio_60xx_config_insn;
3985                 s->insn_bits = dio_60xx_wbits;
3986         } else
3987                 s->type = COMEDI_SUBD_UNUSED;
3988
3989         /*  caldac */
3990         s = &dev->subdevices[6];
3991         s->type = COMEDI_SUBD_CALIB;
3992         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3993         s->n_chan = 8;
3994         if (thisboard->layout == LAYOUT_4020)
3995                 s->maxdata = 0xfff;
3996         else
3997                 s->maxdata = 0xff;
3998         s->insn_read = calib_read_insn;
3999         s->insn_write = calib_write_insn;
4000         for (i = 0; i < s->n_chan; i++)
4001                 caldac_write(dev, i, s->maxdata / 2);
4002
4003         /*  2 channel ad8402 potentiometer */
4004         s = &dev->subdevices[7];
4005         if (thisboard->layout == LAYOUT_64XX) {
4006                 s->type = COMEDI_SUBD_CALIB;
4007                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4008                 s->n_chan = 2;
4009                 s->insn_read = ad8402_read_insn;
4010                 s->insn_write = ad8402_write_insn;
4011                 s->maxdata = 0xff;
4012                 for (i = 0; i < s->n_chan; i++)
4013                         ad8402_write(dev, i, s->maxdata / 2);
4014         } else
4015                 s->type = COMEDI_SUBD_UNUSED;
4016
4017         /* serial EEPROM, if present */
4018         s = &dev->subdevices[8];
4019         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
4020                 s->type = COMEDI_SUBD_MEMORY;
4021                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4022                 s->n_chan = 128;
4023                 s->maxdata = 0xffff;
4024                 s->insn_read = eeprom_read_insn;
4025         } else
4026                 s->type = COMEDI_SUBD_UNUSED;
4027
4028         /*  user counter subd XXX */
4029         s = &dev->subdevices[9];
4030         s->type = COMEDI_SUBD_UNUSED;
4031
4032         return 0;
4033 }
4034
4035 static const struct pcidas64_board
4036 *cb_pcidas64_find_pci_board(struct pci_dev *pcidev)
4037 {
4038         unsigned int i;
4039
4040         for (i = 0; i < ARRAY_SIZE(pcidas64_boards); i++)
4041                 if (pcidev->device == pcidas64_boards[i].device_id)
4042                         return &pcidas64_boards[i];
4043         return NULL;
4044 }
4045
4046 static int auto_attach(struct comedi_device *dev,
4047                                  unsigned long context_unused)
4048 {
4049         const struct pcidas64_board *thisboard;
4050         struct pcidas64_private *devpriv;
4051         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4052         uint32_t local_range, local_decode;
4053         int retval;
4054
4055         dev->board_ptr = cb_pcidas64_find_pci_board(pcidev);
4056         if (!dev->board_ptr) {
4057                 dev_err(dev->class_dev,
4058                         "cb_pcidas64: does not support pci %s\n",
4059                         pci_name(pcidev));
4060                 return -EINVAL;
4061         }
4062         thisboard = comedi_board(dev);
4063
4064         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4065         if (!devpriv)
4066                 return -ENOMEM;
4067         dev->private = devpriv;
4068
4069         if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
4070                 dev_warn(dev->class_dev,
4071                          "failed to enable PCI device and request regions\n");
4072                 return -EIO;
4073         }
4074         pci_set_master(pcidev);
4075
4076         /* Initialize dev->board_name */
4077         dev->board_name = thisboard->name;
4078
4079         dev->iobase = pci_resource_start(pcidev, MAIN_BADDRINDEX);
4080
4081         devpriv->plx9080_phys_iobase =
4082                 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
4083         devpriv->main_phys_iobase = dev->iobase;
4084         devpriv->dio_counter_phys_iobase =
4085                 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
4086
4087         /*  remap, won't work with 2.0 kernels but who cares */
4088         devpriv->plx9080_iobase =
4089                 ioremap(devpriv->plx9080_phys_iobase,
4090                         pci_resource_len(pcidev, PLX9080_BADDRINDEX));
4091         devpriv->main_iobase =
4092                 ioremap(devpriv->main_phys_iobase,
4093                         pci_resource_len(pcidev, MAIN_BADDRINDEX));
4094         devpriv->dio_counter_iobase =
4095                 ioremap(devpriv->dio_counter_phys_iobase,
4096                         pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
4097
4098         if (!devpriv->plx9080_iobase || !devpriv->main_iobase
4099             || !devpriv->dio_counter_iobase) {
4100                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4101                 return -ENOMEM;
4102         }
4103
4104         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
4105         DEBUG_PRINT(" main remapped to 0x%p\n", devpriv->main_iobase);
4106         DEBUG_PRINT(" diocounter remapped to 0x%p\n",
4107                     devpriv->dio_counter_iobase);
4108
4109         /*  figure out what local addresses are */
4110         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4111                       LRNG_MEM_MASK;
4112         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4113                        local_range & LMAP_MEM_MASK;
4114         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4115                                   ~local_range) | local_decode;
4116         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4117                       LRNG_MEM_MASK;
4118         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4119                        local_range & LMAP_MEM_MASK;
4120         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4121                                   ~local_range) | local_decode;
4122
4123         DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv->local0_iobase);
4124         DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv->local1_iobase);
4125
4126         retval = alloc_and_init_dma_members(dev);
4127         if (retval < 0)
4128                 return retval;
4129
4130         devpriv->hw_revision =
4131                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4132         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4133                 devpriv->hw_revision);
4134         init_plx9080(dev);
4135         init_stc_registers(dev);
4136         /*  get irq */
4137         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4138                         "cb_pcidas64", dev)) {
4139                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4140                         pcidev->irq);
4141                 return -EINVAL;
4142         }
4143         dev->irq = pcidev->irq;
4144         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4145
4146         retval = setup_subdevices(dev);
4147         if (retval < 0)
4148                 return retval;
4149
4150         return 0;
4151 }
4152
4153 static void detach(struct comedi_device *dev)
4154 {
4155         const struct pcidas64_board *thisboard = comedi_board(dev);
4156         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4157         struct pcidas64_private *devpriv = dev->private;
4158         unsigned int i;
4159
4160         if (dev->irq)
4161                 free_irq(dev->irq, dev);
4162         if (devpriv) {
4163                 if (pcidev) {
4164                         if (devpriv->plx9080_iobase) {
4165                                 disable_plx_interrupts(dev);
4166                                 iounmap(devpriv->plx9080_iobase);
4167                         }
4168                         if (devpriv->main_iobase)
4169                                 iounmap(devpriv->main_iobase);
4170                         if (devpriv->dio_counter_iobase)
4171                                 iounmap(devpriv->dio_counter_iobase);
4172                         /*  free pci dma buffers */
4173                         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4174                                 if (devpriv->ai_buffer[i])
4175                                         pci_free_consistent(pcidev,
4176                                                 DMA_BUFFER_SIZE,
4177                                                 devpriv->ai_buffer[i],
4178                                                 devpriv->ai_buffer_bus_addr[i]);
4179                         }
4180                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4181                                 if (devpriv->ao_buffer[i])
4182                                         pci_free_consistent(pcidev,
4183                                                 DMA_BUFFER_SIZE,
4184                                                 devpriv->ao_buffer[i],
4185                                                 devpriv->ao_buffer_bus_addr[i]);
4186                         }
4187                         /*  free dma descriptors */
4188                         if (devpriv->ai_dma_desc)
4189                                 pci_free_consistent(pcidev,
4190                                         sizeof(struct plx_dma_desc) *
4191                                         ai_dma_ring_count(thisboard),
4192                                         devpriv->ai_dma_desc,
4193                                         devpriv->ai_dma_desc_bus_addr);
4194                         if (devpriv->ao_dma_desc)
4195                                 pci_free_consistent(pcidev,
4196                                         sizeof(struct plx_dma_desc) *
4197                                         AO_DMA_RING_COUNT,
4198                                         devpriv->ao_dma_desc,
4199                                         devpriv->ao_dma_desc_bus_addr);
4200                 }
4201         }
4202         if (dev->subdevices)
4203                 subdev_8255_cleanup(dev, &dev->subdevices[4]);
4204         if (pcidev) {
4205                 if (dev->iobase)
4206                         comedi_pci_disable(pcidev);
4207         }
4208 }
4209
4210 static struct comedi_driver cb_pcidas64_driver = {
4211         .driver_name    = "cb_pcidas64",
4212         .module         = THIS_MODULE,
4213         .auto_attach    = auto_attach,
4214         .detach         = detach,
4215 };
4216
4217 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4218                                            const struct pci_device_id *ent)
4219 {
4220         return comedi_pci_auto_config(dev, &cb_pcidas64_driver);
4221 }
4222
4223 static void cb_pcidas64_pci_remove(struct pci_dev *dev)
4224 {
4225         comedi_pci_auto_unconfig(dev);
4226 }
4227
4228 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4229         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001d) },
4230         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001e) },
4231         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0035) },
4232         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0036) },
4233         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0037) },
4234         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0052) },
4235         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005d) },
4236         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005e) },
4237         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005f) },
4238         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0061) },
4239         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0062) },
4240         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0063) },
4241         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0064) },
4242         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0066) },
4243         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0067) },
4244         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0068) },
4245         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x006f) },
4246         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0078) },
4247         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0079) },
4248         { 0 }
4249 };
4250 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4251
4252 static struct pci_driver cb_pcidas64_pci_driver = {
4253         .name           = "cb_pcidas64",
4254         .id_table       = cb_pcidas64_pci_table,
4255         .probe          = cb_pcidas64_pci_probe,
4256         .remove         = cb_pcidas64_pci_remove,
4257 };
4258 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4259
4260 MODULE_AUTHOR("Comedi http://www.comedi.org");
4261 MODULE_DESCRIPTION("Comedi low-level driver");
4262 MODULE_LICENSE("GPL");