1 //------------------------------------------------------------------------------
2 // <copyright file="hif.h" company="Atheros">
3 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
6 // Permission to use, copy, modify, and/or distribute this software for any
7 // purpose with or without fee is hereby granted, provided that the above
8 // copyright notice and this permission notice appear in all copies.
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 //------------------------------------------------------------------------------
20 //==============================================================================
21 // HIF specific declarations and prototypes
23 // Author(s): ="Atheros"
24 //==============================================================================
30 #endif /* __cplusplus */
39 typedef struct htc_callbacks HTC_CALLBACKS;
43 * direction - Direction of transfer (HIF_READ/HIF_WRITE).
45 #define HIF_READ 0x00000001
46 #define HIF_WRITE 0x00000002
47 #define HIF_DIR_MASK (HIF_READ | HIF_WRITE)
50 * type - An interface may support different kind of read/write commands.
51 * For example: SDIO supports CMD52/CMD53s. In case of MSIO it
52 * translates to using different kinds of TPCs. The command type
53 * is thus divided into a basic and an extended command and can
54 * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
56 #define HIF_BASIC_IO 0x00000004
57 #define HIF_EXTENDED_IO 0x00000008
58 #define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO)
61 * emode - This indicates the whether the command is to be executed in a
62 * blocking or non-blocking fashion (HIF_SYNCHRONOUS/
63 * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
64 * implemented using the asynchronous mode allowing the the bus
65 * driver to indicate the completion of operation through the
66 * registered callback routine. The requirement primarily comes
67 * from the contexts these operations get called from (a driver's
68 * transmit context or the ISR context in case of receive).
69 * Support for both of these modes is essential.
71 #define HIF_SYNCHRONOUS 0x00000010
72 #define HIF_ASYNCHRONOUS 0x00000020
73 #define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
76 * dmode - An interface may support different kinds of commands based on
77 * the tradeoff between the amount of data it can carry and the
78 * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
79 * HIF_BLOCK_BASIS). In case of latter, the data is rounded off
80 * to the nearest block size by padding. The size of the block is
81 * configurable at compile time using the HIF_BLOCK_SIZE and is
82 * negotiated with the target during initialization after the
83 * AR6000 interrupts are enabled.
85 #define HIF_BYTE_BASIS 0x00000040
86 #define HIF_BLOCK_BASIS 0x00000080
87 #define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
90 * amode - This indicates if the address has to be incremented on AR6000
91 * after every read/write operation (HIF?FIXED_ADDRESS/
92 * HIF_INCREMENTAL_ADDRESS).
94 #define HIF_FIXED_ADDRESS 0x00000100
95 #define HIF_INCREMENTAL_ADDRESS 0x00000200
96 #define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
98 #define HIF_WR_ASYNC_BYTE_FIX \
99 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
100 #define HIF_WR_ASYNC_BYTE_INC \
101 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
102 #define HIF_WR_ASYNC_BLOCK_INC \
103 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
104 #define HIF_WR_SYNC_BYTE_FIX \
105 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
106 #define HIF_WR_SYNC_BYTE_INC \
107 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
108 #define HIF_WR_SYNC_BLOCK_INC \
109 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
110 #define HIF_WR_ASYNC_BLOCK_FIX \
111 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
112 #define HIF_WR_SYNC_BLOCK_FIX \
113 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
114 #define HIF_RD_SYNC_BYTE_INC \
115 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
116 #define HIF_RD_SYNC_BYTE_FIX \
117 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
118 #define HIF_RD_ASYNC_BYTE_FIX \
119 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
120 #define HIF_RD_ASYNC_BLOCK_FIX \
121 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
122 #define HIF_RD_ASYNC_BYTE_INC \
123 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
124 #define HIF_RD_ASYNC_BLOCK_INC \
125 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
126 #define HIF_RD_SYNC_BLOCK_INC \
127 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
128 #define HIF_RD_SYNC_BLOCK_FIX \
129 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
132 HIF_DEVICE_POWER_STATE = 0,
133 HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
134 HIF_DEVICE_GET_MBOX_ADDR,
135 HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
136 HIF_DEVICE_GET_IRQ_PROC_MODE,
137 HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
138 HIF_DEVICE_POWER_STATE_CHANGE,
139 HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
140 HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
141 HIF_DEVICE_GET_OS_DEVICE,
142 HIF_DEVICE_DEBUG_BUS_STATE,
143 } HIF_DEVICE_CONFIG_OPCODE;
146 * HIF CONFIGURE definitions:
148 * HIF_DEVICE_GET_MBOX_BLOCK_SIZE
150 * output : array of 4 u32s
151 * notes: block size is returned for each mailbox (4)
153 * HIF_DEVICE_GET_MBOX_ADDR
155 * output : struct hif_device_mbox_info
158 * HIF_DEVICE_GET_PENDING_EVENTS_FUNC
160 * output: HIF_PENDING_EVENTS_FUNC function pointer
161 * notes: this is optional for the HIF layer, if the request is
162 * not handled then it indicates that the upper layer can use
163 * the standard device methods to get pending events (IRQs, mailbox messages etc..)
164 * otherwise it can call the function pointer to check pending events.
166 * HIF_DEVICE_GET_IRQ_PROC_MODE
168 * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
169 * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
170 * layer can report whether IRQ processing is requires synchronous behavior or
171 * can be processed using asynchronous bus requests (typically faster).
173 * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
175 * output : HIF_MASK_UNMASK_RECV_EVENT function pointer
176 * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism
177 * to mask receive message events. The upper layer can call this pointer when it needs
178 * to mask/unmask receive events (in case it runs out of buffers).
180 * HIF_DEVICE_POWER_STATE_CHANGE
182 * input : HIF_DEVICE_POWER_CHANGE_TYPE
184 * note: this is optional for the HIF layer. The HIF layer can handle power on/off state change
185 * requests in an interconnect specific way. This is highly OS and bus driver dependent.
186 * The caller must guarantee that no HIF read/write requests will be made after the device
189 * HIF_DEVICE_GET_IRQ_YIELD_PARAMS
192 * output : struct hif_device_irq_yield_params
193 * note: This query checks if the HIF layer wishes to impose a processing yield count for the DSR handler.
194 * The DSR callback handler will exit after a fixed number of RX packets or events are processed.
195 * This query is only made if the device reports an IRQ processing mode of HIF_DEVICE_IRQ_SYNC_ONLY.
196 * The HIF implementation can ignore this command if it does not desire the DSR callback to yield.
197 * The HIF layer can indicate the maximum number of IRQ processing units (RX packets) before the
198 * DSR handler callback must yield and return control back to the HIF layer. When a yield limit is
199 * used the DSR callback will not call HIFAckInterrupts() as it would normally do before returning.
200 * The HIF implementation that requires a yield count must call HIFAckInterrupt() when it is prepared
201 * to process interrupts again.
203 * HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT
205 * output : struct hif_device_scatter_support_info
206 * note: This query checks if the HIF layer implements the SCATTER request interface. Scatter requests
207 * allows upper layers to submit mailbox I/O operations using a list of buffers. This is useful for
208 * multi-message transfers that can better utilize the bus interconnect.
211 * HIF_DEVICE_GET_OS_DEVICE
213 * output : struct hif_device_os_device_info;
214 * note: On some operating systems, the HIF layer has a parent device object for the bus. This object
215 * may be required to register certain types of logical devices.
217 * HIF_DEVICE_DEBUG_BUS_STATE
220 * note: This configure option triggers the HIF interface to dump as much bus interface state. This
221 * configuration request is optional (No-OP on some HIF implementations)
225 struct hif_mbox_properties {
226 u32 ExtendedAddress; /* extended address for larger writes */
230 #define HIF_MBOX_FLAG_NO_BUNDLING (1 << 0) /* do not allow bundling over the mailbox */
232 typedef enum _MBOX_BUF_IF_TYPE {
233 MBOX_BUS_IF_SDIO = 0,
237 struct hif_device_mbox_info {
238 u32 MboxAddresses[4]; /* must be first element for legacy HIFs that return the address in
239 and ARRAY of 32-bit words */
241 /* the following describe extended mailbox properties */
242 struct hif_mbox_properties MboxProp[4];
243 /* if the HIF supports the GMbox extended address region it can report it
244 * here, some interfaces cannot support the GMBOX address range and not set this */
247 u32 Flags; /* flags to describe mbox behavior or usage */
248 MBOX_BUF_IF_TYPE MboxBusIFType; /* mailbox bus interface type */
252 HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all
253 interrupts before returning */
254 HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts
255 using ASYNC I/O (that is HIFAckInterrupt can be called at a
257 } HIF_DEVICE_IRQ_PROCESSING_MODE;
260 HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */
261 HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */
262 HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures
263 to completely power-off the module and associated hardware (i.e. cut power supplies)
265 } HIF_DEVICE_POWER_CHANGE_TYPE;
267 struct hif_device_irq_yield_params {
268 int RecvPacketYieldCount; /* max number of packets to force DSR to return */
272 struct hif_scatter_item {
273 u8 *pBuffer; /* CPU accessible address of buffer */
274 int Length; /* length of transfer to/from this buffer */
275 void *pCallerContexts[2]; /* space for caller to insert a context associated with this item */
278 struct hif_scatter_req;
279 typedef void ( *HIF_SCATTER_COMP_CB)(struct hif_scatter_req *);
281 typedef enum _HIF_SCATTER_METHOD {
282 HIF_SCATTER_NONE = 0,
283 HIF_SCATTER_DMA_REAL, /* Real SG support no restrictions */
284 HIF_SCATTER_DMA_BOUNCE, /* Uses SG DMA but HIF layer uses an internal bounce buffer */
285 } HIF_SCATTER_METHOD;
287 struct hif_scatter_req {
288 struct dl_list ListLink; /* link management */
289 u32 Address; /* address for the read/write operation */
290 u32 Request; /* request flags */
291 u32 TotalLength; /* total length of entire transfer */
292 u32 CallerFlags; /* caller specific flags can be stored here */
293 HIF_SCATTER_COMP_CB CompletionRoutine; /* completion routine set by caller */
294 int CompletionStatus; /* status of completion */
295 void *Context; /* caller context for this request */
296 int ValidScatterEntries; /* number of valid entries set by caller */
297 HIF_SCATTER_METHOD ScatterMethod; /* scatter method handled by HIF */
298 void *HIFPrivate[4]; /* HIF private area */
299 u8 *pScatterBounceBuffer; /* bounce buffer for upper layers to copy to/from */
300 struct hif_scatter_item ScatterList[1]; /* start of scatter list */
303 typedef struct hif_scatter_req * ( *HIF_ALLOCATE_SCATTER_REQUEST)(struct hif_device *device);
304 typedef void ( *HIF_FREE_SCATTER_REQUEST)(struct hif_device *device, struct hif_scatter_req *request);
305 typedef int ( *HIF_READWRITE_SCATTER)(struct hif_device *device, struct hif_scatter_req *request);
307 struct hif_device_scatter_support_info {
308 /* information returned from HIF layer */
309 HIF_ALLOCATE_SCATTER_REQUEST pAllocateReqFunc;
310 HIF_FREE_SCATTER_REQUEST pFreeReqFunc;
311 HIF_READWRITE_SCATTER pReadWriteScatterFunc;
312 int MaxScatterEntries;
313 int MaxTransferSizePerScatterReq;
316 struct hif_device_os_device_info {
320 #define HIF_MAX_DEVICES 1
322 struct htc_callbacks {
323 void *context; /* context to pass to the dsrhandler
324 note : rwCompletionHandler is provided the context passed to HIFReadWrite */
325 int (* rwCompletionHandler)(void *rwContext, int status);
326 int (* dsrHandler)(void *context);
329 typedef struct osdrv_callbacks {
330 void *context; /* context to pass for all callbacks except deviceRemovedHandler
331 the deviceRemovedHandler is only called if the device is claimed */
332 int (* deviceInsertedHandler)(void *context, void *hif_handle);
333 int (* deviceRemovedHandler)(void *claimedContext, void *hif_handle);
334 int (* deviceSuspendHandler)(void *context);
335 int (* deviceResumeHandler)(void *context);
336 int (* deviceWakeupHandler)(void *context);
337 int (* devicePowerChangeHandler)(void *context, HIF_DEVICE_POWER_CHANGE_TYPE config);
340 #define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host
341 needs to read the register table to figure out what */
342 #define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */
344 struct hif_pending_events_info {
347 u32 AvailableRecvBytes;
354 /* function to get pending events , some HIF modules use special mechanisms
355 * to detect packet available and other interrupts */
356 typedef int ( *HIF_PENDING_EVENTS_FUNC)(struct hif_device *device,
357 struct hif_pending_events_info *pEvents,
360 #define HIF_MASK_RECV true
361 #define HIF_UNMASK_RECV false
362 /* function to mask recv events */
363 typedef int ( *HIF_MASK_UNMASK_RECV_EVENT)(struct hif_device *device,
369 * This API is used to perform any global initialization of the HIF layer
370 * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
373 int HIFInit(OSDRV_CALLBACKS *callbacks);
375 /* This API claims the HIF device and provides a context for handling removal.
376 * The device removal callback is only called when the OSDRV layer claims
377 * a device. The claimed context must be non-NULL */
378 void HIFClaimDevice(struct hif_device *device, void *claimedContext);
379 /* release the claimed device */
380 void HIFReleaseDevice(struct hif_device *device);
382 /* This API allows the HTC layer to attach to the HIF device */
383 int HIFAttachHTC(struct hif_device *device, HTC_CALLBACKS *callbacks);
384 /* This API detaches the HTC layer from the HIF device */
385 void HIFDetachHTC(struct hif_device *device);
388 * This API is used to provide the read/write interface over the specific bus
390 * address - Starting address in the AR6000's address space. For mailbox
391 * writes, it refers to the start of the mbox boundary. It should
392 * be ensured that the last byte falls on the mailbox's EOM. For
393 * mailbox reads, it refers to the end of the mbox boundary.
394 * buffer - Pointer to the buffer containg the data to be transmitted or
396 * length - Amount of data to be transmitted or received.
397 * request - Characterizes the attributes of the command.
400 HIFReadWrite(struct hif_device *device,
408 * This can be initiated from the unload driver context when the OSDRV layer has no more use for
411 void HIFShutDownDevice(struct hif_device *device);
414 * This should translate to an acknowledgment to the bus driver indicating that
415 * the previous interrupt request has been serviced and the all the relevant
416 * sources have been cleared. HTC is ready to process more interrupts.
417 * This should prevent the bus driver from raising an interrupt unless the
418 * previous one has been serviced and acknowledged using the previous API.
420 void HIFAckInterrupt(struct hif_device *device);
422 void HIFMaskInterrupt(struct hif_device *device);
424 void HIFUnMaskInterrupt(struct hif_device *device);
428 * This set of functions are to be used by the bus driver to notify
429 * the HIF module about various events.
430 * These are not implemented if the bus driver provides an alternative
431 * way for this notification though callbacks for instance.
433 int HIFInsertEventNotify(void);
435 int HIFRemoveEventNotify(void);
437 int HIFIRQEventNotify(void);
439 int HIFRWCompleteEventNotify(void);
443 HIFConfigureDevice(struct hif_device *device, HIF_DEVICE_CONFIG_OPCODE opcode,
444 void *config, u32 configLen);
447 * This API wait for the remaining MBOX messages to be drained
448 * This should be moved to HTC AR6K layer
450 int hifWaitForPendingRecv(struct hif_device *device);