drivers/spi/zynqmp_gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <asm/io.h>
  11 #include <clk.h>
  12 #include <dm.h>
  13 #include <malloc.h>
  14 #include <memalign.h>
  15 #include <spi.h>
  16 #include <ubi_uboot.h>
  17 #include <wait_bit.h>
  18
  19 #define GQSPI_GFIFO_STRT_MODE_MASK      BIT(29)
  20 #define GQSPI_CONFIG_MODE_EN_MASK       (3 << 30)
  21 #define GQSPI_CONFIG_DMA_MODE           (2 << 30)
  22 #define GQSPI_CONFIG_CPHA_MASK          BIT(2)
  23 #define GQSPI_CONFIG_CPOL_MASK          BIT(1)
  24
  25 /*
  26  * QSPI Interrupt Registers bit Masks
  27  *
  28  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  29  * bit definitions.
  30  */
  31 #define GQSPI_IXR_TXNFULL_MASK          0x00000004 /* QSPI TX FIFO Overflow */
  32 #define GQSPI_IXR_TXFULL_MASK           0x00000008 /* QSPI TX FIFO is full */
  33 #define GQSPI_IXR_RXNEMTY_MASK          0x00000010 /* QSPI RX FIFO Not Empty */
  34 #define GQSPI_IXR_GFEMTY_MASK           0x00000080 /* QSPI Generic FIFO Empty */
  35 #define GQSPI_IXR_ALL_MASK              (GQSPI_IXR_TXNFULL_MASK | \
  36                                          GQSPI_IXR_RXNEMTY_MASK)
  37
  38 /*
  39  * QSPI Enable Register bit Masks
  40  *
  41  * This register is used to enable or disable the QSPI controller
  42  */
  43 #define GQSPI_ENABLE_ENABLE_MASK        0x00000001 /* QSPI Enable Bit Mask */
  44
  45 #define GQSPI_GFIFO_LOW_BUS             BIT(14)
  46 #define GQSPI_GFIFO_CS_LOWER            BIT(12)
  47 #define GQSPI_GFIFO_UP_BUS              BIT(15)
  48 #define GQSPI_GFIFO_CS_UPPER            BIT(13)
  49 #define GQSPI_SPI_MODE_QSPI             (3 << 10)
  50 #define GQSPI_SPI_MODE_SPI              BIT(10)
  51 #define GQSPI_SPI_MODE_DUAL_SPI         (2 << 10)
  52 #define GQSPI_IMD_DATA_CS_ASSERT        5
  53 #define GQSPI_IMD_DATA_CS_DEASSERT      5
  54 #define GQSPI_GFIFO_TX                  BIT(16)
  55 #define GQSPI_GFIFO_RX                  BIT(17)
  56 #define GQSPI_GFIFO_STRIPE_MASK         BIT(18)
  57 #define GQSPI_GFIFO_IMD_MASK            0xFF
  58 #define GQSPI_GFIFO_EXP_MASK            BIT(9)
  59 #define GQSPI_GFIFO_DATA_XFR_MASK       BIT(8)
  60 #define GQSPI_STRT_GEN_FIFO             BIT(28)
  61 #define GQSPI_GEN_FIFO_STRT_MOD         BIT(29)
  62 #define GQSPI_GFIFO_WP_HOLD             BIT(19)
  63 #define GQSPI_BAUD_DIV_MASK             (7 << 3)
  64 #define GQSPI_DFLT_BAUD_RATE_DIV        BIT(3)
  65 #define GQSPI_GFIFO_ALL_INT_MASK        0xFBE
  66 #define GQSPI_DMA_DST_I_STS_DONE        BIT(1)
  67 #define GQSPI_DMA_DST_I_STS_MASK        0xFE
  68 #define MODEBITS                        0x6
  69
  70 #define GQSPI_GFIFO_SELECT              BIT(0)
  71 #define GQSPI_FIFO_THRESHOLD            1
  72
  73 #define SPI_XFER_ON_BOTH                0
  74 #define SPI_XFER_ON_LOWER               1
  75 #define SPI_XFER_ON_UPPER               2
  76
  77 #define GQSPI_DMA_ALIGN                 0x4
  78 #define GQSPI_MAX_BAUD_RATE_VAL         7
  79 #define GQSPI_DFLT_BAUD_RATE_VAL        2
  80
  81 #define GQSPI_TIMEOUT                   100000000
  82
  83 #define GQSPI_BAUD_DIV_SHIFT            2
  84 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
  85 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
  86 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
  87 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
  88 #define GQSPI_USE_DATA_DLY              0x1
  89 #define GQSPI_USE_DATA_DLY_SHIFT        31
  90 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
  91 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
  92 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
  93 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
  94 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
  95 #define IOU_TAPDLY_BYPASS_OFST          0xFF180390
  96 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK    0x00000020
  97 #define GQSPI_FREQ_40MHZ                40000000
  98 #define GQSPI_FREQ_100MHZ               100000000
  99 #define GQSPI_FREQ_150MHZ               150000000
 100 #define IOU_TAPDLY_BYPASS_MASK          0x7
 101
 102 #define GQSPI_REG_OFFSET                0x100
 103 #define GQSPI_DMA_REG_OFFSET            0x800
 104
 105 /* QSPI register offsets */
 106 struct zynqmp_qspi_regs {
 107         u32 confr;      /* 0x00 */
 108         u32 isr;        /* 0x04 */
 109         u32 ier;        /* 0x08 */
 110         u32 idisr;      /* 0x0C */
 111         u32 imaskr;     /* 0x10 */
 112         u32 enbr;       /* 0x14 */
 113         u32 dr;         /* 0x18 */
 114         u32 txd0r;      /* 0x1C */
 115         u32 drxr;       /* 0x20 */
 116         u32 sicr;       /* 0x24 */
 117         u32 txftr;      /* 0x28 */
 118         u32 rxftr;      /* 0x2C */
 119         u32 gpior;      /* 0x30 */
 120         u32 reserved0;  /* 0x34 */
 121         u32 lpbkdly;    /* 0x38 */
 122         u32 reserved1;  /* 0x3C */
 123         u32 genfifo;    /* 0x40 */
 124         u32 gqspisel;   /* 0x44 */
 125         u32 reserved2;  /* 0x48 */
 126         u32 gqfifoctrl; /* 0x4C */
 127         u32 gqfthr;     /* 0x50 */
 128         u32 gqpollcfg;  /* 0x54 */
 129         u32 gqpollto;   /* 0x58 */
 130         u32 gqxfersts;  /* 0x5C */
 131         u32 gqfifosnap; /* 0x60 */
 132         u32 gqrxcpy;    /* 0x64 */
 133         u32 reserved3[36];      /* 0x68 */
 134         u32 gqspidlyadj;        /* 0xF8 */
 135 };
 136
 137 struct zynqmp_qspi_dma_regs {
 138         u32 dmadst;     /* 0x00 */
 139         u32 dmasize;    /* 0x04 */
 140         u32 dmasts;     /* 0x08 */
 141         u32 dmactrl;    /* 0x0C */
 142         u32 reserved0;  /* 0x10 */
 143         u32 dmaisr;     /* 0x14 */
 144         u32 dmaier;     /* 0x18 */
 145         u32 dmaidr;     /* 0x1C */
 146         u32 dmaimr;     /* 0x20 */
 147         u32 dmactrl2;   /* 0x24 */
 148         u32 dmadstmsb;  /* 0x28 */
 149 };
 150
 151 DECLARE_GLOBAL_DATA_PTR;
 152
 153 struct zynqmp_qspi_platdata {
 154         struct zynqmp_qspi_regs *regs;
 155         struct zynqmp_qspi_dma_regs *dma_regs;
 156         u32 frequency;
 157         u32 speed_hz;
 158 };
 159
 160 struct zynqmp_qspi_priv {
 161         struct zynqmp_qspi_regs *regs;
 162         struct zynqmp_qspi_dma_regs *dma_regs;
 163         const void *tx_buf;
 164         void *rx_buf;
 165         unsigned int len;
 166         int bytes_to_transfer;
 167         int bytes_to_receive;
 168         unsigned int is_inst;
 169         unsigned int cs_change:1;
 170 };
 171
 172 static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
 173 {
 174         struct zynqmp_qspi_platdata *plat = bus->platdata;
 175
 176         debug("%s\n", __func__);
 177
 178         plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
 179                                                  GQSPI_REG_OFFSET);
 180         plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
 181                           (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
 182
 183         return 0;
 184 }
 185
 186 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 187 {
 188         u32 config_reg;
 189         struct zynqmp_qspi_regs *regs = priv->regs;
 190
 191         writel(GQSPI_GFIFO_SELECT, &regs->gqspisel);
 192         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 193         writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 194         writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
 195         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
 196
 197         config_reg = readl(&regs->confr);
 198         config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 199                         GQSPI_CONFIG_MODE_EN_MASK);
 200         config_reg |= GQSPI_CONFIG_DMA_MODE |
 201                       GQSPI_GFIFO_WP_HOLD |
 202                       GQSPI_DFLT_BAUD_RATE_DIV;
 203         writel(config_reg, &regs->confr);
 204
 205         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 206 }
 207
 208 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
 209 {
 210         u32 gqspi_fifo_reg = 0;
 211
 212         gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
 213                          GQSPI_GFIFO_CS_LOWER;
 214
 215         return gqspi_fifo_reg;
 216 }
 217
 218 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 219                                       u32 gqspi_fifo_reg)
 220 {
 221         struct zynqmp_qspi_regs *regs = priv->regs;
 222         int ret = 0;
 223
 224         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 225                                 GQSPI_TIMEOUT, 1);
 226         if (ret)
 227                 printf("%s Timeout\n", __func__);
 228
 229         writel(gqspi_fifo_reg, &regs->genfifo);
 230 }
 231
 232 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 233 {
 234         u32 gqspi_fifo_reg = 0;
 235
 236         if (is_on) {
 237                 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
 238                 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
 239                                   GQSPI_IMD_DATA_CS_ASSERT;
 240         } else {
 241                 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
 242                 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
 243         }
 244
 245         debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 246
 247         zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 248 }
 249
 250 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 251 {
 252         struct zynqmp_qspi_platdata *plat = bus->platdata;
 253         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 254         struct zynqmp_qspi_regs *regs = priv->regs;
 255         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 256         u32 reqhz = 0;
 257
 258         clk_rate = plat->frequency;
 259         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 260
 261         debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 262               __func__, reqhz, clk_rate, baudrateval);
 263
 264         if (reqhz < GQSPI_FREQ_40MHZ) {
 265                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 266                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 267                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 268         } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 269                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 270                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 271                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 272                 lpbkdlyadj = readl(&regs->lpbkdly);
 273                 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
 274                 datadlyadj = readl(&regs->gqspidlyadj);
 275                 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 276                                 | (GQSPI_DATA_DLY_ADJ_VALUE <<
 277                                         GQSPI_DATA_DLY_ADJ_SHIFT));
 278         } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 279                 lpbkdlyadj = readl(&regs->lpbkdly);
 280                 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
 281                                 GQSPI_LPBK_DLY_ADJ_DLY_0);
 282         }
 283
 284         zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
 285                           tapdlybypass);
 286         writel(lpbkdlyadj, &regs->lpbkdly);
 287         writel(datadlyadj, &regs->gqspidlyadj);
 288 }
 289
 290 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
 291 {
 292         struct zynqmp_qspi_platdata *plat = bus->platdata;
 293         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 294         struct zynqmp_qspi_regs *regs = priv->regs;
 295         u32 confr;
 296         u8 baud_rate_val = 0;
 297
 298         debug("%s\n", __func__);
 299         if (speed > plat->frequency)
 300                 speed = plat->frequency;
 301
 302         /* Set the clock frequency */
 303         confr = readl(&regs->confr);
 304         if (speed == 0) {
 305                 /* Set baudrate x8, if the freq is 0 */
 306                 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 307         } else if (plat->speed_hz != speed) {
 308                 while ((baud_rate_val < 8) &&
 309                        ((plat->frequency /
 310                        (2 << baud_rate_val)) > speed))
 311                         baud_rate_val++;
 312
 313                 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
 314                         baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 315
 316                 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
 317         }
 318         confr &= ~GQSPI_BAUD_DIV_MASK;
 319         confr |= (baud_rate_val << 3);
 320         writel(confr, &regs->confr);
 321
 322         zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
 323         debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
 324
 325         return 0;
 326 }
 327
 328 static int zynqmp_qspi_probe(struct udevice *bus)
 329 {
 330         struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
 331         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 332         struct clk clk;
 333         unsigned long clock;
 334         int ret;
 335
 336         debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
 337
 338         priv->regs = plat->regs;
 339         priv->dma_regs = plat->dma_regs;
 340
 341         ret = clk_get_by_index(bus, 0, &clk);
 342         if (ret < 0) {
 343                 dev_err(dev, "failed to get clock\n");
 344                 return ret;
 345         }
 346
 347         clock = clk_get_rate(&clk);
 348         if (IS_ERR_VALUE(clock)) {
 349                 dev_err(dev, "failed to get rate\n");
 350                 return clock;
 351         }
 352         debug("%s: CLK %ld\n", __func__, clock);
 353
 354         ret = clk_enable(&clk);
 355         if (ret && ret != -ENOSYS) {
 356                 dev_err(dev, "failed to enable clock\n");
 357                 return ret;
 358         }
 359         plat->frequency = clock;
 360         plat->speed_hz = plat->frequency / 2;
 361
 362         /* init the zynq spi hw */
 363         zynqmp_qspi_init_hw(priv);
 364
 365         return 0;
 366 }
 367
 368 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
 369 {
 370         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 371         struct zynqmp_qspi_regs *regs = priv->regs;
 372         u32 confr;
 373
 374         debug("%s\n", __func__);
 375         /* Set the SPI Clock phase and polarities */
 376         confr = readl(&regs->confr);
 377         confr &= ~(GQSPI_CONFIG_CPHA_MASK |
 378                    GQSPI_CONFIG_CPOL_MASK);
 379
 380         if (mode & SPI_CPHA)
 381                 confr |= GQSPI_CONFIG_CPHA_MASK;
 382         if (mode & SPI_CPOL)
 383                 confr |= GQSPI_CONFIG_CPOL_MASK;
 384
 385         writel(confr, &regs->confr);
 386
 387         return 0;
 388 }
 389
 390 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 391 {
 392         u32 data;
 393         int ret = 0;
 394         struct zynqmp_qspi_regs *regs = priv->regs;
 395         u32 *buf = (u32 *)priv->tx_buf;
 396         u32 len = size;
 397
 398         debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
 399               size);
 400
 401         while (size) {
 402                 ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
 403                                         GQSPI_TIMEOUT, 1);
 404                 if (ret) {
 405                         printf("%s: Timeout\n", __func__);
 406                         return ret;
 407                 }
 408
 409                 if (size >= 4) {
 410                         writel(*buf, &regs->txd0r);
 411                         buf++;
 412                         size -= 4;
 413                 } else {
 414                         switch (size) {
 415                         case 1:
 416                                 data = *((u8 *)buf);
 417                                 buf += 1;
 418                                 data |= GENMASK(31, 8);
 419                                 break;
 420                         case 2:
 421                                 data = *((u16 *)buf);
 422                                 buf += 2;
 423                                 data |= GENMASK(31, 16);
 424                                 break;
 425                         case 3:
 426                                 data = *((u16 *)buf);
 427                                 buf += 2;
 428                                 data |= (*((u8 *)buf) << 16);
 429                                 buf += 1;
 430                                 data |= GENMASK(31, 24);
 431                                 break;
 432                         }
 433                         writel(data, &regs->txd0r);
 434                         size = 0;
 435                 }
 436         }
 437
 438         priv->tx_buf += len;
 439         return 0;
 440 }
 441
 442 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
 443 {
 444         u32 gen_fifo_cmd;
 445         u32 bytecount = 0;
 446
 447         while (priv->len) {
 448                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 449                 gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
 450                 gen_fifo_cmd |= *(u8 *)priv->tx_buf;
 451                 bytecount++;
 452                 priv->len--;
 453                 priv->tx_buf = (u8 *)priv->tx_buf + 1;
 454
 455                 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
 456
 457                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 458         }
 459 }
 460
 461 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
 462                                 u32 *gen_fifo_cmd)
 463 {
 464         u32 expval = 8;
 465         u32 len;
 466
 467         while (1) {
 468                 if (priv->len > 255) {
 469                         if (priv->len & (1 << expval)) {
 470                                 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
 471                                 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
 472                                 *gen_fifo_cmd |= expval;
 473                                 priv->len -= (1 << expval);
 474                                 return expval;
 475                         }
 476                         expval++;
 477                 } else {
 478                         *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
 479                                           GQSPI_GFIFO_EXP_MASK);
 480                         *gen_fifo_cmd |= (u8)priv->len;
 481                         len = (u8)priv->len;
 482                         priv->len  = 0;
 483                         return len;
 484                 }
 485         }
 486 }
 487
 488 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
 489 {
 490         u32 gen_fifo_cmd;
 491         u32 len;
 492         int ret = 0;
 493
 494         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 495         gen_fifo_cmd |= GQSPI_GFIFO_TX |
 496                         GQSPI_GFIFO_DATA_XFR_MASK;
 497
 498         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 499
 500         while (priv->len) {
 501                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 502                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 503
 504                 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
 505
 506                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 507                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 508                                                        1 << len);
 509                 else
 510                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 511                                                        len);
 512
 513                 if (ret)
 514                         return ret;
 515         }
 516         return ret;
 517 }
 518
 519 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 520                                  u32 gen_fifo_cmd, u32 *buf)
 521 {
 522         u32 addr;
 523         u32 size, len;
 524         u32 actuallen = priv->len;
 525         int ret = 0;
 526         struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 527
 528         writel((unsigned long)buf, &dma_regs->dmadst);
 529         writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
 530         writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 531         addr = (unsigned long)buf;
 532         size = roundup(priv->len, ARCH_DMA_MINALIGN);
 533         flush_dcache_range(addr, addr + size);
 534
 535         while (priv->len) {
 536                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 537                 if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
 538                     (len % ARCH_DMA_MINALIGN)) {
 539                         gen_fifo_cmd &= ~GENMASK(7, 0);
 540                         gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
 541                 }
 542                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 543
 544                 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 545         }
 546
 547         ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
 548                                 1, GQSPI_TIMEOUT, 1);
 549         if (ret) {
 550                 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
 551                 return -ETIMEDOUT;
 552         }
 553
 554         writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
 555
 556         debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 557               (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
 558               actuallen);
 559
 560         if (buf != priv->rx_buf)
 561                 memcpy(priv->rx_buf, buf, actuallen);
 562
 563         return 0;
 564 }
 565
 566 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
 567 {
 568         u32 gen_fifo_cmd;
 569         u32 *buf;
 570         u32 actuallen = priv->len;
 571
 572         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 573         gen_fifo_cmd |= GQSPI_GFIFO_RX |
 574                         GQSPI_GFIFO_DATA_XFR_MASK;
 575
 576         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 577
 578         /*
 579          * Check if receive buffer is aligned to 4 byte and length
 580          * is multiples of four byte as we are using dma to receive.
 581          */
 582         if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
 583             !(actuallen % GQSPI_DMA_ALIGN)) {
 584                 buf = (u32 *)priv->rx_buf;
 585                 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 586         }
 587
 588         ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
 589                                                   GQSPI_DMA_ALIGN));
 590         buf = (u32 *)tmp;
 591         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 592 }
 593
 594 static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
 595 {
 596         int ret = 0;
 597
 598         if (priv->is_inst) {
 599                 if (priv->tx_buf)
 600                         zynqmp_qspi_genfifo_cmd(priv);
 601                 else
 602                         return -EINVAL;
 603         } else {
 604                 if (priv->tx_buf)
 605                         ret = zynqmp_qspi_genfifo_fill_tx(priv);
 606                 else if (priv->rx_buf)
 607                         ret = zynqmp_qspi_genfifo_fill_rx(priv);
 608                 else
 609                         return -EINVAL;
 610         }
 611         return ret;
 612 }
 613
 614 static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
 615 {
 616         static unsigned int cs_change = 1;
 617         int status = 0;
 618
 619         debug("%s\n", __func__);
 620
 621         while (1) {
 622                 /* Select the chip if required */
 623                 if (cs_change)
 624                         zynqmp_qspi_chipselect(priv, 1);
 625
 626                 cs_change = priv->cs_change;
 627
 628                 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
 629                         status = -EINVAL;
 630                         break;
 631                 }
 632
 633                 /* Request the transfer */
 634                 if (priv->len) {
 635                         status = zynqmp_qspi_start_transfer(priv);
 636                         priv->is_inst = 0;
 637                         if (status < 0)
 638                                 break;
 639                 }
 640
 641                 if (cs_change)
 642                         /* Deselect the chip */
 643                         zynqmp_qspi_chipselect(priv, 0);
 644                 break;
 645         }
 646
 647         return status;
 648 }
 649
 650 static int zynqmp_qspi_claim_bus(struct udevice *dev)
 651 {
 652         struct udevice *bus = dev->parent;
 653         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 654         struct zynqmp_qspi_regs *regs = priv->regs;
 655
 656         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 657
 658         return 0;
 659 }
 660
 661 static int zynqmp_qspi_release_bus(struct udevice *dev)
 662 {
 663         struct udevice *bus = dev->parent;
 664         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 665         struct zynqmp_qspi_regs *regs = priv->regs;
 666
 667         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 668
 669         return 0;
 670 }
 671
 672 int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
 673                      void *din, unsigned long flags)
 674 {
 675         struct udevice *bus = dev->parent;
 676         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 677
 678         debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
 679               (unsigned long)priv, bitlen, (unsigned long)dout);
 680         debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
 681
 682         priv->tx_buf = dout;
 683         priv->rx_buf = din;
 684         priv->len = bitlen / 8;
 685
 686         /*
 687          * Assume that the beginning of a transfer with bits to
 688          * transmit must contain a device command.
 689          */
 690         if (dout && flags & SPI_XFER_BEGIN)
 691                 priv->is_inst = 1;
 692         else
 693                 priv->is_inst = 0;
 694
 695         if (flags & SPI_XFER_END)
 696                 priv->cs_change = 1;
 697         else
 698                 priv->cs_change = 0;
 699
 700         zynqmp_qspi_transfer(priv);
 701
 702         return 0;
 703 }
 704
 705 static const struct dm_spi_ops zynqmp_qspi_ops = {
 706         .claim_bus      = zynqmp_qspi_claim_bus,
 707         .release_bus    = zynqmp_qspi_release_bus,
 708         .xfer           = zynqmp_qspi_xfer,
 709         .set_speed      = zynqmp_qspi_set_speed,
 710         .set_mode       = zynqmp_qspi_set_mode,
 711 };
 712
 713 static const struct udevice_id zynqmp_qspi_ids[] = {
 714         { .compatible = "xlnx,zynqmp-qspi-1.0" },
 715         { .compatible = "xlnx,versal-qspi-1.0" },
 716         { }
 717 };
 718
 719 U_BOOT_DRIVER(zynqmp_qspi) = {
 720         .name   = "zynqmp_qspi",
 721         .id     = UCLASS_SPI,
 722         .of_match = zynqmp_qspi_ids,
 723         .ops    = &zynqmp_qspi_ops,
 724         .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
 725         .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
 726         .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
 727         .probe  = zynqmp_qspi_probe,
 728 };