drivers/spi/zynqmp_gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/cache.h>
  13 #include <asm/io.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <malloc.h>
  17 #include <memalign.h>
  18 #include <spi.h>
  19 #include <ubi_uboot.h>
  20 #include <wait_bit.h>
  21 #include <dm/device_compat.h>
  22 #include <linux/bitops.h>
  23 #include <linux/err.h>
  24
  25 #define GQSPI_GFIFO_STRT_MODE_MASK      BIT(29)
  26 #define GQSPI_CONFIG_MODE_EN_MASK       (3 << 30)
  27 #define GQSPI_CONFIG_DMA_MODE           (2 << 30)
  28 #define GQSPI_CONFIG_CPHA_MASK          BIT(2)
  29 #define GQSPI_CONFIG_CPOL_MASK          BIT(1)
  30
  31 /*
  32  * QSPI Interrupt Registers bit Masks
  33  *
  34  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  35  * bit definitions.
  36  */
  37 #define GQSPI_IXR_TXNFULL_MASK          0x00000004 /* QSPI TX FIFO Overflow */
  38 #define GQSPI_IXR_TXFULL_MASK           0x00000008 /* QSPI TX FIFO is full */
  39 #define GQSPI_IXR_RXNEMTY_MASK          0x00000010 /* QSPI RX FIFO Not Empty */
  40 #define GQSPI_IXR_GFEMTY_MASK           0x00000080 /* QSPI Generic FIFO Empty */
  41 #define GQSPI_IXR_ALL_MASK              (GQSPI_IXR_TXNFULL_MASK | \
  42                                          GQSPI_IXR_RXNEMTY_MASK)
  43
  44 /*
  45  * QSPI Enable Register bit Masks
  46  *
  47  * This register is used to enable or disable the QSPI controller
  48  */
  49 #define GQSPI_ENABLE_ENABLE_MASK        0x00000001 /* QSPI Enable Bit Mask */
  50
  51 #define GQSPI_GFIFO_LOW_BUS             BIT(14)
  52 #define GQSPI_GFIFO_CS_LOWER            BIT(12)
  53 #define GQSPI_GFIFO_UP_BUS              BIT(15)
  54 #define GQSPI_GFIFO_CS_UPPER            BIT(13)
  55 #define GQSPI_SPI_MODE_QSPI             (3 << 10)
  56 #define GQSPI_SPI_MODE_SPI              BIT(10)
  57 #define GQSPI_SPI_MODE_DUAL_SPI         (2 << 10)
  58 #define GQSPI_IMD_DATA_CS_ASSERT        5
  59 #define GQSPI_IMD_DATA_CS_DEASSERT      5
  60 #define GQSPI_GFIFO_TX                  BIT(16)
  61 #define GQSPI_GFIFO_RX                  BIT(17)
  62 #define GQSPI_GFIFO_STRIPE_MASK         BIT(18)
  63 #define GQSPI_GFIFO_IMD_MASK            0xFF
  64 #define GQSPI_GFIFO_EXP_MASK            BIT(9)
  65 #define GQSPI_GFIFO_DATA_XFR_MASK       BIT(8)
  66 #define GQSPI_STRT_GEN_FIFO             BIT(28)
  67 #define GQSPI_GEN_FIFO_STRT_MOD         BIT(29)
  68 #define GQSPI_GFIFO_WP_HOLD             BIT(19)
  69 #define GQSPI_BAUD_DIV_MASK             (7 << 3)
  70 #define GQSPI_DFLT_BAUD_RATE_DIV        BIT(3)
  71 #define GQSPI_GFIFO_ALL_INT_MASK        0xFBE
  72 #define GQSPI_DMA_DST_I_STS_DONE        BIT(1)
  73 #define GQSPI_DMA_DST_I_STS_MASK        0xFE
  74 #define MODEBITS                        0x6
  75
  76 #define GQSPI_GFIFO_SELECT              BIT(0)
  77 #define GQSPI_FIFO_THRESHOLD            1
  78
  79 #define SPI_XFER_ON_BOTH                0
  80 #define SPI_XFER_ON_LOWER               1
  81 #define SPI_XFER_ON_UPPER               2
  82
  83 #define GQSPI_DMA_ALIGN                 0x4
  84 #define GQSPI_MAX_BAUD_RATE_VAL         7
  85 #define GQSPI_DFLT_BAUD_RATE_VAL        2
  86
  87 #define GQSPI_TIMEOUT                   100000000
  88
  89 #define GQSPI_BAUD_DIV_SHIFT            2
  90 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
  91 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
  92 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
  93 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
  94 #define GQSPI_USE_DATA_DLY              0x1
  95 #define GQSPI_USE_DATA_DLY_SHIFT        31
  96 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
  97 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
  98 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
  99 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
 100 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
 101 #define IOU_TAPDLY_BYPASS_OFST          0xFF180390
 102 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK    0x00000020
 103 #define GQSPI_FREQ_40MHZ                40000000
 104 #define GQSPI_FREQ_100MHZ               100000000
 105 #define GQSPI_FREQ_150MHZ               150000000
 106 #define IOU_TAPDLY_BYPASS_MASK          0x7
 107
 108 #define GQSPI_REG_OFFSET                0x100
 109 #define GQSPI_DMA_REG_OFFSET            0x800
 110
 111 /* QSPI register offsets */
 112 struct zynqmp_qspi_regs {
 113         u32 confr;      /* 0x00 */
 114         u32 isr;        /* 0x04 */
 115         u32 ier;        /* 0x08 */
 116         u32 idisr;      /* 0x0C */
 117         u32 imaskr;     /* 0x10 */
 118         u32 enbr;       /* 0x14 */
 119         u32 dr;         /* 0x18 */
 120         u32 txd0r;      /* 0x1C */
 121         u32 drxr;       /* 0x20 */
 122         u32 sicr;       /* 0x24 */
 123         u32 txftr;      /* 0x28 */
 124         u32 rxftr;      /* 0x2C */
 125         u32 gpior;      /* 0x30 */
 126         u32 reserved0;  /* 0x34 */
 127         u32 lpbkdly;    /* 0x38 */
 128         u32 reserved1;  /* 0x3C */
 129         u32 genfifo;    /* 0x40 */
 130         u32 gqspisel;   /* 0x44 */
 131         u32 reserved2;  /* 0x48 */
 132         u32 gqfifoctrl; /* 0x4C */
 133         u32 gqfthr;     /* 0x50 */
 134         u32 gqpollcfg;  /* 0x54 */
 135         u32 gqpollto;   /* 0x58 */
 136         u32 gqxfersts;  /* 0x5C */
 137         u32 gqfifosnap; /* 0x60 */
 138         u32 gqrxcpy;    /* 0x64 */
 139         u32 reserved3[36];      /* 0x68 */
 140         u32 gqspidlyadj;        /* 0xF8 */
 141 };
 142
 143 struct zynqmp_qspi_dma_regs {
 144         u32 dmadst;     /* 0x00 */
 145         u32 dmasize;    /* 0x04 */
 146         u32 dmasts;     /* 0x08 */
 147         u32 dmactrl;    /* 0x0C */
 148         u32 reserved0;  /* 0x10 */
 149         u32 dmaisr;     /* 0x14 */
 150         u32 dmaier;     /* 0x18 */
 151         u32 dmaidr;     /* 0x1C */
 152         u32 dmaimr;     /* 0x20 */
 153         u32 dmactrl2;   /* 0x24 */
 154         u32 dmadstmsb;  /* 0x28 */
 155 };
 156
 157 DECLARE_GLOBAL_DATA_PTR;
 158
 159 struct zynqmp_qspi_platdata {
 160         struct zynqmp_qspi_regs *regs;
 161         struct zynqmp_qspi_dma_regs *dma_regs;
 162         u32 frequency;
 163         u32 speed_hz;
 164 };
 165
 166 struct zynqmp_qspi_priv {
 167         struct zynqmp_qspi_regs *regs;
 168         struct zynqmp_qspi_dma_regs *dma_regs;
 169         const void *tx_buf;
 170         void *rx_buf;
 171         unsigned int len;
 172         int bytes_to_transfer;
 173         int bytes_to_receive;
 174         unsigned int is_inst;
 175         unsigned int cs_change:1;
 176 };
 177
 178 static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
 179 {
 180         struct zynqmp_qspi_platdata *plat = bus->platdata;
 181
 182         debug("%s\n", __func__);
 183
 184         plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
 185                                                  GQSPI_REG_OFFSET);
 186         plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
 187                           (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
 188
 189         return 0;
 190 }
 191
 192 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 193 {
 194         u32 config_reg;
 195         struct zynqmp_qspi_regs *regs = priv->regs;
 196
 197         writel(GQSPI_GFIFO_SELECT, &regs->gqspisel);
 198         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 199         writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 200         writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
 201         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
 202
 203         config_reg = readl(&regs->confr);
 204         config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 205                         GQSPI_CONFIG_MODE_EN_MASK);
 206         config_reg |= GQSPI_CONFIG_DMA_MODE |
 207                       GQSPI_GFIFO_WP_HOLD |
 208                       GQSPI_DFLT_BAUD_RATE_DIV;
 209         writel(config_reg, &regs->confr);
 210
 211         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 212 }
 213
 214 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
 215 {
 216         u32 gqspi_fifo_reg = 0;
 217
 218         gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
 219                          GQSPI_GFIFO_CS_LOWER;
 220
 221         return gqspi_fifo_reg;
 222 }
 223
 224 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 225                                       u32 gqspi_fifo_reg)
 226 {
 227         struct zynqmp_qspi_regs *regs = priv->regs;
 228         int ret = 0;
 229
 230         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 231                                 GQSPI_TIMEOUT, 1);
 232         if (ret)
 233                 printf("%s Timeout\n", __func__);
 234
 235         writel(gqspi_fifo_reg, &regs->genfifo);
 236 }
 237
 238 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 239 {
 240         u32 gqspi_fifo_reg = 0;
 241
 242         if (is_on) {
 243                 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
 244                 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
 245                                   GQSPI_IMD_DATA_CS_ASSERT;
 246         } else {
 247                 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
 248                 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
 249         }
 250
 251         debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 252
 253         zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 254 }
 255
 256 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 257 {
 258         struct zynqmp_qspi_platdata *plat = bus->platdata;
 259         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 260         struct zynqmp_qspi_regs *regs = priv->regs;
 261         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 262         u32 reqhz = 0;
 263
 264         clk_rate = plat->frequency;
 265         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 266
 267         debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 268               __func__, reqhz, clk_rate, baudrateval);
 269
 270         if (reqhz < GQSPI_FREQ_40MHZ) {
 271                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 272                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 273                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 274         } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 275                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 276                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 277                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 278                 lpbkdlyadj = readl(&regs->lpbkdly);
 279                 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
 280                 datadlyadj = readl(&regs->gqspidlyadj);
 281                 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 282                                 | (GQSPI_DATA_DLY_ADJ_VALUE <<
 283                                         GQSPI_DATA_DLY_ADJ_SHIFT));
 284         } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 285                 lpbkdlyadj = readl(&regs->lpbkdly);
 286                 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
 287                                 GQSPI_LPBK_DLY_ADJ_DLY_0);
 288         }
 289
 290         zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
 291                           tapdlybypass);
 292         writel(lpbkdlyadj, &regs->lpbkdly);
 293         writel(datadlyadj, &regs->gqspidlyadj);
 294 }
 295
 296 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
 297 {
 298         struct zynqmp_qspi_platdata *plat = bus->platdata;
 299         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 300         struct zynqmp_qspi_regs *regs = priv->regs;
 301         u32 confr;
 302         u8 baud_rate_val = 0;
 303
 304         debug("%s\n", __func__);
 305         if (speed > plat->frequency)
 306                 speed = plat->frequency;
 307
 308         /* Set the clock frequency */
 309         confr = readl(&regs->confr);
 310         if (speed == 0) {
 311                 /* Set baudrate x8, if the freq is 0 */
 312                 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 313         } else if (plat->speed_hz != speed) {
 314                 while ((baud_rate_val < 8) &&
 315                        ((plat->frequency /
 316                        (2 << baud_rate_val)) > speed))
 317                         baud_rate_val++;
 318
 319                 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
 320                         baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 321
 322                 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
 323         }
 324         confr &= ~GQSPI_BAUD_DIV_MASK;
 325         confr |= (baud_rate_val << 3);
 326         writel(confr, &regs->confr);
 327
 328         zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
 329         debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
 330
 331         return 0;
 332 }
 333
 334 static int zynqmp_qspi_probe(struct udevice *bus)
 335 {
 336         struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
 337         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 338         struct clk clk;
 339         unsigned long clock;
 340         int ret;
 341
 342         debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
 343
 344         priv->regs = plat->regs;
 345         priv->dma_regs = plat->dma_regs;
 346
 347         ret = clk_get_by_index(bus, 0, &clk);
 348         if (ret < 0) {
 349                 dev_err(dev, "failed to get clock\n");
 350                 return ret;
 351         }
 352
 353         clock = clk_get_rate(&clk);
 354         if (IS_ERR_VALUE(clock)) {
 355                 dev_err(dev, "failed to get rate\n");
 356                 return clock;
 357         }
 358         debug("%s: CLK %ld\n", __func__, clock);
 359
 360         ret = clk_enable(&clk);
 361         if (ret && ret != -ENOSYS) {
 362                 dev_err(dev, "failed to enable clock\n");
 363                 return ret;
 364         }
 365         plat->frequency = clock;
 366         plat->speed_hz = plat->frequency / 2;
 367
 368         /* init the zynq spi hw */
 369         zynqmp_qspi_init_hw(priv);
 370
 371         return 0;
 372 }
 373
 374 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
 375 {
 376         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 377         struct zynqmp_qspi_regs *regs = priv->regs;
 378         u32 confr;
 379
 380         debug("%s\n", __func__);
 381         /* Set the SPI Clock phase and polarities */
 382         confr = readl(&regs->confr);
 383         confr &= ~(GQSPI_CONFIG_CPHA_MASK |
 384                    GQSPI_CONFIG_CPOL_MASK);
 385
 386         if (mode & SPI_CPHA)
 387                 confr |= GQSPI_CONFIG_CPHA_MASK;
 388         if (mode & SPI_CPOL)
 389                 confr |= GQSPI_CONFIG_CPOL_MASK;
 390
 391         writel(confr, &regs->confr);
 392
 393         return 0;
 394 }
 395
 396 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 397 {
 398         u32 data;
 399         int ret = 0;
 400         struct zynqmp_qspi_regs *regs = priv->regs;
 401         u32 *buf = (u32 *)priv->tx_buf;
 402         u32 len = size;
 403
 404         debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
 405               size);
 406
 407         while (size) {
 408                 ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
 409                                         GQSPI_TIMEOUT, 1);
 410                 if (ret) {
 411                         printf("%s: Timeout\n", __func__);
 412                         return ret;
 413                 }
 414
 415                 if (size >= 4) {
 416                         writel(*buf, &regs->txd0r);
 417                         buf++;
 418                         size -= 4;
 419                 } else {
 420                         switch (size) {
 421                         case 1:
 422                                 data = *((u8 *)buf);
 423                                 buf += 1;
 424                                 data |= GENMASK(31, 8);
 425                                 break;
 426                         case 2:
 427                                 data = *((u16 *)buf);
 428                                 buf += 2;
 429                                 data |= GENMASK(31, 16);
 430                                 break;
 431                         case 3:
 432                                 data = *((u16 *)buf);
 433                                 buf += 2;
 434                                 data |= (*((u8 *)buf) << 16);
 435                                 buf += 1;
 436                                 data |= GENMASK(31, 24);
 437                                 break;
 438                         }
 439                         writel(data, &regs->txd0r);
 440                         size = 0;
 441                 }
 442         }
 443
 444         priv->tx_buf += len;
 445         return 0;
 446 }
 447
 448 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
 449 {
 450         u32 gen_fifo_cmd;
 451         u32 bytecount = 0;
 452
 453         while (priv->len) {
 454                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 455                 gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
 456                 gen_fifo_cmd |= *(u8 *)priv->tx_buf;
 457                 bytecount++;
 458                 priv->len--;
 459                 priv->tx_buf = (u8 *)priv->tx_buf + 1;
 460
 461                 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
 462
 463                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 464         }
 465 }
 466
 467 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
 468                                 u32 *gen_fifo_cmd)
 469 {
 470         u32 expval = 8;
 471         u32 len;
 472
 473         while (1) {
 474                 if (priv->len > 255) {
 475                         if (priv->len & (1 << expval)) {
 476                                 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
 477                                 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
 478                                 *gen_fifo_cmd |= expval;
 479                                 priv->len -= (1 << expval);
 480                                 return expval;
 481                         }
 482                         expval++;
 483                 } else {
 484                         *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
 485                                           GQSPI_GFIFO_EXP_MASK);
 486                         *gen_fifo_cmd |= (u8)priv->len;
 487                         len = (u8)priv->len;
 488                         priv->len  = 0;
 489                         return len;
 490                 }
 491         }
 492 }
 493
 494 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
 495 {
 496         u32 gen_fifo_cmd;
 497         u32 len;
 498         int ret = 0;
 499
 500         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 501         gen_fifo_cmd |= GQSPI_GFIFO_TX |
 502                         GQSPI_GFIFO_DATA_XFR_MASK;
 503
 504         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 505
 506         while (priv->len) {
 507                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 508                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 509
 510                 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
 511
 512                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 513                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 514                                                        1 << len);
 515                 else
 516                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 517                                                        len);
 518
 519                 if (ret)
 520                         return ret;
 521         }
 522         return ret;
 523 }
 524
 525 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 526                                  u32 gen_fifo_cmd, u32 *buf)
 527 {
 528         u32 addr;
 529         u32 size, len;
 530         u32 actuallen = priv->len;
 531         int ret = 0;
 532         struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 533
 534         writel((unsigned long)buf, &dma_regs->dmadst);
 535         writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
 536         writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 537         addr = (unsigned long)buf;
 538         size = roundup(priv->len, ARCH_DMA_MINALIGN);
 539         flush_dcache_range(addr, addr + size);
 540
 541         while (priv->len) {
 542                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 543                 if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
 544                     (len % ARCH_DMA_MINALIGN)) {
 545                         gen_fifo_cmd &= ~GENMASK(7, 0);
 546                         gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
 547                 }
 548                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 549
 550                 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 551         }
 552
 553         ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
 554                                 1, GQSPI_TIMEOUT, 1);
 555         if (ret) {
 556                 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
 557                 return -ETIMEDOUT;
 558         }
 559
 560         writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
 561
 562         debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 563               (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
 564               actuallen);
 565
 566         if (buf != priv->rx_buf)
 567                 memcpy(priv->rx_buf, buf, actuallen);
 568
 569         return 0;
 570 }
 571
 572 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
 573 {
 574         u32 gen_fifo_cmd;
 575         u32 *buf;
 576         u32 actuallen = priv->len;
 577
 578         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 579         gen_fifo_cmd |= GQSPI_GFIFO_RX |
 580                         GQSPI_GFIFO_DATA_XFR_MASK;
 581
 582         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 583
 584         /*
 585          * Check if receive buffer is aligned to 4 byte and length
 586          * is multiples of four byte as we are using dma to receive.
 587          */
 588         if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
 589             !(actuallen % GQSPI_DMA_ALIGN)) {
 590                 buf = (u32 *)priv->rx_buf;
 591                 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 592         }
 593
 594         ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
 595                                                   GQSPI_DMA_ALIGN));
 596         buf = (u32 *)tmp;
 597         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 598 }
 599
 600 static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
 601 {
 602         int ret = 0;
 603
 604         if (priv->is_inst) {
 605                 if (priv->tx_buf)
 606                         zynqmp_qspi_genfifo_cmd(priv);
 607                 else
 608                         return -EINVAL;
 609         } else {
 610                 if (priv->tx_buf)
 611                         ret = zynqmp_qspi_genfifo_fill_tx(priv);
 612                 else if (priv->rx_buf)
 613                         ret = zynqmp_qspi_genfifo_fill_rx(priv);
 614                 else
 615                         return -EINVAL;
 616         }
 617         return ret;
 618 }
 619
 620 static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
 621 {
 622         static unsigned int cs_change = 1;
 623         int status = 0;
 624
 625         debug("%s\n", __func__);
 626
 627         while (1) {
 628                 /* Select the chip if required */
 629                 if (cs_change)
 630                         zynqmp_qspi_chipselect(priv, 1);
 631
 632                 cs_change = priv->cs_change;
 633
 634                 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
 635                         status = -EINVAL;
 636                         break;
 637                 }
 638
 639                 /* Request the transfer */
 640                 if (priv->len) {
 641                         status = zynqmp_qspi_start_transfer(priv);
 642                         priv->is_inst = 0;
 643                         if (status < 0)
 644                                 break;
 645                 }
 646
 647                 if (cs_change)
 648                         /* Deselect the chip */
 649                         zynqmp_qspi_chipselect(priv, 0);
 650                 break;
 651         }
 652
 653         return status;
 654 }
 655
 656 static int zynqmp_qspi_claim_bus(struct udevice *dev)
 657 {
 658         struct udevice *bus = dev->parent;
 659         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 660         struct zynqmp_qspi_regs *regs = priv->regs;
 661
 662         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 663
 664         return 0;
 665 }
 666
 667 static int zynqmp_qspi_release_bus(struct udevice *dev)
 668 {
 669         struct udevice *bus = dev->parent;
 670         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 671         struct zynqmp_qspi_regs *regs = priv->regs;
 672
 673         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 674
 675         return 0;
 676 }
 677
 678 int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
 679                      void *din, unsigned long flags)
 680 {
 681         struct udevice *bus = dev->parent;
 682         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 683
 684         debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
 685               (unsigned long)priv, bitlen, (unsigned long)dout);
 686         debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
 687
 688         priv->tx_buf = dout;
 689         priv->rx_buf = din;
 690         priv->len = bitlen / 8;
 691
 692         /*
 693          * Assume that the beginning of a transfer with bits to
 694          * transmit must contain a device command.
 695          */
 696         if (dout && flags & SPI_XFER_BEGIN)
 697                 priv->is_inst = 1;
 698         else
 699                 priv->is_inst = 0;
 700
 701         if (flags & SPI_XFER_END)
 702                 priv->cs_change = 1;
 703         else
 704                 priv->cs_change = 0;
 705
 706         zynqmp_qspi_transfer(priv);
 707
 708         return 0;
 709 }
 710
 711 static const struct dm_spi_ops zynqmp_qspi_ops = {
 712         .claim_bus      = zynqmp_qspi_claim_bus,
 713         .release_bus    = zynqmp_qspi_release_bus,
 714         .xfer           = zynqmp_qspi_xfer,
 715         .set_speed      = zynqmp_qspi_set_speed,
 716         .set_mode       = zynqmp_qspi_set_mode,
 717 };
 718
 719 static const struct udevice_id zynqmp_qspi_ids[] = {
 720         { .compatible = "xlnx,zynqmp-qspi-1.0" },
 721         { .compatible = "xlnx,versal-qspi-1.0" },
 722         { }
 723 };
 724
 725 U_BOOT_DRIVER(zynqmp_qspi) = {
 726         .name   = "zynqmp_qspi",
 727         .id     = UCLASS_SPI,
 728         .of_match = zynqmp_qspi_ids,
 729         .ops    = &zynqmp_qspi_ops,
 730         .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
 731         .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
 732         .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
 733         .probe  = zynqmp_qspi_probe,
 734 };