drivers/spi/zynqmp_gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/cache.h>
  13 #include <asm/io.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <malloc.h>
  17 #include <memalign.h>
  18 #include <spi.h>
  19 #include <spi-mem.h>
  20 #include <ubi_uboot.h>
  21 #include <wait_bit.h>
  22 #include <dm/device_compat.h>
  23 #include <linux/bitops.h>
  24 #include <linux/err.h>
  25
  26 #define GQSPI_GFIFO_STRT_MODE_MASK      BIT(29)
  27 #define GQSPI_CONFIG_MODE_EN_MASK       (3 << 30)
  28 #define GQSPI_CONFIG_DMA_MODE           (2 << 30)
  29 #define GQSPI_CONFIG_CPHA_MASK          BIT(2)
  30 #define GQSPI_CONFIG_CPOL_MASK          BIT(1)
  31
  32 /*
  33  * QSPI Interrupt Registers bit Masks
  34  *
  35  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  36  * bit definitions.
  37  */
  38 #define GQSPI_IXR_TXNFULL_MASK          0x00000004 /* QSPI TX FIFO Overflow */
  39 #define GQSPI_IXR_TXFULL_MASK           0x00000008 /* QSPI TX FIFO is full */
  40 #define GQSPI_IXR_RXNEMTY_MASK          0x00000010 /* QSPI RX FIFO Not Empty */
  41 #define GQSPI_IXR_GFEMTY_MASK           0x00000080 /* QSPI Generic FIFO Empty */
  42 #define GQSPI_IXR_ALL_MASK              (GQSPI_IXR_TXNFULL_MASK | \
  43                                          GQSPI_IXR_RXNEMTY_MASK)
  44
  45 /*
  46  * QSPI Enable Register bit Masks
  47  *
  48  * This register is used to enable or disable the QSPI controller
  49  */
  50 #define GQSPI_ENABLE_ENABLE_MASK        0x00000001 /* QSPI Enable Bit Mask */
  51
  52 #define GQSPI_GFIFO_LOW_BUS             BIT(14)
  53 #define GQSPI_GFIFO_CS_LOWER            BIT(12)
  54 #define GQSPI_GFIFO_UP_BUS              BIT(15)
  55 #define GQSPI_GFIFO_CS_UPPER            BIT(13)
  56 #define GQSPI_SPI_MODE_QSPI             (3 << 10)
  57 #define GQSPI_SPI_MODE_SPI              BIT(10)
  58 #define GQSPI_SPI_MODE_DUAL_SPI         (2 << 10)
  59 #define GQSPI_IMD_DATA_CS_ASSERT        5
  60 #define GQSPI_IMD_DATA_CS_DEASSERT      5
  61 #define GQSPI_GFIFO_TX                  BIT(16)
  62 #define GQSPI_GFIFO_RX                  BIT(17)
  63 #define GQSPI_GFIFO_STRIPE_MASK         BIT(18)
  64 #define GQSPI_GFIFO_IMD_MASK            0xFF
  65 #define GQSPI_GFIFO_EXP_MASK            BIT(9)
  66 #define GQSPI_GFIFO_DATA_XFR_MASK       BIT(8)
  67 #define GQSPI_STRT_GEN_FIFO             BIT(28)
  68 #define GQSPI_GEN_FIFO_STRT_MOD         BIT(29)
  69 #define GQSPI_GFIFO_WP_HOLD             BIT(19)
  70 #define GQSPI_BAUD_DIV_MASK             (7 << 3)
  71 #define GQSPI_DFLT_BAUD_RATE_DIV        BIT(3)
  72 #define GQSPI_GFIFO_ALL_INT_MASK        0xFBE
  73 #define GQSPI_DMA_DST_I_STS_DONE        BIT(1)
  74 #define GQSPI_DMA_DST_I_STS_MASK        0xFE
  75 #define MODEBITS                        0x6
  76
  77 #define GQSPI_GFIFO_SELECT              BIT(0)
  78 #define GQSPI_FIFO_THRESHOLD            1
  79
  80 #define SPI_XFER_ON_BOTH                0
  81 #define SPI_XFER_ON_LOWER               1
  82 #define SPI_XFER_ON_UPPER               2
  83
  84 #define GQSPI_DMA_ALIGN                 0x4
  85 #define GQSPI_MAX_BAUD_RATE_VAL         7
  86 #define GQSPI_DFLT_BAUD_RATE_VAL        2
  87
  88 #define GQSPI_TIMEOUT                   100000000
  89
  90 #define GQSPI_BAUD_DIV_SHIFT            2
  91 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
  92 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
  93 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
  94 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
  95 #define GQSPI_USE_DATA_DLY              0x1
  96 #define GQSPI_USE_DATA_DLY_SHIFT        31
  97 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
  98 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
  99 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
 100 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
 101 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
 102 #define IOU_TAPDLY_BYPASS_OFST          0xFF180390
 103 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK    0x00000020
 104 #define GQSPI_FREQ_40MHZ                40000000
 105 #define GQSPI_FREQ_100MHZ               100000000
 106 #define GQSPI_FREQ_150MHZ               150000000
 107 #define IOU_TAPDLY_BYPASS_MASK          0x7
 108
 109 #define GQSPI_REG_OFFSET                0x100
 110 #define GQSPI_DMA_REG_OFFSET            0x800
 111
 112 /* QSPI register offsets */
 113 struct zynqmp_qspi_regs {
 114         u32 confr;      /* 0x00 */
 115         u32 isr;        /* 0x04 */
 116         u32 ier;        /* 0x08 */
 117         u32 idisr;      /* 0x0C */
 118         u32 imaskr;     /* 0x10 */
 119         u32 enbr;       /* 0x14 */
 120         u32 dr;         /* 0x18 */
 121         u32 txd0r;      /* 0x1C */
 122         u32 drxr;       /* 0x20 */
 123         u32 sicr;       /* 0x24 */
 124         u32 txftr;      /* 0x28 */
 125         u32 rxftr;      /* 0x2C */
 126         u32 gpior;      /* 0x30 */
 127         u32 reserved0;  /* 0x34 */
 128         u32 lpbkdly;    /* 0x38 */
 129         u32 reserved1;  /* 0x3C */
 130         u32 genfifo;    /* 0x40 */
 131         u32 gqspisel;   /* 0x44 */
 132         u32 reserved2;  /* 0x48 */
 133         u32 gqfifoctrl; /* 0x4C */
 134         u32 gqfthr;     /* 0x50 */
 135         u32 gqpollcfg;  /* 0x54 */
 136         u32 gqpollto;   /* 0x58 */
 137         u32 gqxfersts;  /* 0x5C */
 138         u32 gqfifosnap; /* 0x60 */
 139         u32 gqrxcpy;    /* 0x64 */
 140         u32 reserved3[36];      /* 0x68 */
 141         u32 gqspidlyadj;        /* 0xF8 */
 142 };
 143
 144 struct zynqmp_qspi_dma_regs {
 145         u32 dmadst;     /* 0x00 */
 146         u32 dmasize;    /* 0x04 */
 147         u32 dmasts;     /* 0x08 */
 148         u32 dmactrl;    /* 0x0C */
 149         u32 reserved0;  /* 0x10 */
 150         u32 dmaisr;     /* 0x14 */
 151         u32 dmaier;     /* 0x18 */
 152         u32 dmaidr;     /* 0x1C */
 153         u32 dmaimr;     /* 0x20 */
 154         u32 dmactrl2;   /* 0x24 */
 155         u32 dmadstmsb;  /* 0x28 */
 156 };
 157
 158 DECLARE_GLOBAL_DATA_PTR;
 159
 160 struct zynqmp_qspi_plat {
 161         struct zynqmp_qspi_regs *regs;
 162         struct zynqmp_qspi_dma_regs *dma_regs;
 163         u32 frequency;
 164         u32 speed_hz;
 165 };
 166
 167 struct zynqmp_qspi_priv {
 168         struct zynqmp_qspi_regs *regs;
 169         struct zynqmp_qspi_dma_regs *dma_regs;
 170         const void *tx_buf;
 171         void *rx_buf;
 172         unsigned int len;
 173         int bytes_to_transfer;
 174         int bytes_to_receive;
 175         const struct spi_mem_op *op;
 176 };
 177
 178 static int zynqmp_qspi_of_to_plat(struct udevice *bus)
 179 {
 180         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 181
 182         debug("%s\n", __func__);
 183
 184         plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
 185                                                  GQSPI_REG_OFFSET);
 186         plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
 187                           (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
 188
 189         return 0;
 190 }
 191
 192 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 193 {
 194         u32 config_reg;
 195         struct zynqmp_qspi_regs *regs = priv->regs;
 196
 197         writel(GQSPI_GFIFO_SELECT, &regs->gqspisel);
 198         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 199         writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 200         writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
 201         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
 202
 203         config_reg = readl(&regs->confr);
 204         config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 205                         GQSPI_CONFIG_MODE_EN_MASK);
 206         config_reg |= GQSPI_CONFIG_DMA_MODE |
 207                       GQSPI_GFIFO_WP_HOLD |
 208                       GQSPI_DFLT_BAUD_RATE_DIV;
 209         writel(config_reg, &regs->confr);
 210
 211         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 212 }
 213
 214 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
 215 {
 216         u32 gqspi_fifo_reg = 0;
 217
 218         gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
 219                          GQSPI_GFIFO_CS_LOWER;
 220
 221         return gqspi_fifo_reg;
 222 }
 223
 224 static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
 225 {
 226         switch (buswidth) {
 227         case 1:
 228                 return GQSPI_SPI_MODE_SPI;
 229         case 2:
 230                 return GQSPI_SPI_MODE_DUAL_SPI;
 231         case 4:
 232                 return GQSPI_SPI_MODE_QSPI;
 233         default:
 234                 debug("Unsupported bus width %u\n", buswidth);
 235                 return GQSPI_SPI_MODE_SPI;
 236         }
 237 }
 238
 239 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 240                                       u32 gqspi_fifo_reg)
 241 {
 242         struct zynqmp_qspi_regs *regs = priv->regs;
 243         int ret = 0;
 244
 245         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 246                                 GQSPI_TIMEOUT, 1);
 247         if (ret)
 248                 printf("%s Timeout\n", __func__);
 249
 250         writel(gqspi_fifo_reg, &regs->genfifo);
 251 }
 252
 253 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 254 {
 255         u32 gqspi_fifo_reg = 0;
 256
 257         if (is_on) {
 258                 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
 259                 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
 260                                   GQSPI_IMD_DATA_CS_ASSERT;
 261         } else {
 262                 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
 263                 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
 264         }
 265
 266         debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 267
 268         zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 269 }
 270
 271 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 272 {
 273         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 274         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 275         struct zynqmp_qspi_regs *regs = priv->regs;
 276         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 277         u32 reqhz = 0;
 278
 279         clk_rate = plat->frequency;
 280         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 281
 282         debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 283               __func__, reqhz, clk_rate, baudrateval);
 284
 285         if (reqhz < GQSPI_FREQ_40MHZ) {
 286                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 287                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 288                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 289         } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 290                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 291                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 292                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 293                 lpbkdlyadj = readl(&regs->lpbkdly);
 294                 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
 295                 datadlyadj = readl(&regs->gqspidlyadj);
 296                 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 297                                 | (GQSPI_DATA_DLY_ADJ_VALUE <<
 298                                         GQSPI_DATA_DLY_ADJ_SHIFT));
 299         } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 300                 lpbkdlyadj = readl(&regs->lpbkdly);
 301                 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
 302                                 GQSPI_LPBK_DLY_ADJ_DLY_0);
 303         }
 304
 305         zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
 306                           tapdlybypass);
 307         writel(lpbkdlyadj, &regs->lpbkdly);
 308         writel(datadlyadj, &regs->gqspidlyadj);
 309 }
 310
 311 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
 312 {
 313         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 314         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 315         struct zynqmp_qspi_regs *regs = priv->regs;
 316         u32 confr;
 317         u8 baud_rate_val = 0;
 318
 319         debug("%s\n", __func__);
 320         if (speed > plat->frequency)
 321                 speed = plat->frequency;
 322
 323         if (plat->speed_hz != speed) {
 324                 /* Set the clock frequency */
 325                 /* If speed == 0, default to lowest speed */
 326                 while ((baud_rate_val < 8) &&
 327                        ((plat->frequency /
 328                        (2 << baud_rate_val)) > speed))
 329                         baud_rate_val++;
 330
 331                 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
 332                         baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 333
 334                 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
 335
 336                 confr = readl(&regs->confr);
 337                 confr &= ~GQSPI_BAUD_DIV_MASK;
 338                 confr |= (baud_rate_val << 3);
 339                 writel(confr, &regs->confr);
 340                 zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
 341
 342                 debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
 343         }
 344
 345         return 0;
 346 }
 347
 348 static int zynqmp_qspi_probe(struct udevice *bus)
 349 {
 350         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 351         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 352         struct clk clk;
 353         unsigned long clock;
 354         int ret;
 355
 356         debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
 357
 358         priv->regs = plat->regs;
 359         priv->dma_regs = plat->dma_regs;
 360
 361         ret = clk_get_by_index(bus, 0, &clk);
 362         if (ret < 0) {
 363                 dev_err(bus, "failed to get clock\n");
 364                 return ret;
 365         }
 366
 367         clock = clk_get_rate(&clk);
 368         if (IS_ERR_VALUE(clock)) {
 369                 dev_err(bus, "failed to get rate\n");
 370                 return clock;
 371         }
 372         debug("%s: CLK %ld\n", __func__, clock);
 373
 374         ret = clk_enable(&clk);
 375         if (ret) {
 376                 dev_err(bus, "failed to enable clock\n");
 377                 return ret;
 378         }
 379         plat->frequency = clock;
 380         plat->speed_hz = plat->frequency / 2;
 381
 382         /* init the zynq spi hw */
 383         zynqmp_qspi_init_hw(priv);
 384
 385         return 0;
 386 }
 387
 388 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
 389 {
 390         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 391         struct zynqmp_qspi_regs *regs = priv->regs;
 392         u32 confr;
 393
 394         debug("%s\n", __func__);
 395         /* Set the SPI Clock phase and polarities */
 396         confr = readl(&regs->confr);
 397         confr &= ~(GQSPI_CONFIG_CPHA_MASK |
 398                    GQSPI_CONFIG_CPOL_MASK);
 399
 400         if (mode & SPI_CPHA)
 401                 confr |= GQSPI_CONFIG_CPHA_MASK;
 402         if (mode & SPI_CPOL)
 403                 confr |= GQSPI_CONFIG_CPOL_MASK;
 404
 405         writel(confr, &regs->confr);
 406
 407         return 0;
 408 }
 409
 410 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 411 {
 412         u32 data;
 413         int ret = 0;
 414         struct zynqmp_qspi_regs *regs = priv->regs;
 415         u32 *buf = (u32 *)priv->tx_buf;
 416         u32 len = size;
 417
 418         debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
 419               size);
 420
 421         while (size) {
 422                 ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
 423                                         GQSPI_TIMEOUT, 1);
 424                 if (ret) {
 425                         printf("%s: Timeout\n", __func__);
 426                         return ret;
 427                 }
 428
 429                 if (size >= 4) {
 430                         writel(*buf, &regs->txd0r);
 431                         buf++;
 432                         size -= 4;
 433                 } else {
 434                         switch (size) {
 435                         case 1:
 436                                 data = *((u8 *)buf);
 437                                 buf += 1;
 438                                 data |= GENMASK(31, 8);
 439                                 break;
 440                         case 2:
 441                                 data = *((u16 *)buf);
 442                                 buf += 2;
 443                                 data |= GENMASK(31, 16);
 444                                 break;
 445                         case 3:
 446                                 data = *buf;
 447                                 buf += 3;
 448                                 data |= GENMASK(31, 24);
 449                                 break;
 450                         }
 451                         writel(data, &regs->txd0r);
 452                         size = 0;
 453                 }
 454         }
 455
 456         priv->tx_buf += len;
 457         return 0;
 458 }
 459
 460 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
 461 {
 462         const struct spi_mem_op *op = priv->op;
 463         u32 gen_fifo_cmd;
 464         u8 i, dummy_cycles, addr;
 465
 466         /* Send opcode */
 467         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 468         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
 469         gen_fifo_cmd |= GQSPI_GFIFO_TX;
 470         gen_fifo_cmd |= op->cmd.opcode;
 471         zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 472
 473         /* Send address */
 474         for (i = 0; i < op->addr.nbytes; i++) {
 475                 addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
 476
 477                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 478                 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
 479                 gen_fifo_cmd |= GQSPI_GFIFO_TX;
 480                 gen_fifo_cmd |= addr;
 481
 482                 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
 483
 484                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 485         }
 486
 487         /* Send dummy */
 488         if (op->dummy.nbytes) {
 489                 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
 490
 491                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 492                 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
 493                 gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
 494                 gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
 495                 gen_fifo_cmd |= dummy_cycles;
 496                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 497         }
 498 }
 499
 500 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
 501                                 u32 *gen_fifo_cmd)
 502 {
 503         u32 expval = 8;
 504         u32 len;
 505
 506         while (1) {
 507                 if (priv->len > 255) {
 508                         if (priv->len & (1 << expval)) {
 509                                 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
 510                                 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
 511                                 *gen_fifo_cmd |= expval;
 512                                 priv->len -= (1 << expval);
 513                                 return expval;
 514                         }
 515                         expval++;
 516                 } else {
 517                         *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
 518                                           GQSPI_GFIFO_EXP_MASK);
 519                         *gen_fifo_cmd |= (u8)priv->len;
 520                         len = (u8)priv->len;
 521                         priv->len  = 0;
 522                         return len;
 523                 }
 524         }
 525 }
 526
 527 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
 528 {
 529         u32 gen_fifo_cmd;
 530         u32 len;
 531         int ret = 0;
 532
 533         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 534         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
 535         gen_fifo_cmd |= GQSPI_GFIFO_TX |
 536                         GQSPI_GFIFO_DATA_XFR_MASK;
 537
 538         while (priv->len) {
 539                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 540                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 541
 542                 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
 543
 544                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 545                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 546                                                        1 << len);
 547                 else
 548                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 549                                                        len);
 550
 551                 if (ret)
 552                         return ret;
 553         }
 554         return ret;
 555 }
 556
 557 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 558                                  u32 gen_fifo_cmd, u32 *buf)
 559 {
 560         u32 addr;
 561         u32 size, len;
 562         u32 actuallen = priv->len;
 563         int ret = 0;
 564         struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 565
 566         writel((unsigned long)buf, &dma_regs->dmadst);
 567         writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
 568         writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 569         addr = (unsigned long)buf;
 570         size = roundup(priv->len, ARCH_DMA_MINALIGN);
 571         flush_dcache_range(addr, addr + size);
 572
 573         while (priv->len) {
 574                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 575                 if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
 576                     (len % ARCH_DMA_MINALIGN)) {
 577                         gen_fifo_cmd &= ~GENMASK(7, 0);
 578                         gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
 579                 }
 580                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 581
 582                 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 583         }
 584
 585         ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
 586                                 1, GQSPI_TIMEOUT, 1);
 587         if (ret) {
 588                 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
 589                 return -ETIMEDOUT;
 590         }
 591
 592         writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
 593
 594         debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 595               (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
 596               actuallen);
 597
 598         if (buf != priv->rx_buf)
 599                 memcpy(priv->rx_buf, buf, actuallen);
 600
 601         return 0;
 602 }
 603
 604 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
 605 {
 606         u32 gen_fifo_cmd;
 607         u32 *buf;
 608         u32 actuallen = priv->len;
 609
 610         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 611         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
 612         gen_fifo_cmd |= GQSPI_GFIFO_RX |
 613                         GQSPI_GFIFO_DATA_XFR_MASK;
 614
 615         /*
 616          * Check if receive buffer is aligned to 4 byte and length
 617          * is multiples of four byte as we are using dma to receive.
 618          */
 619         if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
 620             !(actuallen % GQSPI_DMA_ALIGN)) {
 621                 buf = (u32 *)priv->rx_buf;
 622                 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 623         }
 624
 625         ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
 626                                                   GQSPI_DMA_ALIGN));
 627         buf = (u32 *)tmp;
 628         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 629 }
 630
 631 static int zynqmp_qspi_claim_bus(struct udevice *dev)
 632 {
 633         struct udevice *bus = dev->parent;
 634         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 635         struct zynqmp_qspi_regs *regs = priv->regs;
 636
 637         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 638
 639         return 0;
 640 }
 641
 642 static int zynqmp_qspi_release_bus(struct udevice *dev)
 643 {
 644         struct udevice *bus = dev->parent;
 645         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 646         struct zynqmp_qspi_regs *regs = priv->regs;
 647
 648         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 649
 650         return 0;
 651 }
 652
 653 static int zynqmp_qspi_exec_op(struct spi_slave *slave,
 654                                const struct spi_mem_op *op)
 655 {
 656         struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 657         int ret = 0;
 658
 659         priv->op = op;
 660         priv->tx_buf = op->data.buf.out;
 661         priv->rx_buf = op->data.buf.in;
 662         priv->len = op->data.nbytes;
 663
 664         zynqmp_qspi_chipselect(priv, 1);
 665
 666         /* Send opcode, addr, dummy */
 667         zynqmp_qspi_genfifo_cmd(priv);
 668
 669         /* Request the transfer */
 670         if (op->data.dir == SPI_MEM_DATA_IN)
 671                 ret = zynqmp_qspi_genfifo_fill_rx(priv);
 672         else if (op->data.dir == SPI_MEM_DATA_OUT)
 673                 ret = zynqmp_qspi_genfifo_fill_tx(priv);
 674
 675         zynqmp_qspi_chipselect(priv, 0);
 676
 677         return ret;
 678 }
 679
 680 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
 681         .exec_op = zynqmp_qspi_exec_op,
 682 };
 683
 684 static const struct dm_spi_ops zynqmp_qspi_ops = {
 685         .claim_bus      = zynqmp_qspi_claim_bus,
 686         .release_bus    = zynqmp_qspi_release_bus,
 687         .set_speed      = zynqmp_qspi_set_speed,
 688         .set_mode       = zynqmp_qspi_set_mode,
 689         .mem_ops        = &zynqmp_qspi_mem_ops,
 690 };
 691
 692 static const struct udevice_id zynqmp_qspi_ids[] = {
 693         { .compatible = "xlnx,zynqmp-qspi-1.0" },
 694         { .compatible = "xlnx,versal-qspi-1.0" },
 695         { }
 696 };
 697
 698 U_BOOT_DRIVER(zynqmp_qspi) = {
 699         .name   = "zynqmp_qspi",
 700         .id     = UCLASS_SPI,
 701         .of_match = zynqmp_qspi_ids,
 702         .ops    = &zynqmp_qspi_ops,
 703         .of_to_plat = zynqmp_qspi_of_to_plat,
 704         .plat_auto      = sizeof(struct zynqmp_qspi_plat),
 705         .priv_auto      = sizeof(struct zynqmp_qspi_priv),
 706         .probe  = zynqmp_qspi_probe,
 707 };