drivers/spi/zynqmp_gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/cache.h>
  13 #include <asm/io.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <malloc.h>
  17 #include <memalign.h>
  18 #include <spi.h>
  19 #include <spi-mem.h>
  20 #include <ubi_uboot.h>
  21 #include <wait_bit.h>
  22 #include <dm/device_compat.h>
  23 #include <linux/bitops.h>
  24 #include <linux/err.h>
  25 #include <linux/sizes.h>
  26 #include <zynqmp_firmware.h>
  27
  28 #define GQSPI_GFIFO_STRT_MODE_MASK      BIT(29)
  29 #define GQSPI_CONFIG_MODE_EN_MASK       (3 << 30)
  30 #define GQSPI_CONFIG_DMA_MODE           (2 << 30)
  31 #define GQSPI_CONFIG_CPHA_MASK          BIT(2)
  32 #define GQSPI_CONFIG_CPOL_MASK          BIT(1)
  33
  34 /*
  35  * QSPI Interrupt Registers bit Masks
  36  *
  37  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  38  * bit definitions.
  39  */
  40 #define GQSPI_IXR_TXNFULL_MASK          0x00000004 /* QSPI TX FIFO Overflow */
  41 #define GQSPI_IXR_TXFULL_MASK           0x00000008 /* QSPI TX FIFO is full */
  42 #define GQSPI_IXR_TXFIFOEMPTY_MASK      0x00000100 /* QSPI TX FIFO is Empty */
  43 #define GQSPI_IXR_RXNEMTY_MASK          0x00000010 /* QSPI RX FIFO Not Empty */
  44 #define GQSPI_IXR_GFEMTY_MASK           0x00000080 /* QSPI Generic FIFO Empty */
  45 #define GQSPI_IXR_GFNFULL_MASK          0x00000200 /* QSPI GENFIFO not full */
  46 #define GQSPI_IXR_ALL_MASK              (GQSPI_IXR_TXNFULL_MASK | \
  47                                          GQSPI_IXR_RXNEMTY_MASK)
  48
  49 /*
  50  * QSPI Enable Register bit Masks
  51  *
  52  * This register is used to enable or disable the QSPI controller
  53  */
  54 #define GQSPI_ENABLE_ENABLE_MASK        0x00000001 /* QSPI Enable Bit Mask */
  55
  56 #define GQSPI_GFIFO_LOW_BUS             BIT(14)
  57 #define GQSPI_GFIFO_CS_LOWER            BIT(12)
  58 #define GQSPI_GFIFO_UP_BUS              BIT(15)
  59 #define GQSPI_GFIFO_CS_UPPER            BIT(13)
  60 #define GQSPI_SPI_MODE_QSPI             (3 << 10)
  61 #define GQSPI_SPI_MODE_SPI              BIT(10)
  62 #define GQSPI_SPI_MODE_DUAL_SPI         (2 << 10)
  63 #define GQSPI_IMD_DATA_CS_ASSERT        5
  64 #define GQSPI_IMD_DATA_CS_DEASSERT      5
  65 #define GQSPI_GFIFO_TX                  BIT(16)
  66 #define GQSPI_GFIFO_RX                  BIT(17)
  67 #define GQSPI_GFIFO_STRIPE_MASK         BIT(18)
  68 #define GQSPI_GFIFO_IMD_MASK            0xFF
  69 #define GQSPI_GFIFO_EXP_MASK            BIT(9)
  70 #define GQSPI_GFIFO_DATA_XFR_MASK       BIT(8)
  71 #define GQSPI_STRT_GEN_FIFO             BIT(28)
  72 #define GQSPI_GEN_FIFO_STRT_MOD         BIT(29)
  73 #define GQSPI_GFIFO_WP_HOLD             BIT(19)
  74 #define GQSPI_BAUD_DIV_MASK             (7 << 3)
  75 #define GQSPI_DFLT_BAUD_RATE_DIV        BIT(3)
  76 #define GQSPI_GFIFO_ALL_INT_MASK        0xFBE
  77 #define GQSPI_DMA_DST_I_STS_DONE        BIT(1)
  78 #define GQSPI_DMA_DST_I_STS_MASK        0xFE
  79 #define MODEBITS                        0x6
  80
  81 #define GQSPI_GFIFO_SELECT              BIT(0)
  82 #define GQSPI_FIFO_THRESHOLD            1
  83 #define GQSPI_GENFIFO_THRESHOLD         31
  84
  85 #define SPI_XFER_ON_BOTH                0
  86 #define SPI_XFER_ON_LOWER               1
  87 #define SPI_XFER_ON_UPPER               2
  88
  89 #define GQSPI_DMA_ALIGN                 0x4
  90 #define GQSPI_MAX_BAUD_RATE_VAL         7
  91 #define GQSPI_DFLT_BAUD_RATE_VAL        2
  92
  93 #define GQSPI_TIMEOUT                   100000000
  94
  95 #define GQSPI_BAUD_DIV_SHIFT            2
  96 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
  97 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x1
  98 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
  99 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
 100 #define GQSPI_USE_DATA_DLY              0x1
 101 #define GQSPI_USE_DATA_DLY_SHIFT        31
 102 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
 103 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
 104 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
 105 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
 106 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
 107 #define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \
 108                                  IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \
 109                                 0xFF180390 : 0xF103003C
 110 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK    0x00000020
 111 #define GQSPI_FREQ_37_5MHZ              37500000
 112 #define GQSPI_FREQ_40MHZ                40000000
 113 #define GQSPI_FREQ_100MHZ               100000000
 114 #define GQSPI_FREQ_150MHZ               150000000
 115 #define IOU_TAPDLY_BYPASS_MASK          0x7
 116
 117 #define GQSPI_REG_OFFSET                0x100
 118 #define GQSPI_DMA_REG_OFFSET            0x800
 119
 120 /* QSPI register offsets */
 121 struct zynqmp_qspi_regs {
 122         u32 confr;      /* 0x00 */
 123         u32 isr;        /* 0x04 */
 124         u32 ier;        /* 0x08 */
 125         u32 idisr;      /* 0x0C */
 126         u32 imaskr;     /* 0x10 */
 127         u32 enbr;       /* 0x14 */
 128         u32 dr;         /* 0x18 */
 129         u32 txd0r;      /* 0x1C */
 130         u32 drxr;       /* 0x20 */
 131         u32 sicr;       /* 0x24 */
 132         u32 txftr;      /* 0x28 */
 133         u32 rxftr;      /* 0x2C */
 134         u32 gpior;      /* 0x30 */
 135         u32 reserved0;  /* 0x34 */
 136         u32 lpbkdly;    /* 0x38 */
 137         u32 reserved1;  /* 0x3C */
 138         u32 genfifo;    /* 0x40 */
 139         u32 gqspisel;   /* 0x44 */
 140         u32 reserved2;  /* 0x48 */
 141         u32 gqfifoctrl; /* 0x4C */
 142         u32 gqfthr;     /* 0x50 */
 143         u32 gqpollcfg;  /* 0x54 */
 144         u32 gqpollto;   /* 0x58 */
 145         u32 gqxfersts;  /* 0x5C */
 146         u32 gqfifosnap; /* 0x60 */
 147         u32 gqrxcpy;    /* 0x64 */
 148         u32 reserved3[36];      /* 0x68 */
 149         u32 gqspidlyadj;        /* 0xF8 */
 150 };
 151
 152 struct zynqmp_qspi_dma_regs {
 153         u32 dmadst;     /* 0x00 */
 154         u32 dmasize;    /* 0x04 */
 155         u32 dmasts;     /* 0x08 */
 156         u32 dmactrl;    /* 0x0C */
 157         u32 reserved0;  /* 0x10 */
 158         u32 dmaisr;     /* 0x14 */
 159         u32 dmaier;     /* 0x18 */
 160         u32 dmaidr;     /* 0x1C */
 161         u32 dmaimr;     /* 0x20 */
 162         u32 dmactrl2;   /* 0x24 */
 163         u32 dmadstmsb;  /* 0x28 */
 164 };
 165
 166 struct zynqmp_qspi_plat {
 167         struct zynqmp_qspi_regs *regs;
 168         struct zynqmp_qspi_dma_regs *dma_regs;
 169         u32 frequency;
 170         u32 speed_hz;
 171         unsigned int io_mode;
 172 };
 173
 174 struct zynqmp_qspi_priv {
 175         struct zynqmp_qspi_regs *regs;
 176         struct zynqmp_qspi_dma_regs *dma_regs;
 177         const void *tx_buf;
 178         void *rx_buf;
 179         unsigned int len;
 180         unsigned int io_mode;
 181         int bytes_to_transfer;
 182         int bytes_to_receive;
 183         const struct spi_mem_op *op;
 184 };
 185
 186 __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
 187 {
 188         return 0;
 189 }
 190
 191 static int zynqmp_qspi_of_to_plat(struct udevice *bus)
 192 {
 193         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 194
 195         debug("%s\n", __func__);
 196
 197         plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
 198                                                  GQSPI_REG_OFFSET);
 199         plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
 200                           (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
 201
 202         plat->io_mode = dev_read_bool(bus, "has-io-mode");
 203
 204         return 0;
 205 }
 206
 207 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 208 {
 209         u32 config_reg;
 210         struct zynqmp_qspi_regs *regs = priv->regs;
 211
 212         writel(GQSPI_GFIFO_SELECT, &regs->gqspisel);
 213         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 214         writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 215         writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
 216         writel(GQSPI_GENFIFO_THRESHOLD, &regs->gqfthr);
 217         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
 218         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 219
 220         config_reg = readl(&regs->confr);
 221         config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 222                         GQSPI_CONFIG_MODE_EN_MASK);
 223         config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV;
 224         config_reg |= GQSPI_GFIFO_STRT_MODE_MASK;
 225         if (!priv->io_mode)
 226                 config_reg |= GQSPI_CONFIG_DMA_MODE;
 227
 228         writel(config_reg, &regs->confr);
 229
 230         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 231 }
 232
 233 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
 234 {
 235         u32 gqspi_fifo_reg = 0;
 236
 237         gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
 238                          GQSPI_GFIFO_CS_LOWER;
 239
 240         return gqspi_fifo_reg;
 241 }
 242
 243 static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
 244 {
 245         switch (buswidth) {
 246         case 1:
 247                 return GQSPI_SPI_MODE_SPI;
 248         case 2:
 249                 return GQSPI_SPI_MODE_DUAL_SPI;
 250         case 4:
 251                 return GQSPI_SPI_MODE_QSPI;
 252         default:
 253                 debug("Unsupported bus width %u\n", buswidth);
 254                 return GQSPI_SPI_MODE_SPI;
 255         }
 256 }
 257
 258 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 259                                       u32 gqspi_fifo_reg)
 260 {
 261         struct zynqmp_qspi_regs *regs = priv->regs;
 262         u32 config_reg, ier;
 263         int ret = 0;
 264
 265         writel(gqspi_fifo_reg, &regs->genfifo);
 266
 267         config_reg = readl(&regs->confr);
 268         /* Manual start if needed */
 269         config_reg |= GQSPI_STRT_GEN_FIFO;
 270         writel(config_reg, &regs->confr);
 271
 272         /* Enable interrupts */
 273         ier = readl(&regs->ier);
 274         ier |= GQSPI_IXR_GFEMTY_MASK;
 275         writel(ier, &regs->ier);
 276
 277         /* Wait until the gen fifo is empty to write the new command */
 278         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 279                                 GQSPI_TIMEOUT, 1);
 280         if (ret)
 281                 printf("%s Timeout\n", __func__);
 282
 283 }
 284
 285 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 286 {
 287         u32 gqspi_fifo_reg = 0;
 288
 289         if (is_on) {
 290                 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
 291                 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
 292                                   GQSPI_IMD_DATA_CS_ASSERT;
 293         } else {
 294                 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
 295                 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
 296         }
 297
 298         debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 299
 300         zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 301 }
 302
 303 static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 304 {
 305         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 306         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 307         struct zynqmp_qspi_regs *regs = priv->regs;
 308         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 309         u32 reqhz = 0;
 310
 311         clk_rate = plat->frequency;
 312         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 313
 314         debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 315               __func__, reqhz, clk_rate, baudrateval);
 316
 317         if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
 318               IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
 319                 if (reqhz <= GQSPI_FREQ_40MHZ) {
 320                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 321                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 322                 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 323                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 324                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 325                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
 326                         datadlyadj = (GQSPI_USE_DATA_DLY <<
 327                                       GQSPI_USE_DATA_DLY_SHIFT) |
 328                                        (GQSPI_DATA_DLY_ADJ_VALUE <<
 329                                         GQSPI_DATA_DLY_ADJ_SHIFT);
 330                 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 331                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
 332                                       GQSPI_LPBK_DLY_ADJ_DLY_0;
 333                 }
 334                 zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
 335                                   IOU_TAPDLY_BYPASS_MASK, tapdlybypass);
 336         } else {
 337                 if (reqhz <= GQSPI_FREQ_37_5MHZ) {
 338                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 339                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 340                 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 341                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 342                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 343                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
 344                         datadlyadj = GQSPI_USE_DATA_DLY <<
 345                                       GQSPI_USE_DATA_DLY_SHIFT;
 346                 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 347                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
 348                                       (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
 349                                        GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT);
 350                 }
 351                 writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST);
 352         }
 353         writel(lpbkdlyadj, &regs->lpbkdly);
 354         writel(datadlyadj, &regs->gqspidlyadj);
 355 }
 356
 357 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
 358 {
 359         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 360         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 361         struct zynqmp_qspi_regs *regs = priv->regs;
 362         u32 confr;
 363         u8 baud_rate_val = 0;
 364
 365         debug("%s\n", __func__);
 366         if (speed > plat->frequency)
 367                 speed = plat->frequency;
 368
 369         if (plat->speed_hz != speed) {
 370                 /* Set the clock frequency */
 371                 /* If speed == 0, default to lowest speed */
 372                 while ((baud_rate_val < 8) &&
 373                        ((plat->frequency /
 374                        (2 << baud_rate_val)) > speed))
 375                         baud_rate_val++;
 376
 377                 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
 378                         baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 379
 380                 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
 381
 382                 confr = readl(&regs->confr);
 383                 confr &= ~GQSPI_BAUD_DIV_MASK;
 384                 confr |= (baud_rate_val << 3);
 385                 writel(confr, &regs->confr);
 386                 zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
 387
 388                 debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int zynqmp_qspi_probe(struct udevice *bus)
 395 {
 396         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 397         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 398         struct clk clk;
 399         unsigned long clock;
 400         int ret;
 401
 402         debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
 403
 404         priv->regs = plat->regs;
 405         priv->dma_regs = plat->dma_regs;
 406         priv->io_mode = plat->io_mode;
 407
 408         ret = clk_get_by_index(bus, 0, &clk);
 409         if (ret < 0) {
 410                 dev_err(bus, "failed to get clock\n");
 411                 return ret;
 412         }
 413
 414         clock = clk_get_rate(&clk);
 415         if (IS_ERR_VALUE(clock)) {
 416                 dev_err(bus, "failed to get rate\n");
 417                 return clock;
 418         }
 419         debug("%s: CLK %ld\n", __func__, clock);
 420
 421         ret = clk_enable(&clk);
 422         if (ret) {
 423                 dev_err(bus, "failed to enable clock\n");
 424                 return ret;
 425         }
 426         plat->frequency = clock;
 427         plat->speed_hz = plat->frequency / 2;
 428
 429         /* init the zynq spi hw */
 430         zynqmp_qspi_init_hw(priv);
 431
 432         return 0;
 433 }
 434
 435 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
 436 {
 437         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 438         struct zynqmp_qspi_regs *regs = priv->regs;
 439         u32 confr;
 440
 441         debug("%s\n", __func__);
 442         /* Set the SPI Clock phase and polarities */
 443         confr = readl(&regs->confr);
 444         confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
 445
 446         if (mode & SPI_CPHA)
 447                 confr |= GQSPI_CONFIG_CPHA_MASK;
 448         if (mode & SPI_CPOL)
 449                 confr |= GQSPI_CONFIG_CPOL_MASK;
 450
 451         writel(confr, &regs->confr);
 452
 453         return 0;
 454 }
 455
 456 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 457 {
 458         u32 data;
 459         int ret = 0;
 460         struct zynqmp_qspi_regs *regs = priv->regs;
 461         u32 *buf = (u32 *)priv->tx_buf;
 462         u32 len = size;
 463
 464         debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
 465               size);
 466
 467         while (size) {
 468                 ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
 469                                         GQSPI_TIMEOUT, 1);
 470                 if (ret) {
 471                         printf("%s: Timeout\n", __func__);
 472                         return ret;
 473                 }
 474
 475                 if (size >= 4) {
 476                         writel(*buf, &regs->txd0r);
 477                         buf++;
 478                         size -= 4;
 479                 } else {
 480                         switch (size) {
 481                         case 1:
 482                                 data = *((u8 *)buf);
 483                                 buf += 1;
 484                                 data |= GENMASK(31, 8);
 485                                 break;
 486                         case 2:
 487                                 data = *((u16 *)buf);
 488                                 buf += 2;
 489                                 data |= GENMASK(31, 16);
 490                                 break;
 491                         case 3:
 492                                 data = *buf;
 493                                 buf += 3;
 494                                 data |= GENMASK(31, 24);
 495                                 break;
 496                         }
 497                         writel(data, &regs->txd0r);
 498                         size = 0;
 499                 }
 500         }
 501
 502         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
 503                                 GQSPI_TIMEOUT, 1);
 504         if (ret) {
 505                 printf("%s: Timeout\n", __func__);
 506                 return ret;
 507         }
 508
 509         priv->tx_buf += len;
 510         return 0;
 511 }
 512
 513 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
 514 {
 515         const struct spi_mem_op *op = priv->op;
 516         u32 gen_fifo_cmd;
 517         u8 i, dummy_cycles, addr;
 518
 519         /* Send opcode */
 520         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 521         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
 522         gen_fifo_cmd |= GQSPI_GFIFO_TX;
 523         gen_fifo_cmd |= op->cmd.opcode;
 524         zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 525
 526         /* Send address */
 527         for (i = 0; i < op->addr.nbytes; i++) {
 528                 addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
 529
 530                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 531                 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
 532                 gen_fifo_cmd |= GQSPI_GFIFO_TX;
 533                 gen_fifo_cmd |= addr;
 534
 535                 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
 536
 537                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 538         }
 539
 540         /* Send dummy */
 541         if (op->dummy.nbytes) {
 542                 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
 543
 544                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 545                 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
 546                 gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
 547                 gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
 548                 gen_fifo_cmd |= dummy_cycles;
 549                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 550         }
 551 }
 552
 553 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
 554                                 u32 *gen_fifo_cmd)
 555 {
 556         u32 expval = 8;
 557         u32 len;
 558
 559         while (1) {
 560                 if (priv->len > 255) {
 561                         if (priv->len & (1 << expval)) {
 562                                 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
 563                                 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
 564                                 *gen_fifo_cmd |= expval;
 565                                 priv->len -= (1 << expval);
 566                                 return expval;
 567                         }
 568                         expval++;
 569                 } else {
 570                         *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
 571                                           GQSPI_GFIFO_EXP_MASK);
 572                         *gen_fifo_cmd |= (u8)priv->len;
 573                         len = (u8)priv->len;
 574                         priv->len  = 0;
 575                         return len;
 576                 }
 577         }
 578 }
 579
 580 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
 581 {
 582         u32 gen_fifo_cmd;
 583         u32 len;
 584         int ret = 0;
 585
 586         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 587         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
 588         gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
 589
 590         while (priv->len) {
 591                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 592                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 593
 594                 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
 595
 596                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 597                         ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
 598                 else
 599                         ret = zynqmp_qspi_fill_tx_fifo(priv, len);
 600
 601                 if (ret)
 602                         return ret;
 603         }
 604         return ret;
 605 }
 606
 607 static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
 608                                 u32 gen_fifo_cmd, u32 *buf)
 609 {
 610         u32 len;
 611         u32 actuallen = priv->len;
 612         u32 config_reg, ier, isr;
 613         u32 timeout = GQSPI_TIMEOUT;
 614         struct zynqmp_qspi_regs *regs = priv->regs;
 615         u32 last_bits;
 616         u32 *traverse = buf;
 617
 618         while (priv->len) {
 619                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 620                 /* If exponent bit is set, reset immediate to be 2^len */
 621                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 622                         priv->bytes_to_receive = (1 << len);
 623                 else
 624                         priv->bytes_to_receive = len;
 625                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 626                 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 627                 /* Manual start */
 628                 config_reg = readl(&regs->confr);
 629                 config_reg |= GQSPI_STRT_GEN_FIFO;
 630                 writel(config_reg, &regs->confr);
 631                 /* Enable RX interrupts for IO mode */
 632                 ier = readl(&regs->ier);
 633                 ier |= GQSPI_IXR_ALL_MASK;
 634                 writel(ier, &regs->ier);
 635                 while (priv->bytes_to_receive && timeout) {
 636                         isr = readl(&regs->isr);
 637                         if (isr & GQSPI_IXR_RXNEMTY_MASK) {
 638                                 if (priv->bytes_to_receive >= 4) {
 639                                         *traverse = readl(&regs->drxr);
 640                                         traverse++;
 641                                         priv->bytes_to_receive -= 4;
 642                                 } else {
 643                                         last_bits = readl(&regs->drxr);
 644                                         memcpy(traverse, &last_bits,
 645                                                priv->bytes_to_receive);
 646                                         priv->bytes_to_receive = 0;
 647                                 }
 648                                 timeout = GQSPI_TIMEOUT;
 649                         } else {
 650                                 udelay(1);
 651                                 timeout--;
 652                         }
 653                 }
 654
 655                 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 656                       (unsigned long)buf, (unsigned long)priv->rx_buf,
 657                       *buf, actuallen);
 658                 if (!timeout) {
 659                         printf("IO timeout: %d\n", readl(&regs->isr));
 660                         return -1;
 661                 }
 662         }
 663
 664         return 0;
 665 }
 666
 667 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 668                                  u32 gen_fifo_cmd, u32 *buf)
 669 {
 670         unsigned long addr;
 671         u32 size;
 672         u32 actuallen = priv->len;
 673         u32 totallen = priv->len;
 674         int ret = 0;
 675         struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 676
 677         while (totallen) {
 678                 if (totallen >= SZ_512M)
 679                         priv->len = SZ_256M;
 680                 else
 681                         priv->len = totallen;
 682
 683                 totallen -= priv->len; /* Save remaining bytes length to read */
 684                 actuallen = priv->len; /* Actual number of bytes reading */
 685
 686                 writel(lower_32_bits((unsigned long)buf), &dma_regs->dmadst);
 687                 writel(upper_32_bits((unsigned long)buf) & GENMASK(11, 0),
 688                                                         &dma_regs->dmadstmsb);
 689                 writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
 690                 writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 691                 addr = (unsigned long)buf;
 692                 size = roundup(priv->len, GQSPI_DMA_ALIGN);
 693                 flush_dcache_range(addr, addr + size);
 694
 695                 while (priv->len) {
 696                         zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 697                         zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 698
 699                         debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 700                 }
 701
 702                 ret = wait_for_bit_le32(&dma_regs->dmaisr,
 703                                         GQSPI_DMA_DST_I_STS_DONE, 1,
 704                                         GQSPI_TIMEOUT, 1);
 705                 if (ret) {
 706                         printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
 707                         return -ETIMEDOUT;
 708                 }
 709
 710                 writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
 711
 712                 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 713                       (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
 714                       actuallen);
 715
 716                 if (buf != priv->rx_buf)
 717                         memcpy(priv->rx_buf, buf, actuallen);
 718
 719                 buf = (u32 *)((u8 *)buf + actuallen);
 720                 priv->rx_buf = (u8 *)priv->rx_buf + actuallen;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
 727 {
 728         u32 gen_fifo_cmd;
 729         u32 *buf;
 730         u32 actuallen = priv->len;
 731
 732         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 733         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
 734         gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;
 735
 736         /*
 737          * Check if receive buffer is aligned to 4 byte and length
 738          * is multiples of four byte as we are using dma to receive.
 739          */
 740         if ((!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
 741              !(actuallen % GQSPI_DMA_ALIGN)) || priv->io_mode) {
 742                 buf = (u32 *)priv->rx_buf;
 743                 if (priv->io_mode)
 744                         return zynqmp_qspi_start_io(priv, gen_fifo_cmd, buf);
 745                 else
 746                         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 747         }
 748
 749         ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, GQSPI_DMA_ALIGN));
 750         buf = (u32 *)tmp;
 751         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 752 }
 753
 754 static int zynqmp_qspi_claim_bus(struct udevice *dev)
 755 {
 756         struct udevice *bus = dev->parent;
 757         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 758         struct zynqmp_qspi_regs *regs = priv->regs;
 759
 760         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 761
 762         return 0;
 763 }
 764
 765 static int zynqmp_qspi_release_bus(struct udevice *dev)
 766 {
 767         struct udevice *bus = dev->parent;
 768         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 769         struct zynqmp_qspi_regs *regs = priv->regs;
 770
 771         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 772
 773         return 0;
 774 }
 775
 776 static int zynqmp_qspi_exec_op(struct spi_slave *slave,
 777                                const struct spi_mem_op *op)
 778 {
 779         struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 780         int ret = 0;
 781
 782         priv->op = op;
 783         priv->tx_buf = op->data.buf.out;
 784         priv->rx_buf = op->data.buf.in;
 785         priv->len = op->data.nbytes;
 786
 787         zynqmp_qspi_chipselect(priv, 1);
 788
 789         /* Send opcode, addr, dummy */
 790         zynqmp_qspi_genfifo_cmd(priv);
 791
 792         /* Request the transfer */
 793         if (op->data.dir == SPI_MEM_DATA_IN)
 794                 ret = zynqmp_qspi_genfifo_fill_rx(priv);
 795         else if (op->data.dir == SPI_MEM_DATA_OUT)
 796                 ret = zynqmp_qspi_genfifo_fill_tx(priv);
 797
 798         zynqmp_qspi_chipselect(priv, 0);
 799
 800         return ret;
 801 }
 802
 803 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
 804         .exec_op = zynqmp_qspi_exec_op,
 805 };
 806
 807 static const struct dm_spi_ops zynqmp_qspi_ops = {
 808         .claim_bus      = zynqmp_qspi_claim_bus,
 809         .release_bus    = zynqmp_qspi_release_bus,
 810         .set_speed      = zynqmp_qspi_set_speed,
 811         .set_mode       = zynqmp_qspi_set_mode,
 812         .mem_ops        = &zynqmp_qspi_mem_ops,
 813 };
 814
 815 static const struct udevice_id zynqmp_qspi_ids[] = {
 816         { .compatible = "xlnx,zynqmp-qspi-1.0" },
 817         { .compatible = "xlnx,versal-qspi-1.0" },
 818         { }
 819 };
 820
 821 U_BOOT_DRIVER(zynqmp_qspi) = {
 822         .name   = "zynqmp_qspi",
 823         .id     = UCLASS_SPI,
 824         .of_match = zynqmp_qspi_ids,
 825         .ops    = &zynqmp_qspi_ops,
 826         .of_to_plat = zynqmp_qspi_of_to_plat,
 827         .plat_auto      = sizeof(struct zynqmp_qspi_plat),
 828         .priv_auto      = sizeof(struct zynqmp_qspi_priv),
 829         .probe  = zynqmp_qspi_probe,
 830 };