drivers/spi/zynqmp_gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/cache.h>
  13 #include <asm/io.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <malloc.h>
  17 #include <memalign.h>
  18 #include <spi.h>
  19 #include <spi-mem.h>
  20 #include <ubi_uboot.h>
  21 #include <wait_bit.h>
  22 #include <dm/device_compat.h>
  23 #include <linux/bitops.h>
  24 #include <linux/err.h>
  25 #include <linux/sizes.h>
  26 #include <zynqmp_firmware.h>
  27
  28 #define GQSPI_GFIFO_STRT_MODE_MASK      BIT(29)
  29 #define GQSPI_CONFIG_MODE_EN_MASK       (3 << 30)
  30 #define GQSPI_CONFIG_DMA_MODE           (2 << 30)
  31 #define GQSPI_CONFIG_CPHA_MASK          BIT(2)
  32 #define GQSPI_CONFIG_CPOL_MASK          BIT(1)
  33
  34 /*
  35  * QSPI Interrupt Registers bit Masks
  36  *
  37  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  38  * bit definitions.
  39  */
  40 #define GQSPI_IXR_TXNFULL_MASK          0x00000004 /* QSPI TX FIFO Overflow */
  41 #define GQSPI_IXR_TXFULL_MASK           0x00000008 /* QSPI TX FIFO is full */
  42 #define GQSPI_IXR_TXFIFOEMPTY_MASK      0x00000100 /* QSPI TX FIFO is Empty */
  43 #define GQSPI_IXR_RXNEMTY_MASK          0x00000010 /* QSPI RX FIFO Not Empty */
  44 #define GQSPI_IXR_GFEMTY_MASK           0x00000080 /* QSPI Generic FIFO Empty */
  45 #define GQSPI_IXR_GFNFULL_MASK          0x00000200 /* QSPI GENFIFO not full */
  46 #define GQSPI_IXR_ALL_MASK              (GQSPI_IXR_TXNFULL_MASK | \
  47                                          GQSPI_IXR_RXNEMTY_MASK)
  48
  49 /*
  50  * QSPI Enable Register bit Masks
  51  *
  52  * This register is used to enable or disable the QSPI controller
  53  */
  54 #define GQSPI_ENABLE_ENABLE_MASK        0x00000001 /* QSPI Enable Bit Mask */
  55
  56 #define GQSPI_GFIFO_LOW_BUS             BIT(14)
  57 #define GQSPI_GFIFO_CS_LOWER            BIT(12)
  58 #define GQSPI_GFIFO_UP_BUS              BIT(15)
  59 #define GQSPI_GFIFO_CS_UPPER            BIT(13)
  60 #define GQSPI_SPI_MODE_QSPI             (3 << 10)
  61 #define GQSPI_SPI_MODE_SPI              BIT(10)
  62 #define GQSPI_SPI_MODE_DUAL_SPI         (2 << 10)
  63 #define GQSPI_IMD_DATA_CS_ASSERT        5
  64 #define GQSPI_IMD_DATA_CS_DEASSERT      5
  65 #define GQSPI_GFIFO_TX                  BIT(16)
  66 #define GQSPI_GFIFO_RX                  BIT(17)
  67 #define GQSPI_GFIFO_STRIPE_MASK         BIT(18)
  68 #define GQSPI_GFIFO_IMD_MASK            0xFF
  69 #define GQSPI_GFIFO_EXP_MASK            BIT(9)
  70 #define GQSPI_GFIFO_DATA_XFR_MASK       BIT(8)
  71 #define GQSPI_STRT_GEN_FIFO             BIT(28)
  72 #define GQSPI_GEN_FIFO_STRT_MOD         BIT(29)
  73 #define GQSPI_GFIFO_WP_HOLD             BIT(19)
  74 #define GQSPI_BAUD_DIV_MASK             (7 << 3)
  75 #define GQSPI_DFLT_BAUD_RATE_DIV        BIT(3)
  76 #define GQSPI_GFIFO_ALL_INT_MASK        0xFBE
  77 #define GQSPI_DMA_DST_I_STS_DONE        BIT(1)
  78 #define GQSPI_DMA_DST_I_STS_MASK        0xFE
  79 #define MODEBITS                        0x6
  80
  81 #define GQSPI_GFIFO_SELECT              BIT(0)
  82 #define GQSPI_FIFO_THRESHOLD            1
  83 #define GQSPI_GENFIFO_THRESHOLD         31
  84
  85 #define SPI_XFER_ON_BOTH                0
  86 #define SPI_XFER_ON_LOWER               1
  87 #define SPI_XFER_ON_UPPER               2
  88
  89 #define GQSPI_DMA_ALIGN                 0x4
  90 #define GQSPI_MAX_BAUD_RATE_VAL         7
  91 #define GQSPI_DFLT_BAUD_RATE_VAL        2
  92
  93 #define GQSPI_TIMEOUT                   100000000
  94
  95 #define GQSPI_BAUD_DIV_SHIFT            2
  96 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
  97 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
  98 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
  99 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
 100 #define GQSPI_USE_DATA_DLY              0x1
 101 #define GQSPI_USE_DATA_DLY_SHIFT        31
 102 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
 103 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
 104 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
 105 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
 106 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
 107 #define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \
 108                                 0xFF180390 : 0xF103003C
 109 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK    0x00000020
 110 #define GQSPI_FREQ_37_5MHZ              37500000
 111 #define GQSPI_FREQ_40MHZ                40000000
 112 #define GQSPI_FREQ_100MHZ               100000000
 113 #define GQSPI_FREQ_150MHZ               150000000
 114 #define IOU_TAPDLY_BYPASS_MASK          0x7
 115
 116 #define GQSPI_REG_OFFSET                0x100
 117 #define GQSPI_DMA_REG_OFFSET            0x800
 118
 119 /* QSPI register offsets */
 120 struct zynqmp_qspi_regs {
 121         u32 confr;      /* 0x00 */
 122         u32 isr;        /* 0x04 */
 123         u32 ier;        /* 0x08 */
 124         u32 idisr;      /* 0x0C */
 125         u32 imaskr;     /* 0x10 */
 126         u32 enbr;       /* 0x14 */
 127         u32 dr;         /* 0x18 */
 128         u32 txd0r;      /* 0x1C */
 129         u32 drxr;       /* 0x20 */
 130         u32 sicr;       /* 0x24 */
 131         u32 txftr;      /* 0x28 */
 132         u32 rxftr;      /* 0x2C */
 133         u32 gpior;      /* 0x30 */
 134         u32 reserved0;  /* 0x34 */
 135         u32 lpbkdly;    /* 0x38 */
 136         u32 reserved1;  /* 0x3C */
 137         u32 genfifo;    /* 0x40 */
 138         u32 gqspisel;   /* 0x44 */
 139         u32 reserved2;  /* 0x48 */
 140         u32 gqfifoctrl; /* 0x4C */
 141         u32 gqfthr;     /* 0x50 */
 142         u32 gqpollcfg;  /* 0x54 */
 143         u32 gqpollto;   /* 0x58 */
 144         u32 gqxfersts;  /* 0x5C */
 145         u32 gqfifosnap; /* 0x60 */
 146         u32 gqrxcpy;    /* 0x64 */
 147         u32 reserved3[36];      /* 0x68 */
 148         u32 gqspidlyadj;        /* 0xF8 */
 149 };
 150
 151 struct zynqmp_qspi_dma_regs {
 152         u32 dmadst;     /* 0x00 */
 153         u32 dmasize;    /* 0x04 */
 154         u32 dmasts;     /* 0x08 */
 155         u32 dmactrl;    /* 0x0C */
 156         u32 reserved0;  /* 0x10 */
 157         u32 dmaisr;     /* 0x14 */
 158         u32 dmaier;     /* 0x18 */
 159         u32 dmaidr;     /* 0x1C */
 160         u32 dmaimr;     /* 0x20 */
 161         u32 dmactrl2;   /* 0x24 */
 162         u32 dmadstmsb;  /* 0x28 */
 163 };
 164
 165 struct zynqmp_qspi_plat {
 166         struct zynqmp_qspi_regs *regs;
 167         struct zynqmp_qspi_dma_regs *dma_regs;
 168         u32 frequency;
 169         u32 speed_hz;
 170         unsigned int io_mode;
 171 };
 172
 173 struct zynqmp_qspi_priv {
 174         struct zynqmp_qspi_regs *regs;
 175         struct zynqmp_qspi_dma_regs *dma_regs;
 176         const void *tx_buf;
 177         void *rx_buf;
 178         unsigned int len;
 179         unsigned int io_mode;
 180         int bytes_to_transfer;
 181         int bytes_to_receive;
 182         const struct spi_mem_op *op;
 183 };
 184
 185 static int zynqmp_qspi_of_to_plat(struct udevice *bus)
 186 {
 187         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 188
 189         debug("%s\n", __func__);
 190
 191         plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
 192                                                  GQSPI_REG_OFFSET);
 193         plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
 194                           (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
 195
 196         plat->io_mode = dev_read_bool(bus, "has-io-mode");
 197
 198         return 0;
 199 }
 200
 201 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 202 {
 203         u32 config_reg;
 204         struct zynqmp_qspi_regs *regs = priv->regs;
 205
 206         writel(GQSPI_GFIFO_SELECT, &regs->gqspisel);
 207         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 208         writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 209         writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
 210         writel(GQSPI_GENFIFO_THRESHOLD, &regs->gqfthr);
 211         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
 212         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 213
 214         config_reg = readl(&regs->confr);
 215         config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 216                         GQSPI_CONFIG_MODE_EN_MASK);
 217         config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV;
 218         config_reg |= GQSPI_GFIFO_STRT_MODE_MASK;
 219         if (!priv->io_mode)
 220                 config_reg |= GQSPI_CONFIG_DMA_MODE;
 221
 222         writel(config_reg, &regs->confr);
 223
 224         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 225 }
 226
 227 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
 228 {
 229         u32 gqspi_fifo_reg = 0;
 230
 231         gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
 232                          GQSPI_GFIFO_CS_LOWER;
 233
 234         return gqspi_fifo_reg;
 235 }
 236
 237 static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
 238 {
 239         switch (buswidth) {
 240         case 1:
 241                 return GQSPI_SPI_MODE_SPI;
 242         case 2:
 243                 return GQSPI_SPI_MODE_DUAL_SPI;
 244         case 4:
 245                 return GQSPI_SPI_MODE_QSPI;
 246         default:
 247                 debug("Unsupported bus width %u\n", buswidth);
 248                 return GQSPI_SPI_MODE_SPI;
 249         }
 250 }
 251
 252 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 253                                       u32 gqspi_fifo_reg)
 254 {
 255         struct zynqmp_qspi_regs *regs = priv->regs;
 256         u32 config_reg, ier;
 257         int ret = 0;
 258
 259         writel(gqspi_fifo_reg, &regs->genfifo);
 260
 261         config_reg = readl(&regs->confr);
 262         /* Manual start if needed */
 263         config_reg |= GQSPI_STRT_GEN_FIFO;
 264         writel(config_reg, &regs->confr);
 265
 266         /* Enable interrupts */
 267         ier = readl(&regs->ier);
 268         ier |= GQSPI_IXR_GFEMTY_MASK;
 269         writel(ier, &regs->ier);
 270
 271         /* Wait until the gen fifo is empty to write the new command */
 272         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 273                                 GQSPI_TIMEOUT, 1);
 274         if (ret)
 275                 printf("%s Timeout\n", __func__);
 276
 277 }
 278
 279 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 280 {
 281         u32 gqspi_fifo_reg = 0;
 282
 283         if (is_on) {
 284                 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
 285                 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
 286                                   GQSPI_IMD_DATA_CS_ASSERT;
 287         } else {
 288                 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
 289                 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
 290         }
 291
 292         debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 293
 294         zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 295 }
 296
 297 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 298 {
 299         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 300         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 301         struct zynqmp_qspi_regs *regs = priv->regs;
 302         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 303         u32 reqhz = 0;
 304
 305         clk_rate = plat->frequency;
 306         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 307
 308         debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 309               __func__, reqhz, clk_rate, baudrateval);
 310
 311         if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) {
 312                 if (reqhz <= GQSPI_FREQ_40MHZ) {
 313                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 314                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 315                 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 316                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 317                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 318                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
 319                         datadlyadj = (GQSPI_USE_DATA_DLY <<
 320                                       GQSPI_USE_DATA_DLY_SHIFT) |
 321                                        (GQSPI_DATA_DLY_ADJ_VALUE <<
 322                                         GQSPI_DATA_DLY_ADJ_SHIFT);
 323                 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 324                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
 325                                       GQSPI_LPBK_DLY_ADJ_DLY_0;
 326                 }
 327                 zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
 328                                   IOU_TAPDLY_BYPASS_MASK, tapdlybypass);
 329         } else {
 330                 if (reqhz <= GQSPI_FREQ_37_5MHZ) {
 331                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 332                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 333                 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 334                         tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 335                                         TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
 336                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
 337                         datadlyadj = GQSPI_USE_DATA_DLY <<
 338                                       GQSPI_USE_DATA_DLY_SHIFT;
 339                 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 340                         lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
 341                                       (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
 342                                        GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT);
 343                 }
 344                 writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST);
 345         }
 346         writel(lpbkdlyadj, &regs->lpbkdly);
 347         writel(datadlyadj, &regs->gqspidlyadj);
 348 }
 349
 350 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
 351 {
 352         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 353         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 354         struct zynqmp_qspi_regs *regs = priv->regs;
 355         u32 confr;
 356         u8 baud_rate_val = 0;
 357
 358         debug("%s\n", __func__);
 359         if (speed > plat->frequency)
 360                 speed = plat->frequency;
 361
 362         if (plat->speed_hz != speed) {
 363                 /* Set the clock frequency */
 364                 /* If speed == 0, default to lowest speed */
 365                 while ((baud_rate_val < 8) &&
 366                        ((plat->frequency /
 367                        (2 << baud_rate_val)) > speed))
 368                         baud_rate_val++;
 369
 370                 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
 371                         baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 372
 373                 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
 374
 375                 confr = readl(&regs->confr);
 376                 confr &= ~GQSPI_BAUD_DIV_MASK;
 377                 confr |= (baud_rate_val << 3);
 378                 writel(confr, &regs->confr);
 379                 zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
 380
 381                 debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int zynqmp_qspi_probe(struct udevice *bus)
 388 {
 389         struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
 390         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 391         struct clk clk;
 392         unsigned long clock;
 393         int ret;
 394
 395         debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
 396
 397         priv->regs = plat->regs;
 398         priv->dma_regs = plat->dma_regs;
 399         priv->io_mode = plat->io_mode;
 400
 401         ret = clk_get_by_index(bus, 0, &clk);
 402         if (ret < 0) {
 403                 dev_err(bus, "failed to get clock\n");
 404                 return ret;
 405         }
 406
 407         clock = clk_get_rate(&clk);
 408         if (IS_ERR_VALUE(clock)) {
 409                 dev_err(bus, "failed to get rate\n");
 410                 return clock;
 411         }
 412         debug("%s: CLK %ld\n", __func__, clock);
 413
 414         ret = clk_enable(&clk);
 415         if (ret) {
 416                 dev_err(bus, "failed to enable clock\n");
 417                 return ret;
 418         }
 419         plat->frequency = clock;
 420         plat->speed_hz = plat->frequency / 2;
 421
 422         /* init the zynq spi hw */
 423         zynqmp_qspi_init_hw(priv);
 424
 425         return 0;
 426 }
 427
 428 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
 429 {
 430         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 431         struct zynqmp_qspi_regs *regs = priv->regs;
 432         u32 confr;
 433
 434         debug("%s\n", __func__);
 435         /* Set the SPI Clock phase and polarities */
 436         confr = readl(&regs->confr);
 437         confr &= ~(GQSPI_CONFIG_CPHA_MASK |
 438                    GQSPI_CONFIG_CPOL_MASK);
 439
 440         if (mode & SPI_CPHA)
 441                 confr |= GQSPI_CONFIG_CPHA_MASK;
 442         if (mode & SPI_CPOL)
 443                 confr |= GQSPI_CONFIG_CPOL_MASK;
 444
 445         writel(confr, &regs->confr);
 446
 447         return 0;
 448 }
 449
 450 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 451 {
 452         u32 data;
 453         int ret = 0;
 454         struct zynqmp_qspi_regs *regs = priv->regs;
 455         u32 *buf = (u32 *)priv->tx_buf;
 456         u32 len = size;
 457
 458         debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
 459               size);
 460
 461         while (size) {
 462                 ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
 463                                         GQSPI_TIMEOUT, 1);
 464                 if (ret) {
 465                         printf("%s: Timeout\n", __func__);
 466                         return ret;
 467                 }
 468
 469                 if (size >= 4) {
 470                         writel(*buf, &regs->txd0r);
 471                         buf++;
 472                         size -= 4;
 473                 } else {
 474                         switch (size) {
 475                         case 1:
 476                                 data = *((u8 *)buf);
 477                                 buf += 1;
 478                                 data |= GENMASK(31, 8);
 479                                 break;
 480                         case 2:
 481                                 data = *((u16 *)buf);
 482                                 buf += 2;
 483                                 data |= GENMASK(31, 16);
 484                                 break;
 485                         case 3:
 486                                 data = *buf;
 487                                 buf += 3;
 488                                 data |= GENMASK(31, 24);
 489                                 break;
 490                         }
 491                         writel(data, &regs->txd0r);
 492                         size = 0;
 493                 }
 494         }
 495
 496         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
 497                                 GQSPI_TIMEOUT, 1);
 498         if (ret) {
 499                 printf("%s: Timeout\n", __func__);
 500                 return ret;
 501         }
 502
 503         priv->tx_buf += len;
 504         return 0;
 505 }
 506
 507 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
 508 {
 509         const struct spi_mem_op *op = priv->op;
 510         u32 gen_fifo_cmd;
 511         u8 i, dummy_cycles, addr;
 512
 513         /* Send opcode */
 514         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 515         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
 516         gen_fifo_cmd |= GQSPI_GFIFO_TX;
 517         gen_fifo_cmd |= op->cmd.opcode;
 518         zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 519
 520         /* Send address */
 521         for (i = 0; i < op->addr.nbytes; i++) {
 522                 addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
 523
 524                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 525                 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
 526                 gen_fifo_cmd |= GQSPI_GFIFO_TX;
 527                 gen_fifo_cmd |= addr;
 528
 529                 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
 530
 531                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 532         }
 533
 534         /* Send dummy */
 535         if (op->dummy.nbytes) {
 536                 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
 537
 538                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 539                 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
 540                 gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
 541                 gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
 542                 gen_fifo_cmd |= dummy_cycles;
 543                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 544         }
 545 }
 546
 547 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
 548                                 u32 *gen_fifo_cmd)
 549 {
 550         u32 expval = 8;
 551         u32 len;
 552
 553         while (1) {
 554                 if (priv->len > 255) {
 555                         if (priv->len & (1 << expval)) {
 556                                 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
 557                                 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
 558                                 *gen_fifo_cmd |= expval;
 559                                 priv->len -= (1 << expval);
 560                                 return expval;
 561                         }
 562                         expval++;
 563                 } else {
 564                         *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
 565                                           GQSPI_GFIFO_EXP_MASK);
 566                         *gen_fifo_cmd |= (u8)priv->len;
 567                         len = (u8)priv->len;
 568                         priv->len  = 0;
 569                         return len;
 570                 }
 571         }
 572 }
 573
 574 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
 575 {
 576         u32 gen_fifo_cmd;
 577         u32 len;
 578         int ret = 0;
 579
 580         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 581         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
 582         gen_fifo_cmd |= GQSPI_GFIFO_TX |
 583                         GQSPI_GFIFO_DATA_XFR_MASK;
 584
 585         while (priv->len) {
 586                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 587                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 588
 589                 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
 590
 591                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 592                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 593                                                        1 << len);
 594                 else
 595                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 596                                                        len);
 597
 598                 if (ret)
 599                         return ret;
 600         }
 601         return ret;
 602 }
 603
 604 static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
 605                                 u32 gen_fifo_cmd, u32 *buf)
 606 {
 607         u32 len;
 608         u32 actuallen = priv->len;
 609         u32 config_reg, ier, isr;
 610         u32 timeout = GQSPI_TIMEOUT;
 611         struct zynqmp_qspi_regs *regs = priv->regs;
 612         u32 last_bits;
 613         u32 *traverse = buf;
 614
 615         while (priv->len) {
 616                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 617                 /* If exponent bit is set, reset immediate to be 2^len */
 618                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 619                         priv->bytes_to_receive = (1 << len);
 620                 else
 621                         priv->bytes_to_receive = len;
 622                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 623                 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 624                 /* Manual start */
 625                 config_reg = readl(&regs->confr);
 626                 config_reg |= GQSPI_STRT_GEN_FIFO;
 627                 writel(config_reg, &regs->confr);
 628                 /* Enable RX interrupts for IO mode */
 629                 ier = readl(&regs->ier);
 630                 ier |= GQSPI_IXR_ALL_MASK;
 631                 writel(ier, &regs->ier);
 632                 while (priv->bytes_to_receive && timeout) {
 633                         isr = readl(&regs->isr);
 634                         if (isr & GQSPI_IXR_RXNEMTY_MASK) {
 635                                 if (priv->bytes_to_receive >= 4) {
 636                                         *traverse = readl(&regs->drxr);
 637                                         traverse++;
 638                                         priv->bytes_to_receive -= 4;
 639                                 } else {
 640                                         last_bits = readl(&regs->drxr);
 641                                         memcpy(traverse, &last_bits,
 642                                                priv->bytes_to_receive);
 643                                         priv->bytes_to_receive = 0;
 644                                 }
 645                                 timeout = GQSPI_TIMEOUT;
 646                         } else {
 647                                 udelay(1);
 648                                 timeout--;
 649                         }
 650                 }
 651
 652                 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 653                       (unsigned long)buf, (unsigned long)priv->rx_buf,
 654                       *buf, actuallen);
 655                 if (!timeout) {
 656                         printf("IO timeout: %d\n", readl(&regs->isr));
 657                         return -1;
 658                 }
 659         }
 660
 661         return 0;
 662 }
 663
 664 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 665                                  u32 gen_fifo_cmd, u32 *buf)
 666 {
 667         u32 addr;
 668         u32 size;
 669         u32 actuallen = priv->len;
 670         u32 totallen = priv->len;
 671         int ret = 0;
 672         struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 673
 674         while (totallen) {
 675                 if (totallen >= SZ_512M)
 676                         priv->len = SZ_256M;
 677                 else
 678                         priv->len = totallen;
 679
 680                 totallen -= priv->len; /* Save remaining bytes length to read */
 681                 actuallen = priv->len; /* Actual number of bytes reading */
 682
 683                 writel((unsigned long)buf, &dma_regs->dmadst);
 684                 writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
 685                 writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 686                 addr = (unsigned long)buf;
 687                 size = roundup(priv->len, GQSPI_DMA_ALIGN);
 688                 flush_dcache_range(addr, addr + size);
 689
 690                 while (priv->len) {
 691                         zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 692                         zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 693
 694                         debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 695                 }
 696
 697                 ret = wait_for_bit_le32(&dma_regs->dmaisr,
 698                                         GQSPI_DMA_DST_I_STS_DONE, 1,
 699                                         GQSPI_TIMEOUT, 1);
 700                 if (ret) {
 701                         printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
 702                         return -ETIMEDOUT;
 703                 }
 704
 705                 writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
 706
 707                 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 708                       (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
 709                       actuallen);
 710
 711                 if (buf != priv->rx_buf)
 712                         memcpy(priv->rx_buf, buf, actuallen);
 713
 714                 buf = (u32 *)((u8 *)buf + actuallen);
 715                 priv->rx_buf = (u8 *)priv->rx_buf + actuallen;
 716         }
 717
 718         return 0;
 719 }
 720
 721 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
 722 {
 723         u32 gen_fifo_cmd;
 724         u32 *buf;
 725         u32 actuallen = priv->len;
 726
 727         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 728         gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
 729         gen_fifo_cmd |= GQSPI_GFIFO_RX |
 730                         GQSPI_GFIFO_DATA_XFR_MASK;
 731
 732         /*
 733          * Check if receive buffer is aligned to 4 byte and length
 734          * is multiples of four byte as we are using dma to receive.
 735          */
 736         if ((!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
 737              !(actuallen % GQSPI_DMA_ALIGN)) || priv->io_mode) {
 738                 buf = (u32 *)priv->rx_buf;
 739                 if (priv->io_mode)
 740                         return zynqmp_qspi_start_io(priv, gen_fifo_cmd, buf);
 741                 else
 742                         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 743         }
 744
 745         ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
 746                                                   GQSPI_DMA_ALIGN));
 747         buf = (u32 *)tmp;
 748         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 749 }
 750
 751 static int zynqmp_qspi_claim_bus(struct udevice *dev)
 752 {
 753         struct udevice *bus = dev->parent;
 754         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 755         struct zynqmp_qspi_regs *regs = priv->regs;
 756
 757         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 758
 759         return 0;
 760 }
 761
 762 static int zynqmp_qspi_release_bus(struct udevice *dev)
 763 {
 764         struct udevice *bus = dev->parent;
 765         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 766         struct zynqmp_qspi_regs *regs = priv->regs;
 767
 768         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 769
 770         return 0;
 771 }
 772
 773 static int zynqmp_qspi_exec_op(struct spi_slave *slave,
 774                                const struct spi_mem_op *op)
 775 {
 776         struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 777         int ret = 0;
 778
 779         priv->op = op;
 780         priv->tx_buf = op->data.buf.out;
 781         priv->rx_buf = op->data.buf.in;
 782         priv->len = op->data.nbytes;
 783
 784         zynqmp_qspi_chipselect(priv, 1);
 785
 786         /* Send opcode, addr, dummy */
 787         zynqmp_qspi_genfifo_cmd(priv);
 788
 789         /* Request the transfer */
 790         if (op->data.dir == SPI_MEM_DATA_IN)
 791                 ret = zynqmp_qspi_genfifo_fill_rx(priv);
 792         else if (op->data.dir == SPI_MEM_DATA_OUT)
 793                 ret = zynqmp_qspi_genfifo_fill_tx(priv);
 794
 795         zynqmp_qspi_chipselect(priv, 0);
 796
 797         return ret;
 798 }
 799
 800 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
 801         .exec_op = zynqmp_qspi_exec_op,
 802 };
 803
 804 static const struct dm_spi_ops zynqmp_qspi_ops = {
 805         .claim_bus      = zynqmp_qspi_claim_bus,
 806         .release_bus    = zynqmp_qspi_release_bus,
 807         .set_speed      = zynqmp_qspi_set_speed,
 808         .set_mode       = zynqmp_qspi_set_mode,
 809         .mem_ops        = &zynqmp_qspi_mem_ops,
 810 };
 811
 812 static const struct udevice_id zynqmp_qspi_ids[] = {
 813         { .compatible = "xlnx,zynqmp-qspi-1.0" },
 814         { .compatible = "xlnx,versal-qspi-1.0" },
 815         { }
 816 };
 817
 818 U_BOOT_DRIVER(zynqmp_qspi) = {
 819         .name   = "zynqmp_qspi",
 820         .id     = UCLASS_SPI,
 821         .of_match = zynqmp_qspi_ids,
 822         .ops    = &zynqmp_qspi_ops,
 823         .of_to_plat = zynqmp_qspi_of_to_plat,
 824         .plat_auto      = sizeof(struct zynqmp_qspi_plat),
 825         .priv_auto      = sizeof(struct zynqmp_qspi_priv),
 826         .probe  = zynqmp_qspi_probe,
 827 };