1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2018 Xilinx
5 * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
11 #include <asm/arch/sys_proto.h>
12 #include <asm/cache.h>
20 #include <ubi_uboot.h>
22 #include <dm/device_compat.h>
23 #include <linux/bitops.h>
24 #include <linux/err.h>
25 #include <linux/sizes.h>
26 #include <zynqmp_firmware.h>
28 #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
29 #define GQSPI_CONFIG_MODE_EN_MASK (3 << 30)
30 #define GQSPI_CONFIG_DMA_MODE (2 << 30)
31 #define GQSPI_CONFIG_CPHA_MASK BIT(2)
32 #define GQSPI_CONFIG_CPOL_MASK BIT(1)
35 * QSPI Interrupt Registers bit Masks
37 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
40 #define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
41 #define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
42 #define GQSPI_IXR_TXFIFOEMPTY_MASK 0x00000100 /* QSPI TX FIFO is Empty */
43 #define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
44 #define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
45 #define GQSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */
46 #define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \
47 GQSPI_IXR_RXNEMTY_MASK)
50 * QSPI Enable Register bit Masks
52 * This register is used to enable or disable the QSPI controller
54 #define GQSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */
56 #define GQSPI_GFIFO_LOW_BUS BIT(14)
57 #define GQSPI_GFIFO_CS_LOWER BIT(12)
58 #define GQSPI_GFIFO_UP_BUS BIT(15)
59 #define GQSPI_GFIFO_CS_UPPER BIT(13)
60 #define GQSPI_SPI_MODE_QSPI (3 << 10)
61 #define GQSPI_SPI_MODE_SPI BIT(10)
62 #define GQSPI_SPI_MODE_DUAL_SPI (2 << 10)
63 #define GQSPI_IMD_DATA_CS_ASSERT 5
64 #define GQSPI_IMD_DATA_CS_DEASSERT 5
65 #define GQSPI_GFIFO_TX BIT(16)
66 #define GQSPI_GFIFO_RX BIT(17)
67 #define GQSPI_GFIFO_STRIPE_MASK BIT(18)
68 #define GQSPI_GFIFO_IMD_MASK 0xFF
69 #define GQSPI_GFIFO_EXP_MASK BIT(9)
70 #define GQSPI_GFIFO_DATA_XFR_MASK BIT(8)
71 #define GQSPI_STRT_GEN_FIFO BIT(28)
72 #define GQSPI_GEN_FIFO_STRT_MOD BIT(29)
73 #define GQSPI_GFIFO_WP_HOLD BIT(19)
74 #define GQSPI_BAUD_DIV_MASK (7 << 3)
75 #define GQSPI_DFLT_BAUD_RATE_DIV BIT(3)
76 #define GQSPI_GFIFO_ALL_INT_MASK 0xFBE
77 #define GQSPI_DMA_DST_I_STS_DONE BIT(1)
78 #define GQSPI_DMA_DST_I_STS_MASK 0xFE
81 #define GQSPI_GFIFO_SELECT BIT(0)
82 #define GQSPI_FIFO_THRESHOLD 1
83 #define GQSPI_GENFIFO_THRESHOLD 31
85 #define SPI_XFER_ON_BOTH 0
86 #define SPI_XFER_ON_LOWER 1
87 #define SPI_XFER_ON_UPPER 2
89 #define GQSPI_DMA_ALIGN 0x4
90 #define GQSPI_MAX_BAUD_RATE_VAL 7
91 #define GQSPI_DFLT_BAUD_RATE_VAL 2
93 #define GQSPI_TIMEOUT 100000000
95 #define GQSPI_BAUD_DIV_SHIFT 2
96 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5
97 #define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2
98 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3
99 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3
100 #define GQSPI_USE_DATA_DLY 0x1
101 #define GQSPI_USE_DATA_DLY_SHIFT 31
102 #define GQSPI_DATA_DLY_ADJ_VALUE 0x2
103 #define GQSPI_DATA_DLY_ADJ_SHIFT 28
104 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
105 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
106 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
107 #define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \
108 0xFF180390 : 0xF103003C
109 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020
110 #define GQSPI_FREQ_37_5MHZ 37500000
111 #define GQSPI_FREQ_40MHZ 40000000
112 #define GQSPI_FREQ_100MHZ 100000000
113 #define GQSPI_FREQ_150MHZ 150000000
114 #define IOU_TAPDLY_BYPASS_MASK 0x7
116 #define GQSPI_REG_OFFSET 0x100
117 #define GQSPI_DMA_REG_OFFSET 0x800
119 /* QSPI register offsets */
120 struct zynqmp_qspi_regs {
121 u32 confr; /* 0x00 */
124 u32 idisr; /* 0x0C */
125 u32 imaskr; /* 0x10 */
128 u32 txd0r; /* 0x1C */
131 u32 txftr; /* 0x28 */
132 u32 rxftr; /* 0x2C */
133 u32 gpior; /* 0x30 */
134 u32 reserved0; /* 0x34 */
135 u32 lpbkdly; /* 0x38 */
136 u32 reserved1; /* 0x3C */
137 u32 genfifo; /* 0x40 */
138 u32 gqspisel; /* 0x44 */
139 u32 reserved2; /* 0x48 */
140 u32 gqfifoctrl; /* 0x4C */
141 u32 gqfthr; /* 0x50 */
142 u32 gqpollcfg; /* 0x54 */
143 u32 gqpollto; /* 0x58 */
144 u32 gqxfersts; /* 0x5C */
145 u32 gqfifosnap; /* 0x60 */
146 u32 gqrxcpy; /* 0x64 */
147 u32 reserved3[36]; /* 0x68 */
148 u32 gqspidlyadj; /* 0xF8 */
151 struct zynqmp_qspi_dma_regs {
152 u32 dmadst; /* 0x00 */
153 u32 dmasize; /* 0x04 */
154 u32 dmasts; /* 0x08 */
155 u32 dmactrl; /* 0x0C */
156 u32 reserved0; /* 0x10 */
157 u32 dmaisr; /* 0x14 */
158 u32 dmaier; /* 0x18 */
159 u32 dmaidr; /* 0x1C */
160 u32 dmaimr; /* 0x20 */
161 u32 dmactrl2; /* 0x24 */
162 u32 dmadstmsb; /* 0x28 */
165 struct zynqmp_qspi_plat {
166 struct zynqmp_qspi_regs *regs;
167 struct zynqmp_qspi_dma_regs *dma_regs;
170 unsigned int io_mode;
173 struct zynqmp_qspi_priv {
174 struct zynqmp_qspi_regs *regs;
175 struct zynqmp_qspi_dma_regs *dma_regs;
179 unsigned int io_mode;
180 int bytes_to_transfer;
181 int bytes_to_receive;
182 const struct spi_mem_op *op;
185 static int zynqmp_qspi_of_to_plat(struct udevice *bus)
187 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
189 debug("%s\n", __func__);
191 plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
193 plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
194 (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
196 plat->io_mode = dev_read_bool(bus, "has-io-mode");
201 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
204 struct zynqmp_qspi_regs *regs = priv->regs;
206 writel(GQSPI_GFIFO_SELECT, ®s->gqspisel);
207 writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
208 writel(GQSPI_FIFO_THRESHOLD, ®s->txftr);
209 writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr);
210 writel(GQSPI_GENFIFO_THRESHOLD, ®s->gqfthr);
211 writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr);
212 writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
214 config_reg = readl(®s->confr);
215 config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
216 GQSPI_CONFIG_MODE_EN_MASK);
217 config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV;
218 config_reg |= GQSPI_GFIFO_STRT_MODE_MASK;
220 config_reg |= GQSPI_CONFIG_DMA_MODE;
222 writel(config_reg, ®s->confr);
224 writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
227 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
229 u32 gqspi_fifo_reg = 0;
231 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
232 GQSPI_GFIFO_CS_LOWER;
234 return gqspi_fifo_reg;
237 static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
241 return GQSPI_SPI_MODE_SPI;
243 return GQSPI_SPI_MODE_DUAL_SPI;
245 return GQSPI_SPI_MODE_QSPI;
247 debug("Unsupported bus width %u\n", buswidth);
248 return GQSPI_SPI_MODE_SPI;
252 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
255 struct zynqmp_qspi_regs *regs = priv->regs;
259 writel(gqspi_fifo_reg, ®s->genfifo);
261 config_reg = readl(®s->confr);
262 /* Manual start if needed */
263 config_reg |= GQSPI_STRT_GEN_FIFO;
264 writel(config_reg, ®s->confr);
266 /* Enable interrupts */
267 ier = readl(®s->ier);
268 ier |= GQSPI_IXR_GFEMTY_MASK;
269 writel(ier, ®s->ier);
271 /* Wait until the gen fifo is empty to write the new command */
272 ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
275 printf("%s Timeout\n", __func__);
279 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
281 u32 gqspi_fifo_reg = 0;
284 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
285 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
286 GQSPI_IMD_DATA_CS_ASSERT;
288 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
289 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
292 debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
294 zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
297 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
299 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
300 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
301 struct zynqmp_qspi_regs *regs = priv->regs;
302 u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
305 clk_rate = plat->frequency;
306 reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
308 debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
309 __func__, reqhz, clk_rate, baudrateval);
311 if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) {
312 if (reqhz <= GQSPI_FREQ_40MHZ) {
313 tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
314 TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
315 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
316 tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
317 TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
318 lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
319 datadlyadj = (GQSPI_USE_DATA_DLY <<
320 GQSPI_USE_DATA_DLY_SHIFT) |
321 (GQSPI_DATA_DLY_ADJ_VALUE <<
322 GQSPI_DATA_DLY_ADJ_SHIFT);
323 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
324 lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
325 GQSPI_LPBK_DLY_ADJ_DLY_0;
327 zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
328 IOU_TAPDLY_BYPASS_MASK, tapdlybypass);
330 if (reqhz <= GQSPI_FREQ_37_5MHZ) {
331 tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
332 TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
333 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
334 tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
335 TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
336 lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
337 datadlyadj = GQSPI_USE_DATA_DLY <<
338 GQSPI_USE_DATA_DLY_SHIFT;
339 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
340 lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
341 (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
342 GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT);
344 writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST);
346 writel(lpbkdlyadj, ®s->lpbkdly);
347 writel(datadlyadj, ®s->gqspidlyadj);
350 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
352 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
353 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
354 struct zynqmp_qspi_regs *regs = priv->regs;
356 u8 baud_rate_val = 0;
358 debug("%s\n", __func__);
359 if (speed > plat->frequency)
360 speed = plat->frequency;
362 if (plat->speed_hz != speed) {
363 /* Set the clock frequency */
364 /* If speed == 0, default to lowest speed */
365 while ((baud_rate_val < 8) &&
367 (2 << baud_rate_val)) > speed))
370 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
371 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
373 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
375 confr = readl(®s->confr);
376 confr &= ~GQSPI_BAUD_DIV_MASK;
377 confr |= (baud_rate_val << 3);
378 writel(confr, ®s->confr);
379 zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
381 debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
387 static int zynqmp_qspi_probe(struct udevice *bus)
389 struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
390 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
395 debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
397 priv->regs = plat->regs;
398 priv->dma_regs = plat->dma_regs;
399 priv->io_mode = plat->io_mode;
401 ret = clk_get_by_index(bus, 0, &clk);
403 dev_err(bus, "failed to get clock\n");
407 clock = clk_get_rate(&clk);
408 if (IS_ERR_VALUE(clock)) {
409 dev_err(bus, "failed to get rate\n");
412 debug("%s: CLK %ld\n", __func__, clock);
414 ret = clk_enable(&clk);
416 dev_err(bus, "failed to enable clock\n");
419 plat->frequency = clock;
420 plat->speed_hz = plat->frequency / 2;
422 /* init the zynq spi hw */
423 zynqmp_qspi_init_hw(priv);
428 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
430 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
431 struct zynqmp_qspi_regs *regs = priv->regs;
434 debug("%s\n", __func__);
435 /* Set the SPI Clock phase and polarities */
436 confr = readl(®s->confr);
437 confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
440 confr |= GQSPI_CONFIG_CPHA_MASK;
442 confr |= GQSPI_CONFIG_CPOL_MASK;
444 writel(confr, ®s->confr);
449 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
453 struct zynqmp_qspi_regs *regs = priv->regs;
454 u32 *buf = (u32 *)priv->tx_buf;
457 debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
461 ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1,
464 printf("%s: Timeout\n", __func__);
469 writel(*buf, ®s->txd0r);
477 data |= GENMASK(31, 8);
480 data = *((u16 *)buf);
482 data |= GENMASK(31, 16);
487 data |= GENMASK(31, 24);
490 writel(data, ®s->txd0r);
495 ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
498 printf("%s: Timeout\n", __func__);
506 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
508 const struct spi_mem_op *op = priv->op;
510 u8 i, dummy_cycles, addr;
513 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
514 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
515 gen_fifo_cmd |= GQSPI_GFIFO_TX;
516 gen_fifo_cmd |= op->cmd.opcode;
517 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
520 for (i = 0; i < op->addr.nbytes; i++) {
521 addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
523 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
524 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
525 gen_fifo_cmd |= GQSPI_GFIFO_TX;
526 gen_fifo_cmd |= addr;
528 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
530 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
534 if (op->dummy.nbytes) {
535 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
537 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
538 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
539 gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
540 gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
541 gen_fifo_cmd |= dummy_cycles;
542 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
546 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
553 if (priv->len > 255) {
554 if (priv->len & (1 << expval)) {
555 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
556 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
557 *gen_fifo_cmd |= expval;
558 priv->len -= (1 << expval);
563 *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
564 GQSPI_GFIFO_EXP_MASK);
565 *gen_fifo_cmd |= (u8)priv->len;
573 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
579 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
580 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
581 gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
584 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
585 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
587 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
589 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
590 ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
592 ret = zynqmp_qspi_fill_tx_fifo(priv, len);
600 static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
601 u32 gen_fifo_cmd, u32 *buf)
604 u32 actuallen = priv->len;
605 u32 config_reg, ier, isr;
606 u32 timeout = GQSPI_TIMEOUT;
607 struct zynqmp_qspi_regs *regs = priv->regs;
612 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
613 /* If exponent bit is set, reset immediate to be 2^len */
614 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
615 priv->bytes_to_receive = (1 << len);
617 priv->bytes_to_receive = len;
618 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
619 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
621 config_reg = readl(®s->confr);
622 config_reg |= GQSPI_STRT_GEN_FIFO;
623 writel(config_reg, ®s->confr);
624 /* Enable RX interrupts for IO mode */
625 ier = readl(®s->ier);
626 ier |= GQSPI_IXR_ALL_MASK;
627 writel(ier, ®s->ier);
628 while (priv->bytes_to_receive && timeout) {
629 isr = readl(®s->isr);
630 if (isr & GQSPI_IXR_RXNEMTY_MASK) {
631 if (priv->bytes_to_receive >= 4) {
632 *traverse = readl(®s->drxr);
634 priv->bytes_to_receive -= 4;
636 last_bits = readl(®s->drxr);
637 memcpy(traverse, &last_bits,
638 priv->bytes_to_receive);
639 priv->bytes_to_receive = 0;
641 timeout = GQSPI_TIMEOUT;
648 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
649 (unsigned long)buf, (unsigned long)priv->rx_buf,
652 printf("IO timeout: %d\n", readl(®s->isr));
660 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
661 u32 gen_fifo_cmd, u32 *buf)
665 u32 actuallen = priv->len;
666 u32 totallen = priv->len;
668 struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
671 if (totallen >= SZ_512M)
674 priv->len = totallen;
676 totallen -= priv->len; /* Save remaining bytes length to read */
677 actuallen = priv->len; /* Actual number of bytes reading */
679 writel((unsigned long)buf, &dma_regs->dmadst);
680 writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
681 writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
682 addr = (unsigned long)buf;
683 size = roundup(priv->len, GQSPI_DMA_ALIGN);
684 flush_dcache_range(addr, addr + size);
687 zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
688 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
690 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
693 ret = wait_for_bit_le32(&dma_regs->dmaisr,
694 GQSPI_DMA_DST_I_STS_DONE, 1,
697 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
701 writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
703 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
704 (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
707 if (buf != priv->rx_buf)
708 memcpy(priv->rx_buf, buf, actuallen);
710 buf = (u32 *)((u8 *)buf + actuallen);
711 priv->rx_buf = (u8 *)priv->rx_buf + actuallen;
717 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
721 u32 actuallen = priv->len;
723 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
724 gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
725 gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;
728 * Check if receive buffer is aligned to 4 byte and length
729 * is multiples of four byte as we are using dma to receive.
731 if ((!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
732 !(actuallen % GQSPI_DMA_ALIGN)) || priv->io_mode) {
733 buf = (u32 *)priv->rx_buf;
735 return zynqmp_qspi_start_io(priv, gen_fifo_cmd, buf);
737 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
740 ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, GQSPI_DMA_ALIGN));
742 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
745 static int zynqmp_qspi_claim_bus(struct udevice *dev)
747 struct udevice *bus = dev->parent;
748 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
749 struct zynqmp_qspi_regs *regs = priv->regs;
751 writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
756 static int zynqmp_qspi_release_bus(struct udevice *dev)
758 struct udevice *bus = dev->parent;
759 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
760 struct zynqmp_qspi_regs *regs = priv->regs;
762 writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
767 static int zynqmp_qspi_exec_op(struct spi_slave *slave,
768 const struct spi_mem_op *op)
770 struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
774 priv->tx_buf = op->data.buf.out;
775 priv->rx_buf = op->data.buf.in;
776 priv->len = op->data.nbytes;
778 zynqmp_qspi_chipselect(priv, 1);
780 /* Send opcode, addr, dummy */
781 zynqmp_qspi_genfifo_cmd(priv);
783 /* Request the transfer */
784 if (op->data.dir == SPI_MEM_DATA_IN)
785 ret = zynqmp_qspi_genfifo_fill_rx(priv);
786 else if (op->data.dir == SPI_MEM_DATA_OUT)
787 ret = zynqmp_qspi_genfifo_fill_tx(priv);
789 zynqmp_qspi_chipselect(priv, 0);
794 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
795 .exec_op = zynqmp_qspi_exec_op,
798 static const struct dm_spi_ops zynqmp_qspi_ops = {
799 .claim_bus = zynqmp_qspi_claim_bus,
800 .release_bus = zynqmp_qspi_release_bus,
801 .set_speed = zynqmp_qspi_set_speed,
802 .set_mode = zynqmp_qspi_set_mode,
803 .mem_ops = &zynqmp_qspi_mem_ops,
806 static const struct udevice_id zynqmp_qspi_ids[] = {
807 { .compatible = "xlnx,zynqmp-qspi-1.0" },
808 { .compatible = "xlnx,versal-qspi-1.0" },
812 U_BOOT_DRIVER(zynqmp_qspi) = {
813 .name = "zynqmp_qspi",
815 .of_match = zynqmp_qspi_ids,
816 .ops = &zynqmp_qspi_ops,
817 .of_to_plat = zynqmp_qspi_of_to_plat,
818 .plat_auto = sizeof(struct zynqmp_qspi_plat),
819 .priv_auto = sizeof(struct zynqmp_qspi_priv),
820 .probe = zynqmp_qspi_probe,