1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Xilinx, Inc.
4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
12 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
22 #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
23 #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
24 #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
25 #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
26 #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
27 #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
28 #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
29 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
30 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
31 #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
32 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
33 #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
34 #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
35 #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
36 #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
38 /* zynq qspi Transmit Data Register */
39 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
40 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
41 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
42 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
44 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
45 #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
47 #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
48 #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
49 #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
51 #define ZYNQ_QSPI_FIFO_DEPTH 63
52 #define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
54 /* zynq qspi register set */
55 struct zynq_qspi_regs {
74 u32 lqspicfg; /* 0xA0 */
75 u32 lqspists; /* 0xA4 */
78 /* zynq qspi platform data */
79 struct zynq_qspi_platdata {
80 struct zynq_qspi_regs *regs;
81 u32 frequency; /* input frequency */
86 struct zynq_qspi_priv {
87 struct zynq_qspi_regs *regs;
91 u32 freq; /* required frequency */
95 int bytes_to_transfer;
101 static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
103 struct zynq_qspi_platdata *plat = bus->platdata;
104 const void *blob = gd->fdt_blob;
105 int node = dev_of_offset(bus);
107 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
114 * zynq_qspi_init_hw - Initialize the hardware
115 * @priv: Pointer to the zynq_qspi_priv structure
117 * The default settings of the QSPI controller's configurable parameters on
120 * - Baud rate divisor is set to 2
121 * - Threshold value for TX FIFO not full interrupt is set to 1
122 * - Flash memory interface mode enabled
123 * - Size of the word to be transferred as 8 bit
124 * This function performs the following actions
125 * - Disable and clear all the interrupts
126 * - Enable manual slave select
127 * - Enable auto start
128 * - Deselect all the chip select lines
129 * - Set the size of the word to be transferred as 32 bit
130 * - Set the little endian mode of TX FIFO and
131 * - Enable the QSPI controller
133 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
135 struct zynq_qspi_regs *regs = priv->regs;
139 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
141 /* Disable Interrupts */
142 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
144 /* Clear the TX and RX threshold reg */
145 writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
146 writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
148 /* Clear the RX FIFO */
149 while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
152 /* Clear Interrupts */
153 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
155 /* Manual slave select and Auto start */
156 confr = readl(®s->cr);
157 confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
158 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
159 ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
160 ZYNQ_QSPI_CR_MSTREN_MASK;
161 writel(confr, ®s->cr);
163 /* Disable the LQSPI feature */
164 confr = readl(®s->lqspicfg);
165 confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
166 writel(confr, ®s->lqspicfg);
169 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
172 static int zynq_qspi_probe(struct udevice *bus)
174 struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
175 struct zynq_qspi_priv *priv = dev_get_priv(bus);
180 priv->regs = plat->regs;
181 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
183 ret = clk_get_by_name(bus, "ref_clk", &clk);
185 dev_err(bus, "failed to get clock\n");
189 clock = clk_get_rate(&clk);
190 if (IS_ERR_VALUE(clock)) {
191 dev_err(bus, "failed to get rate\n");
195 ret = clk_enable(&clk);
196 if (ret && ret != -ENOSYS) {
197 dev_err(bus, "failed to enable clock\n");
201 /* init the zynq spi hw */
202 zynq_qspi_init_hw(priv);
204 plat->frequency = clock;
205 plat->speed_hz = plat->frequency / 2;
207 debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
213 * zynq_qspi_read_data - Copy data to RX buffer
214 * @priv: Pointer to the zynq_qspi_priv structure
215 * @data: The 32 bit variable where data is stored
216 * @size: Number of bytes to be copied from data to RX buffer
218 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
222 debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
223 data, (unsigned)(priv->rx_buf), size);
228 *((u8 *)priv->rx_buf) = data;
232 *((u16 *)priv->rx_buf) = data;
236 *((u16 *)priv->rx_buf) = data;
238 byte3 = (u8)(data >> 16);
239 *((u8 *)priv->rx_buf) = byte3;
243 /* Can not assume word aligned buffer */
244 memcpy(priv->rx_buf, &data, size);
248 /* This will never execute */
252 priv->bytes_to_receive -= size;
253 if (priv->bytes_to_receive < 0)
254 priv->bytes_to_receive = 0;
258 * zynq_qspi_write_data - Copy data from TX buffer
259 * @priv: Pointer to the zynq_qspi_priv structure
260 * @data: Pointer to the 32 bit variable where data is to be copied
261 * @size: Number of bytes to be copied from TX buffer to data
263 static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
269 *data = *((u8 *)priv->tx_buf);
274 *data = *((u16 *)priv->tx_buf);
279 *data = *((u16 *)priv->tx_buf);
281 *data |= (*((u8 *)priv->tx_buf) << 16);
286 /* Can not assume word aligned buffer */
287 memcpy(data, priv->tx_buf, size);
291 /* This will never execute */
298 debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
299 *data, (u32)priv->tx_buf, size);
301 priv->bytes_to_transfer -= size;
302 if (priv->bytes_to_transfer < 0)
303 priv->bytes_to_transfer = 0;
307 * zynq_qspi_chipselect - Select or deselect the chip select line
308 * @priv: Pointer to the zynq_qspi_priv structure
309 * @is_on: Select(1) or deselect (0) the chip select line
311 static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
314 struct zynq_qspi_regs *regs = priv->regs;
316 confr = readl(®s->cr);
319 /* Select the slave */
320 confr &= ~ZYNQ_QSPI_CR_SS_MASK;
321 confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
322 ZYNQ_QSPI_CR_SS_MASK;
324 /* Deselect the slave */
325 confr |= ZYNQ_QSPI_CR_SS_MASK;
327 writel(confr, ®s->cr);
331 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
332 * @priv: Pointer to the zynq_qspi_priv structure
333 * @size: Number of bytes to be copied to fifo
335 static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
339 unsigned len, offset;
340 struct zynq_qspi_regs *regs = priv->regs;
341 static const unsigned offsets[4] = {
342 ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
343 ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
345 while ((fifocount < size) &&
346 (priv->bytes_to_transfer > 0)) {
347 if (priv->bytes_to_transfer >= 4) {
349 memcpy(&data, priv->tx_buf, 4);
354 writel(data, ®s->txd0r);
355 priv->bytes_to_transfer -= 4;
358 /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
359 if (!(readl(®s->isr)
360 & ZYNQ_QSPI_IXR_TXOW_MASK) &&
363 len = priv->bytes_to_transfer;
364 zynq_qspi_write_data(priv, &data, len);
365 offset = (priv->rx_buf) ? offsets[0] : offsets[len];
366 writel(data, ®s->cr + (offset / 4));
372 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
373 * @priv: Pointer to the zynq_qspi structure
375 * This function handles TX empty and Mode Fault interrupts only.
376 * On TX empty interrupt this function reads the received data from RX FIFO and
377 * fills the TX FIFO if there is any data remaining to be transferred.
378 * On Mode Fault interrupt this function indicates that transfer is completed,
379 * the SPI subsystem will identify the error as the remaining bytes to be
380 * transferred is non-zero.
382 * returns: 0 for poll timeout
383 * 1 transfer operation complete
385 static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
387 struct zynq_qspi_regs *regs = priv->regs;
392 /* Poll until any of the interrupt status bits are set */
393 timeout = get_timer(0);
395 status = readl(®s->isr);
396 } while ((status == 0) &&
397 (get_timer(timeout) < ZYNQ_QSPI_WAIT));
400 printf("zynq_qspi_irq_poll: Timeout!\n");
404 writel(status, ®s->isr);
406 /* Disable all interrupts */
407 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
408 if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
409 (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
411 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
412 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
415 rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
416 rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
417 while ((rxindex < rxcount) &&
418 (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
419 /* Read out the data from the RX FIFO */
421 data = readl(®s->drxr);
423 if (priv->bytes_to_receive >= 4) {
425 memcpy(priv->rx_buf, &data, 4);
428 priv->bytes_to_receive -= 4;
430 zynq_qspi_read_data(priv, data,
431 priv->bytes_to_receive);
436 if (priv->bytes_to_transfer) {
437 /* There is more data to send */
438 zynq_qspi_fill_tx_fifo(priv,
439 ZYNQ_QSPI_RXFIFO_THRESHOLD);
441 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
444 * If transfer and receive is completed then only send
447 if (!priv->bytes_to_receive) {
448 /* return operation complete */
449 writel(ZYNQ_QSPI_IXR_ALL_MASK,
460 * zynq_qspi_start_transfer - Initiates the QSPI transfer
461 * @priv: Pointer to the zynq_qspi_priv structure
463 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
464 * transfer to be completed.
466 * returns: Number of bytes transferred in the last transfer
468 static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
471 struct zynq_qspi_regs *regs = priv->regs;
473 debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
474 (u32)priv, (u32)priv, priv->len);
476 priv->bytes_to_transfer = priv->len;
477 priv->bytes_to_receive = priv->len;
480 zynq_qspi_fill_tx_fifo(priv, priv->len);
482 zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
484 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
486 /* wait for completion */
488 data = zynq_qspi_irq_poll(priv);
491 return (priv->len) - (priv->bytes_to_transfer);
494 static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
496 unsigned cs_change = 1;
500 /* Select the chip if required */
502 zynq_qspi_chipselect(priv, 1);
504 cs_change = priv->cs_change;
506 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
511 /* Request the transfer */
513 status = zynq_qspi_start_transfer(priv);
517 if (status != priv->len) {
520 debug("zynq_qspi_transfer:%d len:%d\n",
527 /* Deselect the chip */
528 zynq_qspi_chipselect(priv, 0);
536 static int zynq_qspi_claim_bus(struct udevice *dev)
538 struct udevice *bus = dev->parent;
539 struct zynq_qspi_priv *priv = dev_get_priv(bus);
540 struct zynq_qspi_regs *regs = priv->regs;
542 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
547 static int zynq_qspi_release_bus(struct udevice *dev)
549 struct udevice *bus = dev->parent;
550 struct zynq_qspi_priv *priv = dev_get_priv(bus);
551 struct zynq_qspi_regs *regs = priv->regs;
553 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
558 static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
559 const void *dout, void *din, unsigned long flags)
561 struct udevice *bus = dev->parent;
562 struct zynq_qspi_priv *priv = dev_get_priv(bus);
563 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
565 priv->cs = slave_plat->cs;
568 priv->len = bitlen / 8;
570 debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
571 bus->seq, slave_plat->cs, bitlen, priv->len, flags);
575 * Assume that the beginning of a transfer with bits to
576 * transmit must contain a device command.
578 if (dout && flags & SPI_XFER_BEGIN)
583 if (flags & SPI_XFER_END)
588 zynq_qspi_transfer(priv);
593 static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
595 struct zynq_qspi_platdata *plat = bus->platdata;
596 struct zynq_qspi_priv *priv = dev_get_priv(bus);
597 struct zynq_qspi_regs *regs = priv->regs;
599 u8 baud_rate_val = 0;
601 if (speed > plat->frequency)
602 speed = plat->frequency;
604 /* Set the clock frequency */
605 confr = readl(®s->cr);
607 /* Set baudrate x8, if the freq is 0 */
609 } else if (plat->speed_hz != speed) {
610 while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
612 (2 << baud_rate_val)) > speed))
615 plat->speed_hz = speed / (2 << baud_rate_val);
617 confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
618 confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
620 writel(confr, ®s->cr);
623 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
628 static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
630 struct zynq_qspi_priv *priv = dev_get_priv(bus);
631 struct zynq_qspi_regs *regs = priv->regs;
634 /* Set the SPI Clock phase and polarities */
635 confr = readl(®s->cr);
636 confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
639 confr |= ZYNQ_QSPI_CR_CPHA_MASK;
641 confr |= ZYNQ_QSPI_CR_CPOL_MASK;
643 writel(confr, ®s->cr);
646 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
651 static const struct dm_spi_ops zynq_qspi_ops = {
652 .claim_bus = zynq_qspi_claim_bus,
653 .release_bus = zynq_qspi_release_bus,
654 .xfer = zynq_qspi_xfer,
655 .set_speed = zynq_qspi_set_speed,
656 .set_mode = zynq_qspi_set_mode,
659 static const struct udevice_id zynq_qspi_ids[] = {
660 { .compatible = "xlnx,zynq-qspi-1.0" },
664 U_BOOT_DRIVER(zynq_qspi) = {
667 .of_match = zynq_qspi_ids,
668 .ops = &zynq_qspi_ops,
669 .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
670 .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
671 .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
672 .probe = zynq_qspi_probe,