1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Xilinx, Inc.
4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
15 #include <linux/bitops.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
20 #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
21 #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
22 #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
23 #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
24 #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
25 #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
26 #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
27 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
28 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
29 #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
30 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
31 #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
32 #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
33 #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
34 #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
36 /* zynq qspi Transmit Data Register */
37 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
38 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
39 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
40 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
42 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
43 #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
45 #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
46 #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
47 #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
49 #define ZYNQ_QSPI_FIFO_DEPTH 63
50 #ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
51 #define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
54 /* zynq qspi register set */
55 struct zynq_qspi_regs {
74 u32 lqspicfg; /* 0xA0 */
75 u32 lqspists; /* 0xA4 */
78 /* zynq qspi platform data */
79 struct zynq_qspi_platdata {
80 struct zynq_qspi_regs *regs;
81 u32 frequency; /* input frequency */
86 struct zynq_qspi_priv {
87 struct zynq_qspi_regs *regs;
91 u32 freq; /* required frequency */
95 int bytes_to_transfer;
101 static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
103 struct zynq_qspi_platdata *plat = bus->platdata;
104 const void *blob = gd->fdt_blob;
105 int node = dev_of_offset(bus);
107 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
110 /* FIXME: Use 166MHz as a suitable default */
111 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
113 plat->speed_hz = plat->frequency / 2;
115 debug("%s: regs=%p max-frequency=%d\n", __func__,
116 plat->regs, plat->frequency);
121 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
123 struct zynq_qspi_regs *regs = priv->regs;
127 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
129 /* Disable Interrupts */
130 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
132 /* Clear the TX and RX threshold reg */
133 writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
134 writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
136 /* Clear the RX FIFO */
137 while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
140 /* Clear Interrupts */
141 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
143 /* Manual slave select and Auto start */
144 confr = readl(®s->cr);
145 confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
146 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
147 ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
148 ZYNQ_QSPI_CR_MSTREN_MASK;
149 writel(confr, ®s->cr);
151 /* Disable the LQSPI feature */
152 confr = readl(®s->lqspicfg);
153 confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
154 writel(confr, ®s->lqspicfg);
157 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
160 static int zynq_qspi_probe(struct udevice *bus)
162 struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
163 struct zynq_qspi_priv *priv = dev_get_priv(bus);
165 priv->regs = plat->regs;
166 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
168 /* init the zynq spi hw */
169 zynq_qspi_init_hw(priv);
175 * zynq_qspi_read_data - Copy data to RX buffer
176 * @zqspi: Pointer to the zynq_qspi structure
177 * @data: The 32 bit variable where data is stored
178 * @size: Number of bytes to be copied from data to RX buffer
180 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
184 debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
185 data, (unsigned)(priv->rx_buf), size);
190 *((u8 *)priv->rx_buf) = data;
194 *((u16 *)priv->rx_buf) = data;
198 *((u16 *)priv->rx_buf) = data;
200 byte3 = (u8)(data >> 16);
201 *((u8 *)priv->rx_buf) = byte3;
205 /* Can not assume word aligned buffer */
206 memcpy(priv->rx_buf, &data, size);
210 /* This will never execute */
214 priv->bytes_to_receive -= size;
215 if (priv->bytes_to_receive < 0)
216 priv->bytes_to_receive = 0;
220 * zynq_qspi_write_data - Copy data from TX buffer
221 * @zqspi: Pointer to the zynq_qspi structure
222 * @data: Pointer to the 32 bit variable where data is to be copied
223 * @size: Number of bytes to be copied from TX buffer to data
225 static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
231 *data = *((u8 *)priv->tx_buf);
236 *data = *((u16 *)priv->tx_buf);
241 *data = *((u16 *)priv->tx_buf);
243 *data |= (*((u8 *)priv->tx_buf) << 16);
248 /* Can not assume word aligned buffer */
249 memcpy(data, priv->tx_buf, size);
253 /* This will never execute */
260 debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
261 *data, (u32)priv->tx_buf, size);
263 priv->bytes_to_transfer -= size;
264 if (priv->bytes_to_transfer < 0)
265 priv->bytes_to_transfer = 0;
268 static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
271 struct zynq_qspi_regs *regs = priv->regs;
273 confr = readl(®s->cr);
276 /* Select the slave */
277 confr &= ~ZYNQ_QSPI_CR_SS_MASK;
278 confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
279 ZYNQ_QSPI_CR_SS_MASK;
281 /* Deselect the slave */
282 confr |= ZYNQ_QSPI_CR_SS_MASK;
284 writel(confr, ®s->cr);
288 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
289 * @zqspi: Pointer to the zynq_qspi structure
291 static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
295 unsigned len, offset;
296 struct zynq_qspi_regs *regs = priv->regs;
297 static const unsigned offsets[4] = {
298 ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
299 ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
301 while ((fifocount < size) &&
302 (priv->bytes_to_transfer > 0)) {
303 if (priv->bytes_to_transfer >= 4) {
305 memcpy(&data, priv->tx_buf, 4);
310 writel(data, ®s->txd0r);
311 priv->bytes_to_transfer -= 4;
314 /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
315 if (!(readl(®s->isr)
316 & ZYNQ_QSPI_IXR_TXOW_MASK) &&
319 len = priv->bytes_to_transfer;
320 zynq_qspi_write_data(priv, &data, len);
321 offset = (priv->rx_buf) ? offsets[0] : offsets[len];
322 writel(data, ®s->cr + (offset / 4));
328 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
329 * @zqspi: Pointer to the zynq_qspi structure
331 * This function handles TX empty and Mode Fault interrupts only.
332 * On TX empty interrupt this function reads the received data from RX FIFO and
333 * fills the TX FIFO if there is any data remaining to be transferred.
334 * On Mode Fault interrupt this function indicates that transfer is completed,
335 * the SPI subsystem will identify the error as the remaining bytes to be
336 * transferred is non-zero.
338 * returns: 0 for poll timeout
339 * 1 transfer operation complete
341 static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
343 struct zynq_qspi_regs *regs = priv->regs;
348 /* Poll until any of the interrupt status bits are set */
349 timeout = get_timer(0);
351 status = readl(®s->isr);
352 } while ((status == 0) &&
353 (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
356 printf("zynq_qspi_irq_poll: Timeout!\n");
360 writel(status, ®s->isr);
362 /* Disable all interrupts */
363 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
364 if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
365 (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
367 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
368 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
371 rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
372 rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
373 while ((rxindex < rxcount) &&
374 (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
375 /* Read out the data from the RX FIFO */
377 data = readl(®s->drxr);
379 if (priv->bytes_to_receive >= 4) {
381 memcpy(priv->rx_buf, &data, 4);
384 priv->bytes_to_receive -= 4;
386 zynq_qspi_read_data(priv, data,
387 priv->bytes_to_receive);
392 if (priv->bytes_to_transfer) {
393 /* There is more data to send */
394 zynq_qspi_fill_tx_fifo(priv,
395 ZYNQ_QSPI_RXFIFO_THRESHOLD);
397 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
400 * If transfer and receive is completed then only send
403 if (!priv->bytes_to_receive) {
404 /* return operation complete */
405 writel(ZYNQ_QSPI_IXR_ALL_MASK,
416 * zynq_qspi_start_transfer - Initiates the QSPI transfer
417 * @qspi: Pointer to the spi_device structure
418 * @transfer: Pointer to the spi_transfer structure which provide information
419 * about next transfer parameters
421 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
422 * transfer to be completed.
424 * returns: Number of bytes transferred in the last transfer
426 static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
429 struct zynq_qspi_regs *regs = priv->regs;
431 debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
432 (u32)priv, (u32)priv, priv->len);
434 priv->bytes_to_transfer = priv->len;
435 priv->bytes_to_receive = priv->len;
438 zynq_qspi_fill_tx_fifo(priv, priv->len);
440 zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
442 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
444 /* wait for completion */
446 data = zynq_qspi_irq_poll(priv);
449 return (priv->len) - (priv->bytes_to_transfer);
452 static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
454 unsigned cs_change = 1;
458 /* Select the chip if required */
460 zynq_qspi_chipselect(priv, 1);
462 cs_change = priv->cs_change;
464 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
469 /* Request the transfer */
471 status = zynq_qspi_start_transfer(priv);
475 if (status != priv->len) {
478 debug("zynq_qspi_transfer:%d len:%d\n",
485 /* Deselect the chip */
486 zynq_qspi_chipselect(priv, 0);
494 static int zynq_qspi_claim_bus(struct udevice *dev)
496 struct udevice *bus = dev->parent;
497 struct zynq_qspi_priv *priv = dev_get_priv(bus);
498 struct zynq_qspi_regs *regs = priv->regs;
500 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
505 static int zynq_qspi_release_bus(struct udevice *dev)
507 struct udevice *bus = dev->parent;
508 struct zynq_qspi_priv *priv = dev_get_priv(bus);
509 struct zynq_qspi_regs *regs = priv->regs;
511 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
516 static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
517 const void *dout, void *din, unsigned long flags)
519 struct udevice *bus = dev->parent;
520 struct zynq_qspi_priv *priv = dev_get_priv(bus);
521 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
523 priv->cs = slave_plat->cs;
526 priv->len = bitlen / 8;
528 debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
529 bus->seq, slave_plat->cs, bitlen, priv->len, flags);
533 * Assume that the beginning of a transfer with bits to
534 * transmit must contain a device command.
536 if (dout && flags & SPI_XFER_BEGIN)
541 if (flags & SPI_XFER_END)
546 zynq_qspi_transfer(priv);
551 static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
553 struct zynq_qspi_platdata *plat = bus->platdata;
554 struct zynq_qspi_priv *priv = dev_get_priv(bus);
555 struct zynq_qspi_regs *regs = priv->regs;
557 u8 baud_rate_val = 0;
559 if (speed > plat->frequency)
560 speed = plat->frequency;
562 /* Set the clock frequency */
563 confr = readl(®s->cr);
565 /* Set baudrate x8, if the freq is 0 */
567 } else if (plat->speed_hz != speed) {
568 while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
570 (2 << baud_rate_val)) > speed))
573 plat->speed_hz = speed / (2 << baud_rate_val);
575 confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
576 confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
578 writel(confr, ®s->cr);
581 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
586 static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
588 struct zynq_qspi_priv *priv = dev_get_priv(bus);
589 struct zynq_qspi_regs *regs = priv->regs;
592 /* Set the SPI Clock phase and polarities */
593 confr = readl(®s->cr);
594 confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
597 confr |= ZYNQ_QSPI_CR_CPHA_MASK;
599 confr |= ZYNQ_QSPI_CR_CPOL_MASK;
601 writel(confr, ®s->cr);
604 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
609 static const struct dm_spi_ops zynq_qspi_ops = {
610 .claim_bus = zynq_qspi_claim_bus,
611 .release_bus = zynq_qspi_release_bus,
612 .xfer = zynq_qspi_xfer,
613 .set_speed = zynq_qspi_set_speed,
614 .set_mode = zynq_qspi_set_mode,
617 static const struct udevice_id zynq_qspi_ids[] = {
618 { .compatible = "xlnx,zynq-qspi-1.0" },
622 U_BOOT_DRIVER(zynq_qspi) = {
625 .of_match = zynq_qspi_ids,
626 .ops = &zynq_qspi_ops,
627 .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
628 .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
629 .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
630 .probe = zynq_qspi_probe,