1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Xilinx, Inc.
4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
12 #include <dm/device_compat.h>
16 #include <asm/global_data.h>
18 #include <linux/bitops.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
24 #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
25 #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
26 #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
27 #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
28 #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
29 #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
30 #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
31 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
32 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
33 #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
34 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
35 #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
36 #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
37 #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
38 #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
40 /* zynq qspi Transmit Data Register */
41 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
42 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
43 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
44 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
46 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
47 #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
49 #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
50 #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
51 #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
53 #define ZYNQ_QSPI_MAX_BAUD_RATE 0x7
54 #define ZYNQ_QSPI_DEFAULT_BAUD_RATE 0x2
56 #define ZYNQ_QSPI_FIFO_DEPTH 63
57 #define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
59 /* zynq qspi register set */
60 struct zynq_qspi_regs {
79 u32 lqspicfg; /* 0xA0 */
80 u32 lqspists; /* 0xA4 */
83 /* zynq qspi platform data */
84 struct zynq_qspi_plat {
85 struct zynq_qspi_regs *regs;
86 u32 frequency; /* input frequency */
91 struct zynq_qspi_priv {
92 struct zynq_qspi_regs *regs;
96 u32 freq; /* required frequency */
101 int bytes_to_transfer;
102 int bytes_to_receive;
103 unsigned int is_inst;
104 unsigned cs_change:1;
107 static int zynq_qspi_of_to_plat(struct udevice *bus)
109 struct zynq_qspi_plat *plat = dev_get_plat(bus);
110 const void *blob = gd->fdt_blob;
111 int node = dev_of_offset(bus);
113 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
120 * zynq_qspi_init_hw - Initialize the hardware
121 * @priv: Pointer to the zynq_qspi_priv structure
123 * The default settings of the QSPI controller's configurable parameters on
126 * - Baud rate divisor is set to 2
127 * - Threshold value for TX FIFO not full interrupt is set to 1
128 * - Flash memory interface mode enabled
129 * - Size of the word to be transferred as 8 bit
130 * This function performs the following actions
131 * - Disable and clear all the interrupts
132 * - Enable manual slave select
133 * - Enable auto start
134 * - Deselect all the chip select lines
135 * - Set the size of the word to be transferred as 32 bit
136 * - Set the little endian mode of TX FIFO and
137 * - Enable the QSPI controller
139 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
141 struct zynq_qspi_regs *regs = priv->regs;
145 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
147 /* Disable Interrupts */
148 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
150 /* Clear the TX and RX threshold reg */
151 writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
152 writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
154 /* Clear the RX FIFO */
155 while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
158 /* Clear Interrupts */
159 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
161 /* Manual slave select and Auto start */
162 confr = readl(®s->cr);
163 confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
164 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
165 ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
166 ZYNQ_QSPI_CR_MSTREN_MASK;
167 writel(confr, ®s->cr);
169 /* Disable the LQSPI feature */
170 confr = readl(®s->lqspicfg);
171 confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
172 writel(confr, ®s->lqspicfg);
175 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
178 static int zynq_qspi_child_pre_probe(struct udevice *bus)
180 struct spi_slave *slave = dev_get_parent_priv(bus);
181 struct zynq_qspi_priv *priv = dev_get_priv(bus->parent);
183 priv->max_hz = slave->max_hz;
188 static int zynq_qspi_probe(struct udevice *bus)
190 struct zynq_qspi_plat *plat = dev_get_plat(bus);
191 struct zynq_qspi_priv *priv = dev_get_priv(bus);
196 priv->regs = plat->regs;
197 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
199 ret = clk_get_by_name(bus, "ref_clk", &clk);
201 dev_err(bus, "failed to get clock\n");
205 clock = clk_get_rate(&clk);
206 if (IS_ERR_VALUE(clock)) {
207 dev_err(bus, "failed to get rate\n");
211 ret = clk_enable(&clk);
213 dev_err(bus, "failed to enable clock\n");
217 /* init the zynq spi hw */
218 zynq_qspi_init_hw(priv);
220 plat->frequency = clock;
221 plat->speed_hz = plat->frequency / 2;
223 debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
229 * zynq_qspi_read_data - Copy data to RX buffer
230 * @priv: Pointer to the zynq_qspi_priv structure
231 * @data: The 32 bit variable where data is stored
232 * @size: Number of bytes to be copied from data to RX buffer
234 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
238 debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
239 data, (unsigned)(priv->rx_buf), size);
244 *((u8 *)priv->rx_buf) = data;
248 *((u8 *)priv->rx_buf) = data;
250 *((u8 *)priv->rx_buf) = (u8)(data >> 8);
254 *((u8 *)priv->rx_buf) = data;
256 *((u8 *)priv->rx_buf) = (u8)(data >> 8);
258 byte3 = (u8)(data >> 16);
259 *((u8 *)priv->rx_buf) = byte3;
263 /* Can not assume word aligned buffer */
264 memcpy(priv->rx_buf, &data, size);
268 /* This will never execute */
272 priv->bytes_to_receive -= size;
273 if (priv->bytes_to_receive < 0)
274 priv->bytes_to_receive = 0;
278 * zynq_qspi_write_data - Copy data from TX buffer
279 * @priv: Pointer to the zynq_qspi_priv structure
280 * @data: Pointer to the 32 bit variable where data is to be copied
281 * @size: Number of bytes to be copied from TX buffer to data
283 static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
289 *data = *((u8 *)priv->tx_buf);
294 *data = *((u8 *)priv->tx_buf);
296 *data |= (*((u8 *)priv->tx_buf) << 8);
301 *data = *((u8 *)priv->tx_buf);
303 *data |= (*((u8 *)priv->tx_buf) << 8);
305 *data |= (*((u8 *)priv->tx_buf) << 16);
310 /* Can not assume word aligned buffer */
311 memcpy(data, priv->tx_buf, size);
315 /* This will never execute */
322 debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
323 *data, (u32)priv->tx_buf, size);
325 priv->bytes_to_transfer -= size;
326 if (priv->bytes_to_transfer < 0)
327 priv->bytes_to_transfer = 0;
331 * zynq_qspi_chipselect - Select or deselect the chip select line
332 * @priv: Pointer to the zynq_qspi_priv structure
333 * @is_on: Select(1) or deselect (0) the chip select line
335 static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
338 struct zynq_qspi_regs *regs = priv->regs;
340 confr = readl(®s->cr);
343 /* Select the slave */
344 confr &= ~ZYNQ_QSPI_CR_SS_MASK;
345 confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
346 ZYNQ_QSPI_CR_SS_MASK;
348 /* Deselect the slave */
349 confr |= ZYNQ_QSPI_CR_SS_MASK;
351 writel(confr, ®s->cr);
355 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
356 * @priv: Pointer to the zynq_qspi_priv structure
357 * @size: Number of bytes to be copied to fifo
359 static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
363 unsigned len, offset;
364 struct zynq_qspi_regs *regs = priv->regs;
365 static const unsigned offsets[4] = {
366 ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
367 ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
369 while ((fifocount < size) &&
370 (priv->bytes_to_transfer > 0)) {
371 if (priv->bytes_to_transfer >= 4) {
373 memcpy(&data, priv->tx_buf, 4);
378 writel(data, ®s->txd0r);
379 priv->bytes_to_transfer -= 4;
382 /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
383 if (!(readl(®s->isr)
384 & ZYNQ_QSPI_IXR_TXOW_MASK) &&
387 len = priv->bytes_to_transfer;
388 zynq_qspi_write_data(priv, &data, len);
389 offset = (priv->rx_buf) ? offsets[0] : offsets[len];
390 writel(data, ®s->cr + (offset / 4));
396 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
397 * @priv: Pointer to the zynq_qspi structure
399 * This function handles TX empty and Mode Fault interrupts only.
400 * On TX empty interrupt this function reads the received data from RX FIFO and
401 * fills the TX FIFO if there is any data remaining to be transferred.
402 * On Mode Fault interrupt this function indicates that transfer is completed,
403 * the SPI subsystem will identify the error as the remaining bytes to be
404 * transferred is non-zero.
406 * returns: 0 for poll timeout
407 * 1 transfer operation complete
409 static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
411 struct zynq_qspi_regs *regs = priv->regs;
416 /* Poll until any of the interrupt status bits are set */
417 timeout = get_timer(0);
419 status = readl(®s->isr);
420 } while ((status == 0) &&
421 (get_timer(timeout) < ZYNQ_QSPI_WAIT));
424 printf("zynq_qspi_irq_poll: Timeout!\n");
428 writel(status, ®s->isr);
430 /* Disable all interrupts */
431 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
432 if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
433 (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
435 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
436 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
439 rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
440 rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
441 while ((rxindex < rxcount) &&
442 (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
443 /* Read out the data from the RX FIFO */
445 data = readl(®s->drxr);
447 if (priv->bytes_to_receive >= 4) {
449 memcpy(priv->rx_buf, &data, 4);
452 priv->bytes_to_receive -= 4;
454 zynq_qspi_read_data(priv, data,
455 priv->bytes_to_receive);
460 if (priv->bytes_to_transfer) {
461 /* There is more data to send */
462 zynq_qspi_fill_tx_fifo(priv,
463 ZYNQ_QSPI_RXFIFO_THRESHOLD);
465 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
468 * If transfer and receive is completed then only send
471 if (!priv->bytes_to_receive) {
472 /* return operation complete */
473 writel(ZYNQ_QSPI_IXR_ALL_MASK,
484 * zynq_qspi_start_transfer - Initiates the QSPI transfer
485 * @priv: Pointer to the zynq_qspi_priv structure
487 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
488 * transfer to be completed.
490 * returns: Number of bytes transferred in the last transfer
492 static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
495 struct zynq_qspi_regs *regs = priv->regs;
497 debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
498 (u32)priv, (u32)priv, priv->len);
500 priv->bytes_to_transfer = priv->len;
501 priv->bytes_to_receive = priv->len;
504 zynq_qspi_fill_tx_fifo(priv, priv->len);
506 zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
508 writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
510 /* wait for completion */
512 data = zynq_qspi_irq_poll(priv);
515 return (priv->len) - (priv->bytes_to_transfer);
518 static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
520 unsigned cs_change = 1;
524 /* Select the chip if required */
526 zynq_qspi_chipselect(priv, 1);
528 cs_change = priv->cs_change;
530 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
535 /* Request the transfer */
537 status = zynq_qspi_start_transfer(priv);
541 if (status != priv->len) {
544 debug("zynq_qspi_transfer:%d len:%d\n",
551 /* Deselect the chip */
552 zynq_qspi_chipselect(priv, 0);
560 static int zynq_qspi_claim_bus(struct udevice *dev)
562 struct udevice *bus = dev->parent;
563 struct zynq_qspi_priv *priv = dev_get_priv(bus);
564 struct zynq_qspi_regs *regs = priv->regs;
566 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
571 static int zynq_qspi_release_bus(struct udevice *dev)
573 struct udevice *bus = dev->parent;
574 struct zynq_qspi_priv *priv = dev_get_priv(bus);
575 struct zynq_qspi_regs *regs = priv->regs;
577 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
582 static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
583 const void *dout, void *din, unsigned long flags)
585 struct udevice *bus = dev->parent;
586 struct zynq_qspi_priv *priv = dev_get_priv(bus);
587 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
589 priv->cs = slave_plat->cs;
592 priv->len = bitlen / 8;
594 debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
595 dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
599 * Assume that the beginning of a transfer with bits to
600 * transmit must contain a device command.
602 if (dout && flags & SPI_XFER_BEGIN)
607 if (flags & SPI_XFER_END)
612 zynq_qspi_transfer(priv);
617 static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
619 struct zynq_qspi_plat *plat = dev_get_plat(bus);
620 struct zynq_qspi_priv *priv = dev_get_priv(bus);
621 struct zynq_qspi_regs *regs = priv->regs;
623 u8 baud_rate_val = 0;
625 if (!speed || speed > priv->max_hz)
626 speed = priv->max_hz;
628 /* Set the clock frequency */
629 confr = readl(®s->cr);
630 if (plat->speed_hz != speed) {
631 while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
633 (2 << baud_rate_val)) > speed))
636 if (baud_rate_val > ZYNQ_QSPI_MAX_BAUD_RATE)
637 baud_rate_val = ZYNQ_QSPI_DEFAULT_BAUD_RATE;
639 plat->speed_hz = speed / (2 << baud_rate_val);
641 confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
642 confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
644 writel(confr, ®s->cr);
647 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
652 static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
654 struct zynq_qspi_priv *priv = dev_get_priv(bus);
655 struct zynq_qspi_regs *regs = priv->regs;
658 /* Set the SPI Clock phase and polarities */
659 confr = readl(®s->cr);
660 confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
663 confr |= ZYNQ_QSPI_CR_CPHA_MASK;
665 confr |= ZYNQ_QSPI_CR_CPOL_MASK;
667 writel(confr, ®s->cr);
670 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
675 static int zynq_qspi_exec_op(struct spi_slave *slave,
676 const struct spi_mem_op *op)
678 int op_len, pos = 0, ret, i;
680 unsigned int flag = 0;
681 const u8 *tx_buf = NULL;
684 if (op->data.nbytes) {
685 if (op->data.dir == SPI_MEM_DATA_IN)
686 rx_buf = op->data.buf.in;
688 tx_buf = op->data.buf.out;
691 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
692 if (op->dummy.nbytes) {
693 op_len = op->cmd.nbytes + op->addr.nbytes +
694 op->dummy.nbytes / op->dummy.buswidth;
695 dummy_bytes = op->dummy.nbytes / op->dummy.buswidth;
700 op_buf[pos++] = op->cmd.opcode;
702 if (op->addr.nbytes) {
703 for (i = 0; i < op->addr.nbytes; i++)
704 op_buf[pos + i] = op->addr.val >>
705 (8 * (op->addr.nbytes - i - 1));
707 pos += op->addr.nbytes;
711 memset(op_buf + pos, 0xff, dummy_bytes);
713 /* 1st transfer: opcode + address + dummy cycles */
714 /* Make sure to set END bit if no tx or rx data messages follow */
715 if (!tx_buf && !rx_buf)
716 flag |= SPI_XFER_END;
718 ret = zynq_qspi_xfer(slave->dev, op_len * 8, op_buf, NULL,
719 flag | SPI_XFER_BEGIN);
723 /* 2nd transfer: rx or tx data path */
724 if (tx_buf || rx_buf) {
725 ret = zynq_qspi_xfer(slave->dev, op->data.nbytes * 8, tx_buf,
726 rx_buf, flag | SPI_XFER_END);
731 spi_release_bus(slave);
736 static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width)
738 u32 mode = slave->mode;
744 if (mode & SPI_RX_DUAL)
748 if (mode & SPI_RX_QUAD)
756 bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
757 const struct spi_mem_op *op)
759 if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth))
762 if (op->addr.nbytes &&
763 zynq_qspi_check_buswidth(slave, op->addr.buswidth))
766 if (op->dummy.nbytes &&
767 zynq_qspi_check_buswidth(slave, op->dummy.buswidth))
770 if (op->data.dir != SPI_MEM_NO_DATA &&
771 zynq_qspi_check_buswidth(slave, op->data.buswidth))
777 static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
778 .exec_op = zynq_qspi_exec_op,
779 .supports_op = zynq_qspi_mem_exec_op,
782 static const struct dm_spi_ops zynq_qspi_ops = {
783 .claim_bus = zynq_qspi_claim_bus,
784 .release_bus = zynq_qspi_release_bus,
785 .xfer = zynq_qspi_xfer,
786 .set_speed = zynq_qspi_set_speed,
787 .set_mode = zynq_qspi_set_mode,
788 .mem_ops = &zynq_qspi_mem_ops,
791 static const struct udevice_id zynq_qspi_ids[] = {
792 { .compatible = "xlnx,zynq-qspi-1.0" },
796 U_BOOT_DRIVER(zynq_qspi) = {
799 .of_match = zynq_qspi_ids,
800 .ops = &zynq_qspi_ops,
801 .of_to_plat = zynq_qspi_of_to_plat,
802 .plat_auto = sizeof(struct zynq_qspi_plat),
803 .priv_auto = sizeof(struct zynq_qspi_priv),
804 .probe = zynq_qspi_probe,
805 .child_pre_probe = zynq_qspi_child_pre_probe,