1 // SPDX-License-Identifier: GPL-2.0+
5 * Supports 8 bit SPI transfers only, with or w/o FIFO
7 * Based on bfin_spi.c, by way of altera_spi.c
8 * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
9 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
10 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
11 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
12 * Copyright (c) 2005-2008 Analog Devices Inc.
25 #include <linux/bitops.h>
28 * [0]: http://www.xilinx.com/support/documentation
30 * Xilinx SPI Register Definitions
31 * [1]: [0]/ip_documentation/xps_spi.pdf
32 * page 8, Register Descriptions
33 * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
34 * page 7, Register Overview Table
37 /* SPI Control Register (spicr), [1] p9, [2] p8 */
38 #define SPICR_LSB_FIRST BIT(9)
39 #define SPICR_MASTER_INHIBIT BIT(8)
40 #define SPICR_MANUAL_SS BIT(7)
41 #define SPICR_RXFIFO_RESEST BIT(6)
42 #define SPICR_TXFIFO_RESEST BIT(5)
43 #define SPICR_CPHA BIT(4)
44 #define SPICR_CPOL BIT(3)
45 #define SPICR_MASTER_MODE BIT(2)
46 #define SPICR_SPE BIT(1)
47 #define SPICR_LOOP BIT(0)
49 /* SPI Status Register (spisr), [1] p11, [2] p10 */
50 #define SPISR_SLAVE_MODE_SELECT BIT(5)
51 #define SPISR_MODF BIT(4)
52 #define SPISR_TX_FULL BIT(3)
53 #define SPISR_TX_EMPTY BIT(2)
54 #define SPISR_RX_FULL BIT(1)
55 #define SPISR_RX_EMPTY BIT(0)
57 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
58 #define SPIDTR_8BIT_MASK GENMASK(7, 0)
59 #define SPIDTR_16BIT_MASK GENMASK(15, 0)
60 #define SPIDTR_32BIT_MASK GENMASK(31, 0)
62 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
63 #define SPIDRR_8BIT_MASK GENMASK(7, 0)
64 #define SPIDRR_16BIT_MASK GENMASK(15, 0)
65 #define SPIDRR_32BIT_MASK GENMASK(31, 0)
67 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
68 #define SPISSR_MASK(cs) (1 << (cs))
69 #define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
70 #define SPISSR_OFF ~0UL
72 /* SPI Software Reset Register (ssr) */
73 #define SPISSR_RESET_VALUE 0x0a
75 #define XILSPI_MAX_XFER_BITS 8
76 #define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
77 SPICR_SPE | SPICR_MASTER_INHIBIT)
78 #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
80 #define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
82 #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
84 /* xilinx spi register set */
85 struct xilinx_spi_regs {
87 u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
88 u32 ipisr; /* IP Interrupt Status Register (IPISR) */
90 u32 ipier; /* IP Interrupt Enable Register (IPIER) */
92 u32 srr; /* Softare Reset Register (SRR) */
94 u32 spicr; /* SPI Control Register (SPICR) */
95 u32 spisr; /* SPI Status Register (SPISR) */
96 u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
97 u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
98 u32 spissr; /* SPI Slave Select Register (SPISSR) */
99 u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
100 u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
103 /* xilinx spi priv */
104 struct xilinx_spi_priv {
105 struct xilinx_spi_regs *regs;
108 unsigned int fifo_depth;
112 static int xilinx_spi_probe(struct udevice *bus)
114 struct xilinx_spi_priv *priv = dev_get_priv(bus);
115 struct xilinx_spi_regs *regs = priv->regs;
117 priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
119 priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
121 writel(SPISSR_RESET_VALUE, ®s->srr);
125 * Enable Manual Slave Select Assertion,
126 * Set SPI controller into master mode, and enable it
128 writel(SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST |
129 SPICR_MANUAL_SS | SPICR_MASTER_MODE | SPICR_SPE,
135 static void spi_cs_activate(struct udevice *dev, uint cs)
137 struct udevice *bus = dev_get_parent(dev);
138 struct xilinx_spi_priv *priv = dev_get_priv(bus);
139 struct xilinx_spi_regs *regs = priv->regs;
141 writel(SPISSR_ACT(cs), ®s->spissr);
144 static void spi_cs_deactivate(struct udevice *dev)
146 struct udevice *bus = dev_get_parent(dev);
147 struct xilinx_spi_priv *priv = dev_get_priv(bus);
148 struct xilinx_spi_regs *regs = priv->regs;
151 reg = readl(®s->spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST;
152 writel(reg, ®s->spicr);
153 writel(SPISSR_OFF, ®s->spissr);
156 static int xilinx_spi_claim_bus(struct udevice *dev)
158 struct udevice *bus = dev_get_parent(dev);
159 struct xilinx_spi_priv *priv = dev_get_priv(bus);
160 struct xilinx_spi_regs *regs = priv->regs;
162 writel(SPISSR_OFF, ®s->spissr);
163 writel(XILSPI_SPICR_DFLT_ON, ®s->spicr);
168 static int xilinx_spi_release_bus(struct udevice *dev)
170 struct udevice *bus = dev_get_parent(dev);
171 struct xilinx_spi_priv *priv = dev_get_priv(bus);
172 struct xilinx_spi_regs *regs = priv->regs;
174 writel(SPISSR_OFF, ®s->spissr);
175 writel(XILSPI_SPICR_DFLT_OFF, ®s->spicr);
180 static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
183 struct xilinx_spi_priv *priv = dev_get_priv(bus);
184 struct xilinx_spi_regs *regs = priv->regs;
188 while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) &&
189 i < priv->fifo_depth) {
190 d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
191 debug("spi_xfer: tx:%x ", d);
192 /* write out and wait for processing (receive data) */
193 writel(d & SPIDTR_8BIT_MASK, ®s->spidtr);
201 static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
203 struct xilinx_spi_priv *priv = dev_get_priv(bus);
204 struct xilinx_spi_regs *regs = priv->regs;
208 while (rxbytes && !(readl(®s->spisr) & SPISR_RX_EMPTY)) {
209 d = readl(®s->spidrr) & SPIDRR_8BIT_MASK;
212 debug("spi_xfer: rx:%x\n", d);
221 static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len)
223 struct udevice *bus = spi->dev->parent;
224 struct xilinx_spi_priv *priv = dev_get_priv(bus);
225 struct xilinx_spi_regs *regs = priv->regs;
226 u32 count, txbytes, rxbytes;
228 const unsigned char *txp = (const unsigned char *)dout;
229 unsigned char *rxp = (unsigned char *)din;
233 while (txbytes || rxbytes) {
234 /* Disable master transaction */
235 reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
236 writel(reg, ®s->spicr);
237 count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
238 /* Enable master transaction */
239 reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT;
240 writel(reg, ®s->spicr);
245 ret = wait_for_bit_le32(®s->spisr, SPISR_TX_EMPTY, true,
246 XILINX_SPISR_TIMEOUT, false);
248 printf("XILSPI error: Xfer timeout\n");
252 reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
253 writel(reg, ®s->spicr);
254 count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
263 static void xilinx_spi_startup_block(struct spi_slave *spi)
265 struct dm_spi_slave_plat *slave_plat =
266 dev_get_parent_plat(spi->dev);
268 unsigned char rxp[8];
271 * Perform a dummy read as a work around for
272 * the startup block issue.
274 spi_cs_activate(spi->dev, slave_plat->cs);
276 start_transfer(spi, (void *)&txp, NULL, 1);
278 start_transfer(spi, NULL, (void *)rxp, 6);
280 spi_cs_deactivate(spi->dev);
283 static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
284 const struct spi_mem_op *op)
286 struct dm_spi_slave_plat *slave_plat =
287 dev_get_parent_plat(spi->dev);
292 * This is the work around for the startup block issue in
293 * the spi controller. SPI clock is passing through STARTUP
294 * block to FLASH. STARTUP block don't provide clock as soon
295 * as QSPI provides command. So first command fails.
298 xilinx_spi_startup_block(spi);
302 spi_cs_activate(spi->dev, slave_plat->cs);
304 if (op->cmd.opcode) {
305 ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
309 if (op->addr.nbytes) {
313 for (i = 0; i < op->addr.nbytes; i++)
314 addr_buf[i] = op->addr.val >>
315 (8 * (op->addr.nbytes - i - 1));
317 ret = start_transfer(spi, (void *)addr_buf, NULL,
322 if (op->dummy.nbytes) {
323 dummy_len = (op->dummy.nbytes * op->data.buswidth) /
326 ret = start_transfer(spi, NULL, NULL, dummy_len);
330 if (op->data.nbytes) {
331 if (op->data.dir == SPI_MEM_DATA_IN) {
332 ret = start_transfer(spi, NULL,
333 op->data.buf.in, op->data.nbytes);
335 ret = start_transfer(spi, op->data.buf.out,
336 NULL, op->data.nbytes);
342 spi_cs_deactivate(spi->dev);
347 static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width)
349 u32 mode = slave->mode;
355 if (mode & SPI_RX_DUAL)
359 if (mode & SPI_RX_QUAD)
367 bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
368 const struct spi_mem_op *op)
370 if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth))
373 if (op->addr.nbytes &&
374 xilinx_qspi_check_buswidth(slave, op->addr.buswidth))
377 if (op->dummy.nbytes &&
378 xilinx_qspi_check_buswidth(slave, op->dummy.buswidth))
381 if (op->data.dir != SPI_MEM_NO_DATA &&
382 xilinx_qspi_check_buswidth(slave, op->data.buswidth))
388 static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
390 struct xilinx_spi_priv *priv = dev_get_priv(bus);
394 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
399 static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
401 struct xilinx_spi_priv *priv = dev_get_priv(bus);
402 struct xilinx_spi_regs *regs = priv->regs;
405 spicr = readl(®s->spicr);
406 if (mode & SPI_LSB_FIRST)
407 spicr |= SPICR_LSB_FIRST;
415 writel(spicr, ®s->spicr);
418 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
423 static const struct spi_controller_mem_ops xilinx_spi_mem_ops = {
424 .exec_op = xilinx_spi_mem_exec_op,
425 .supports_op = xilinx_qspi_mem_exec_op,
428 static const struct dm_spi_ops xilinx_spi_ops = {
429 .claim_bus = xilinx_spi_claim_bus,
430 .release_bus = xilinx_spi_release_bus,
431 .set_speed = xilinx_spi_set_speed,
432 .set_mode = xilinx_spi_set_mode,
433 .mem_ops = &xilinx_spi_mem_ops,
436 static const struct udevice_id xilinx_spi_ids[] = {
437 { .compatible = "xlnx,xps-spi-2.00.a" },
438 { .compatible = "xlnx,xps-spi-2.00.b" },
442 U_BOOT_DRIVER(xilinx_spi) = {
443 .name = "xilinx_spi",
445 .of_match = xilinx_spi_ids,
446 .ops = &xilinx_spi_ops,
447 .priv_auto = sizeof(struct xilinx_spi_priv),
448 .probe = xilinx_spi_probe,