1 // SPDX-License-Identifier: GPL-2.0+
3 * uniphier_spi.c - Socionext UniPhier SPI driver
4 * Copyright 2019 Socionext, Inc.
10 #include <linux/bitfield.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 #define SSI_CTL_EN BIT(0)
21 #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
22 #define SSI_CKS_CKPHS BIT(14)
23 #define SSI_CKS_CKINIT BIT(13)
24 #define SSI_CKS_CKDLY BIT(12)
26 #define SSI_TXWDS 0x08
27 #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
28 #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
29 #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
31 #define SSI_RXWDS 0x0c
32 #define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
33 #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
36 #define SSI_FPS_FSPOL BIT(15)
37 #define SSI_FPS_FSTRT BIT(14)
40 #define SSI_SR_BUSY BIT(7)
41 #define SSI_SR_TNF BIT(5)
42 #define SSI_SR_RNE BIT(0)
47 #define SSI_IC_TCIC BIT(4)
48 #define SSI_IC_RCIC BIT(3)
49 #define SSI_IC_RORIC BIT(0)
52 #define SSI_FC_TXFFL BIT(12)
53 #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
54 #define SSI_FC_RXFFL BIT(4)
55 #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
57 #define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
59 #define SSI_FIFO_DEPTH 8U
61 #define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
62 #define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
64 #define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
66 struct uniphier_spi_platdata {
68 u32 frequency; /* input frequency */
70 uint deactivate_delay_us; /* Delay to wait after deactivate */
71 uint activate_delay_us; /* Delay to wait after activate */
74 struct uniphier_spi_priv {
79 ulong last_transaction_us; /* Time of last transaction end */
82 static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
86 val = readl(priv->base + SSI_CTL);
91 writel(val, priv->base + SSI_CTL);
94 static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
96 pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
97 pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
98 pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
99 pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
100 pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
101 pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
102 pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
103 pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
104 pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
105 pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
108 static void spi_cs_activate(struct udevice *dev)
110 struct udevice *bus = dev->parent;
111 struct uniphier_spi_platdata *plat = bus->platdata;
112 struct uniphier_spi_priv *priv = dev_get_priv(bus);
113 ulong delay_us; /* The delay completed so far */
116 /* If it's too soon to do another transaction, wait */
117 if (plat->deactivate_delay_us && priv->last_transaction_us) {
118 delay_us = timer_get_us() - priv->last_transaction_us;
119 if (delay_us < plat->deactivate_delay_us)
120 udelay(plat->deactivate_delay_us - delay_us);
123 val = readl(priv->base + SSI_FPS);
124 if (priv->mode & SPI_CS_HIGH)
125 val |= SSI_FPS_FSPOL;
127 val &= ~SSI_FPS_FSPOL;
128 writel(val, priv->base + SSI_FPS);
130 if (plat->activate_delay_us)
131 udelay(plat->activate_delay_us);
134 static void spi_cs_deactivate(struct udevice *dev)
136 struct udevice *bus = dev->parent;
137 struct uniphier_spi_platdata *plat = bus->platdata;
138 struct uniphier_spi_priv *priv = dev_get_priv(bus);
141 val = readl(priv->base + SSI_FPS);
142 if (priv->mode & SPI_CS_HIGH)
143 val &= ~SSI_FPS_FSPOL;
145 val |= SSI_FPS_FSPOL;
146 writel(val, priv->base + SSI_FPS);
148 /* Remember time of this transaction so we can honour the bus delay */
149 if (plat->deactivate_delay_us)
150 priv->last_transaction_us = timer_get_us();
153 static int uniphier_spi_claim_bus(struct udevice *dev)
155 struct udevice *bus = dev->parent;
156 struct uniphier_spi_priv *priv = dev_get_priv(bus);
159 uniphier_spi_enable(priv, false);
161 /* disable interrupts */
162 writel(0, priv->base + SSI_IE);
165 size = priv->bits_per_word;
166 val = readl(priv->base + SSI_TXWDS);
167 val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
168 val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
169 val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
170 writel(val, priv->base + SSI_TXWDS);
172 val = readl(priv->base + SSI_RXWDS);
173 val &= ~SSI_RXWDS_DTLEN_MASK;
174 val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
175 writel(val, priv->base + SSI_RXWDS);
178 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
179 writel(val, priv->base + SSI_FC);
182 val = readl(priv->base + SSI_FC);
183 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
184 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
185 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
186 writel(val, priv->base + SSI_FC);
188 /* clear interrupts */
189 writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
190 priv->base + SSI_IC);
192 uniphier_spi_enable(priv, true);
197 static int uniphier_spi_release_bus(struct udevice *dev)
199 struct udevice *bus = dev->parent;
200 struct uniphier_spi_priv *priv = dev_get_priv(bus);
202 uniphier_spi_enable(priv, false);
207 static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
208 const void *dout, void *din, unsigned long flags)
210 struct udevice *bus = dev->parent;
211 struct uniphier_spi_priv *priv = dev_get_priv(bus);
212 const u8 *tx_buf = dout;
213 u8 *rx_buf = din, buf;
214 u32 len = bitlen / 8;
220 dev_err(dev, "Non byte aligned SPI transfer\n");
224 if (flags & SPI_XFER_BEGIN)
225 spi_cs_activate(dev);
227 uniphier_spi_enable(priv, true);
233 uniphier_spi_regdump(priv);
235 while (tx_len || rx_len) {
236 ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
237 SSI_REG_TIMEOUT * 1000, false);
239 if (ret == -ETIMEDOUT)
240 dev_err(dev, "access timeout\n");
244 status = readl(priv->base + SSI_SR);
245 /* write the data into TX */
246 if (tx_len && (status & SSI_SR_TNF)) {
247 buf = tx_buf ? *tx_buf++ : 0;
248 writel(buf, priv->base + SSI_XDR);
252 /* read the data from RX */
253 if (rx_len && (status & SSI_SR_RNE)) {
254 buf = readl(priv->base + SSI_XDR);
260 if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
261 dev_err(dev, "transfer timeout\n");
267 if (flags & SPI_XFER_END)
268 spi_cs_deactivate(dev);
270 uniphier_spi_enable(priv, false);
275 static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
277 struct uniphier_spi_platdata *plat = bus->platdata;
278 struct uniphier_spi_priv *priv = dev_get_priv(bus);
281 if (speed > plat->frequency)
282 speed = plat->frequency;
285 ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
286 ckdiv = round_up(ckdiv, 2);
288 val = readl(priv->base + SSI_CKS);
289 val &= ~SSI_CKS_CKRAT_MASK;
290 val |= ckdiv & SSI_CKS_CKRAT_MASK;
291 writel(val, priv->base + SSI_CKS);
296 static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
298 struct uniphier_spi_priv *priv = dev_get_priv(bus);
303 * CKPHS capture timing. 0:rising edge, 1:falling edge
304 * CKINIT clock initial level. 0:low, 1:high
305 * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
306 * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
309 * FSPOL frame signal porarity. 0: low, 1: high
310 * FSTRT start frame timing
311 * 0: rising edge of clock, 1: falling edge of clock
313 val1 = readl(priv->base + SSI_CKS);
314 val2 = readl(priv->base + SSI_FPS);
316 switch (mode & (SPI_CPOL | SPI_CPHA)) {
318 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
319 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
320 val1 &= ~SSI_CKS_CKINIT;
321 val2 &= ~SSI_FPS_FSTRT;
324 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
325 val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
326 val2 |= SSI_FPS_FSTRT;
329 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
330 val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
331 val1 &= ~SSI_CKS_CKPHS;
332 val2 |= SSI_FPS_FSTRT;
335 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
336 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
337 val1 &= ~SSI_CKS_CKDLY;
338 val2 &= ~SSI_FPS_FSTRT;
342 writel(val1, priv->base + SSI_CKS);
343 writel(val2, priv->base + SSI_FPS);
346 val1 = readl(priv->base + SSI_TXWDS);
347 val2 = readl(priv->base + SSI_RXWDS);
348 if (mode & SPI_LSB_FIRST) {
349 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
350 val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
352 writel(val1, priv->base + SSI_TXWDS);
353 writel(val2, priv->base + SSI_RXWDS);
360 static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
362 struct uniphier_spi_platdata *plat = bus->platdata;
363 const void *blob = gd->fdt_blob;
364 int node = dev_of_offset(bus);
366 plat->base = devfdt_get_addr_ptr(bus);
369 fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
370 plat->deactivate_delay_us =
371 fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
372 plat->activate_delay_us =
373 fdtdec_get_int(blob, node, "spi-activate-delay", 0);
374 plat->speed_hz = plat->frequency / 2;
379 static int uniphier_spi_probe(struct udevice *bus)
381 struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
382 struct uniphier_spi_priv *priv = dev_get_priv(bus);
384 priv->base = plat->base;
385 priv->fifo_depth = SSI_FIFO_DEPTH;
386 priv->bits_per_word = 8;
391 static const struct dm_spi_ops uniphier_spi_ops = {
392 .claim_bus = uniphier_spi_claim_bus,
393 .release_bus = uniphier_spi_release_bus,
394 .xfer = uniphier_spi_xfer,
395 .set_speed = uniphier_spi_set_speed,
396 .set_mode = uniphier_spi_set_mode,
399 static const struct udevice_id uniphier_spi_ids[] = {
400 { .compatible = "socionext,uniphier-scssi" },
404 U_BOOT_DRIVER(uniphier_spi) = {
405 .name = "uniphier_spi",
407 .of_match = uniphier_spi_ids,
408 .ops = &uniphier_spi_ops,
409 .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
410 .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
411 .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
412 .probe = uniphier_spi_probe,