drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/cache.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/omap.h>
  14 #include <malloc.h>
  15 #include <spi.h>
  16 #include <spi-mem.h>
  17 #include <dm.h>
  18 #include <asm/gpio.h>
  19 #include <asm/omap_gpio.h>
  20 #include <asm/omap_common.h>
  21 #include <asm/ti-common/ti-edma3.h>
  22 #include <linux/err.h>
  23 #include <linux/kernel.h>
  24 #include <regmap.h>
  25 #include <syscon.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* ti qpsi register bit masks */
  30 #define QSPI_TIMEOUT                    2000000
  31 #define QSPI_FCLK                       192000000
  32 #define QSPI_DRA7XX_FCLK                76800000
  33 #define QSPI_WLEN_MAX_BITS              128
  34 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  35 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  36 /* clock control */
  37 #define QSPI_CLK_EN                     BIT(31)
  38 #define QSPI_CLK_DIV_MAX                0xffff
  39 /* command */
  40 #define QSPI_EN_CS(n)                   (n << 28)
  41 #define QSPI_WLEN(n)                    ((n-1) << 19)
  42 #define QSPI_3_PIN                      BIT(18)
  43 #define QSPI_RD_SNGL                    BIT(16)
  44 #define QSPI_WR_SNGL                    (2 << 16)
  45 #define QSPI_INVAL                      (4 << 16)
  46 #define QSPI_RD_QUAD                    (7 << 16)
  47 /* device control */
  48 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  49 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  50 #define QSPI_CKPOL(n)                   (1 << (n*8))
  51 /* status */
  52 #define QSPI_WC                         BIT(1)
  53 #define QSPI_BUSY                       BIT(0)
  54 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  55 #define QSPI_XFER_DONE                  QSPI_WC
  56 #define MM_SWITCH                       0x01
  57 #define MEM_CS(cs)                      ((cs + 1) << 8)
  58 #define MEM_CS_UNSELECT                 0xfffff8ff
  59
  60 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  61 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  62 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  63 #define QSPI_SETUP0_ADDR_SHIFT          (8)
  64 #define QSPI_SETUP0_DBITS_SHIFT         (10)
  65
  66 #define TI_QSPI_SETUP_REG(priv, cs)     (&(priv)->base->setup0 + (cs))
  67
  68 /* ti qspi register set */
  69 struct ti_qspi_regs {
  70         u32 pid;
  71         u32 pad0[3];
  72         u32 sysconfig;
  73         u32 pad1[3];
  74         u32 int_stat_raw;
  75         u32 int_stat_en;
  76         u32 int_en_set;
  77         u32 int_en_ctlr;
  78         u32 intc_eoi;
  79         u32 pad2[3];
  80         u32 clk_ctrl;
  81         u32 dc;
  82         u32 cmd;
  83         u32 status;
  84         u32 data;
  85         u32 setup0;
  86         u32 setup1;
  87         u32 setup2;
  88         u32 setup3;
  89         u32 memswitch;
  90         u32 data1;
  91         u32 data2;
  92         u32 data3;
  93 };
  94
  95 /* ti qspi priv */
  96 struct ti_qspi_priv {
  97         void *memory_map;
  98         size_t mmap_size;
  99         uint max_hz;
 100         u32 num_cs;
 101         struct ti_qspi_regs *base;
 102         void *ctrl_mod_mmap;
 103         ulong fclk;
 104         unsigned int mode;
 105         u32 cmd;
 106         u32 dc;
 107 };
 108
 109 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 110 {
 111         struct ti_qspi_priv *priv = dev_get_priv(bus);
 112         uint clk_div;
 113
 114         if (!hz)
 115                 clk_div = 0;
 116         else
 117                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 118
 119         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 120         if (clk_div > QSPI_CLK_DIV_MAX)
 121                 clk_div = QSPI_CLK_DIV_MAX;
 122
 123         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 124
 125         /* disable SCLK */
 126         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 127                &priv->base->clk_ctrl);
 128         /* enable SCLK and program the clk divider */
 129         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 130
 131         return 0;
 132 }
 133
 134 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 135 {
 136         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 137         /* dummy readl to ensure bus sync */
 138         readl(&priv->base->cmd);
 139 }
 140
 141 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 142 {
 143         u32 val;
 144
 145         val = readl(ctrl_mod_mmap);
 146         if (enable)
 147                 val |= MEM_CS(cs);
 148         else
 149                 val &= MEM_CS_UNSELECT;
 150         writel(val, ctrl_mod_mmap);
 151 }
 152
 153 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 154                         const void *dout, void *din, unsigned long flags)
 155 {
 156         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 157         struct ti_qspi_priv *priv;
 158         struct udevice *bus;
 159         uint words = bitlen >> 3; /* fixed 8-bit word length */
 160         const uchar *txp = dout;
 161         uchar *rxp = din;
 162         uint status;
 163         int timeout;
 164         unsigned int cs = slave->cs;
 165
 166         bus = dev->parent;
 167         priv = dev_get_priv(bus);
 168
 169         if (cs > priv->num_cs) {
 170                 debug("invalid qspi chip select\n");
 171                 return -EINVAL;
 172         }
 173
 174         if (bitlen == 0)
 175                 return -1;
 176
 177         if (bitlen % 8) {
 178                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 179                 return -1;
 180         }
 181
 182         /* Setup command reg */
 183         priv->cmd = 0;
 184         priv->cmd |= QSPI_WLEN(8);
 185         priv->cmd |= QSPI_EN_CS(cs);
 186         if (priv->mode & SPI_3WIRE)
 187                 priv->cmd |= QSPI_3_PIN;
 188         priv->cmd |= 0xfff;
 189
 190         while (words) {
 191                 u8 xfer_len = 0;
 192
 193                 if (txp) {
 194                         u32 cmd = priv->cmd;
 195
 196                         if (words >= QSPI_WLEN_MAX_BYTES) {
 197                                 u32 *txbuf = (u32 *)txp;
 198                                 u32 data;
 199
 200                                 data = cpu_to_be32(*txbuf++);
 201                                 writel(data, &priv->base->data3);
 202                                 data = cpu_to_be32(*txbuf++);
 203                                 writel(data, &priv->base->data2);
 204                                 data = cpu_to_be32(*txbuf++);
 205                                 writel(data, &priv->base->data1);
 206                                 data = cpu_to_be32(*txbuf++);
 207                                 writel(data, &priv->base->data);
 208                                 cmd &= ~QSPI_WLEN_MASK;
 209                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 210                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 211                         } else {
 212                                 writeb(*txp, &priv->base->data);
 213                                 xfer_len = 1;
 214                         }
 215                         debug("tx cmd %08x dc %08x\n",
 216                               cmd | QSPI_WR_SNGL, priv->dc);
 217                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 218                         status = readl(&priv->base->status);
 219                         timeout = QSPI_TIMEOUT;
 220                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 221                                 if (--timeout < 0) {
 222                                         printf("spi_xfer: TX timeout!\n");
 223                                         return -1;
 224                                 }
 225                                 status = readl(&priv->base->status);
 226                         }
 227                         txp += xfer_len;
 228                         debug("tx done, status %08x\n", status);
 229                 }
 230                 if (rxp) {
 231                         debug("rx cmd %08x dc %08x\n",
 232                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 233                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 234                         status = readl(&priv->base->status);
 235                         timeout = QSPI_TIMEOUT;
 236                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 237                                 if (--timeout < 0) {
 238                                         printf("spi_xfer: RX timeout!\n");
 239                                         return -1;
 240                                 }
 241                                 status = readl(&priv->base->status);
 242                         }
 243                         *rxp++ = readl(&priv->base->data);
 244                         xfer_len = 1;
 245                         debug("rx done, status %08x, read %02x\n",
 246                               status, *(rxp-1));
 247                 }
 248                 words -= xfer_len;
 249         }
 250
 251         /* Terminate frame */
 252         if (flags & SPI_XFER_END)
 253                 ti_qspi_cs_deactivate(priv);
 254
 255         return 0;
 256 }
 257
 258 /* TODO: control from sf layer to here through dm-spi */
 259 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 260 {
 261 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 262         unsigned int                    addr = (unsigned int) (data);
 263         unsigned int                    edma_slot_num = 1;
 264
 265         /* Invalidate the area, so no writeback into the RAM races with DMA */
 266         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 267
 268         /* enable edma3 clocks */
 269         enable_edma3_clocks();
 270
 271         /* Call edma3 api to do actual DMA transfer     */
 272         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 273
 274         /* disable edma3 clocks */
 275         disable_edma3_clocks();
 276 #else
 277         memcpy_fromio(data, offset, len);
 278 #endif
 279
 280         *((unsigned int *)offset) += len;
 281 }
 282
 283 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
 284                                     u8 opcode, u8 data_nbits, u8 addr_width,
 285                                     u8 dummy_bytes)
 286 {
 287         u32 memval = opcode;
 288
 289         switch (data_nbits) {
 290         case 4:
 291                 memval |= QSPI_SETUP0_READ_QUAD;
 292                 break;
 293         case 2:
 294                 memval |= QSPI_SETUP0_READ_DUAL;
 295                 break;
 296         default:
 297                 memval |= QSPI_SETUP0_READ_NORMAL;
 298                 break;
 299         }
 300
 301         memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
 302                    dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
 303
 304         writel(memval, TI_QSPI_SETUP_REG(priv, cs));
 305 }
 306
 307 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 308 {
 309         struct ti_qspi_priv *priv = dev_get_priv(bus);
 310
 311         priv->dc = 0;
 312         if (mode & SPI_CPHA)
 313                 priv->dc |= QSPI_CKPHA(0);
 314         if (mode & SPI_CPOL)
 315                 priv->dc |= QSPI_CKPOL(0);
 316         if (mode & SPI_CS_HIGH)
 317                 priv->dc |= QSPI_CSPOL(0);
 318
 319         return 0;
 320 }
 321
 322 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
 323                                const struct spi_mem_op *op)
 324 {
 325         struct dm_spi_slave_platdata *slave_plat;
 326         struct ti_qspi_priv *priv;
 327         struct udevice *bus;
 328         u32 from = 0;
 329         int ret = 0;
 330
 331         bus = slave->dev->parent;
 332         priv = dev_get_priv(bus);
 333         slave_plat = dev_get_parent_platdata(slave->dev);
 334
 335         /* Only optimize read path. */
 336         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 337             !op->addr.nbytes || op->addr.nbytes > 4)
 338                 return -ENOTSUPP;
 339
 340         /* Address exceeds MMIO window size, fall back to regular mode. */
 341         from = op->addr.val;
 342         if (from + op->data.nbytes > priv->mmap_size)
 343                 return -ENOTSUPP;
 344
 345         ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
 346                                 op->data.buswidth, op->addr.nbytes,
 347                                 op->dummy.nbytes);
 348
 349         ti_qspi_copy_mmap((void *)op->data.buf.in,
 350                           (void *)priv->memory_map + from, op->data.nbytes);
 351
 352         return ret;
 353 }
 354
 355 static int ti_qspi_claim_bus(struct udevice *dev)
 356 {
 357         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 358         struct ti_qspi_priv *priv;
 359         struct udevice *bus;
 360
 361         bus = dev->parent;
 362         priv = dev_get_priv(bus);
 363
 364         if (slave_plat->cs > priv->num_cs) {
 365                 debug("invalid qspi chip select\n");
 366                 return -EINVAL;
 367         }
 368
 369         writel(MM_SWITCH, &priv->base->memswitch);
 370         if (priv->ctrl_mod_mmap)
 371                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 372                                        slave_plat->cs, true);
 373
 374         writel(priv->dc, &priv->base->dc);
 375         writel(0, &priv->base->cmd);
 376         writel(0, &priv->base->data);
 377
 378         priv->dc <<= slave_plat->cs * 8;
 379         writel(priv->dc, &priv->base->dc);
 380
 381         return 0;
 382 }
 383
 384 static int ti_qspi_release_bus(struct udevice *dev)
 385 {
 386         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 387         struct ti_qspi_priv *priv;
 388         struct udevice *bus;
 389
 390         bus = dev->parent;
 391         priv = dev_get_priv(bus);
 392
 393         writel(~MM_SWITCH, &priv->base->memswitch);
 394         if (priv->ctrl_mod_mmap)
 395                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 396                                        slave_plat->cs, false);
 397
 398         writel(0, &priv->base->dc);
 399         writel(0, &priv->base->cmd);
 400         writel(0, &priv->base->data);
 401         writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
 402
 403         return 0;
 404 }
 405
 406 static int ti_qspi_probe(struct udevice *bus)
 407 {
 408         struct ti_qspi_priv *priv = dev_get_priv(bus);
 409
 410         priv->fclk = dev_get_driver_data(bus);
 411
 412         return 0;
 413 }
 414
 415 static void *map_syscon_chipselects(struct udevice *bus)
 416 {
 417 #if CONFIG_IS_ENABLED(SYSCON)
 418         struct udevice *syscon;
 419         struct regmap *regmap;
 420         const fdt32_t *cell;
 421         int len, err;
 422
 423         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 424                                            "syscon-chipselects", &syscon);
 425         if (err) {
 426                 debug("%s: unable to find syscon device (%d)\n", __func__,
 427                       err);
 428                 return NULL;
 429         }
 430
 431         regmap = syscon_get_regmap(syscon);
 432         if (IS_ERR(regmap)) {
 433                 debug("%s: unable to find regmap (%ld)\n", __func__,
 434                       PTR_ERR(regmap));
 435                 return NULL;
 436         }
 437
 438         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 439                            "syscon-chipselects", &len);
 440         if (len < 2*sizeof(fdt32_t)) {
 441                 debug("%s: offset not available\n", __func__);
 442                 return NULL;
 443         }
 444
 445         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 446 #else
 447         fdt_addr_t addr;
 448         addr = devfdt_get_addr_index(bus, 2);
 449         return (addr == FDT_ADDR_T_NONE) ? NULL :
 450                 map_physmem(addr, 0, MAP_NOCACHE);
 451 #endif
 452 }
 453
 454 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 455 {
 456         struct ti_qspi_priv *priv = dev_get_priv(bus);
 457         const void *blob = gd->fdt_blob;
 458         int node = dev_of_offset(bus);
 459         fdt_addr_t mmap_addr;
 460         fdt_addr_t mmap_size;
 461
 462         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 463         priv->base = map_physmem(devfdt_get_addr(bus),
 464                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 465         mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
 466         priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
 467         priv->mmap_size = mmap_size;
 468
 469         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 470         if (priv->max_hz < 0) {
 471                 debug("Error: Max frequency missing\n");
 472                 return -ENODEV;
 473         }
 474         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 475
 476         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 477               (int)priv->base, priv->max_hz);
 478
 479         return 0;
 480 }
 481
 482 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 483         .exec_op = ti_qspi_exec_mem_op,
 484 };
 485
 486 static const struct dm_spi_ops ti_qspi_ops = {
 487         .claim_bus      = ti_qspi_claim_bus,
 488         .release_bus    = ti_qspi_release_bus,
 489         .xfer           = ti_qspi_xfer,
 490         .set_speed      = ti_qspi_set_speed,
 491         .set_mode       = ti_qspi_set_mode,
 492         .mem_ops        = &ti_qspi_mem_ops,
 493 };
 494
 495 static const struct udevice_id ti_qspi_ids[] = {
 496         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 497         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 498         { }
 499 };
 500
 501 U_BOOT_DRIVER(ti_qspi) = {
 502         .name   = "ti_qspi",
 503         .id     = UCLASS_SPI,
 504         .of_match = ti_qspi_ids,
 505         .ops    = &ti_qspi_ops,
 506         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 507         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 508         .probe  = ti_qspi_probe,
 509 };