drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/cache.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/omap.h>
  15 #include <malloc.h>
  16 #include <spi.h>
  17 #include <spi-mem.h>
  18 #include <dm.h>
  19 #include <asm/gpio.h>
  20 #include <asm/omap_gpio.h>
  21 #include <asm/omap_common.h>
  22 #include <asm/ti-common/ti-edma3.h>
  23 #include <linux/bitops.h>
  24 #include <linux/err.h>
  25 #include <linux/kernel.h>
  26 #include <regmap.h>
  27 #include <syscon.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /* ti qpsi register bit masks */
  32 #define QSPI_TIMEOUT                    2000000
  33 #define QSPI_FCLK                       192000000
  34 #define QSPI_DRA7XX_FCLK                76800000
  35 #define QSPI_WLEN_MAX_BITS              128
  36 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  37 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  38 /* clock control */
  39 #define QSPI_CLK_EN                     BIT(31)
  40 #define QSPI_CLK_DIV_MAX                0xffff
  41 /* command */
  42 #define QSPI_EN_CS(n)                   (n << 28)
  43 #define QSPI_WLEN(n)                    ((n-1) << 19)
  44 #define QSPI_3_PIN                      BIT(18)
  45 #define QSPI_RD_SNGL                    BIT(16)
  46 #define QSPI_WR_SNGL                    (2 << 16)
  47 #define QSPI_INVAL                      (4 << 16)
  48 #define QSPI_RD_QUAD                    (7 << 16)
  49 /* device control */
  50 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  51 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  52 #define QSPI_CKPOL(n)                   (1 << (n*8))
  53 /* status */
  54 #define QSPI_WC                         BIT(1)
  55 #define QSPI_BUSY                       BIT(0)
  56 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  57 #define QSPI_XFER_DONE                  QSPI_WC
  58 #define MM_SWITCH                       0x01
  59 #define MEM_CS(cs)                      ((cs + 1) << 8)
  60 #define MEM_CS_UNSELECT                 0xfffff8ff
  61
  62 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  63 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  64 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  65 #define QSPI_SETUP0_ADDR_SHIFT          (8)
  66 #define QSPI_SETUP0_DBITS_SHIFT         (10)
  67
  68 #define TI_QSPI_SETUP_REG(priv, cs)     (&(priv)->base->setup0 + (cs))
  69
  70 /* ti qspi register set */
  71 struct ti_qspi_regs {
  72         u32 pid;
  73         u32 pad0[3];
  74         u32 sysconfig;
  75         u32 pad1[3];
  76         u32 int_stat_raw;
  77         u32 int_stat_en;
  78         u32 int_en_set;
  79         u32 int_en_ctlr;
  80         u32 intc_eoi;
  81         u32 pad2[3];
  82         u32 clk_ctrl;
  83         u32 dc;
  84         u32 cmd;
  85         u32 status;
  86         u32 data;
  87         u32 setup0;
  88         u32 setup1;
  89         u32 setup2;
  90         u32 setup3;
  91         u32 memswitch;
  92         u32 data1;
  93         u32 data2;
  94         u32 data3;
  95 };
  96
  97 /* ti qspi priv */
  98 struct ti_qspi_priv {
  99         void *memory_map;
 100         size_t mmap_size;
 101         uint max_hz;
 102         u32 num_cs;
 103         struct ti_qspi_regs *base;
 104         void *ctrl_mod_mmap;
 105         ulong fclk;
 106         unsigned int mode;
 107         u32 cmd;
 108         u32 dc;
 109 };
 110
 111 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 112 {
 113         struct ti_qspi_priv *priv = dev_get_priv(bus);
 114         uint clk_div;
 115
 116         if (!hz)
 117                 clk_div = 0;
 118         else
 119                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 120
 121         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 122         if (clk_div > QSPI_CLK_DIV_MAX)
 123                 clk_div = QSPI_CLK_DIV_MAX;
 124
 125         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 126
 127         /* disable SCLK */
 128         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 129                &priv->base->clk_ctrl);
 130         /* enable SCLK and program the clk divider */
 131         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 132
 133         return 0;
 134 }
 135
 136 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 137 {
 138         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 139         /* dummy readl to ensure bus sync */
 140         readl(&priv->base->cmd);
 141 }
 142
 143 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 144 {
 145         u32 val;
 146
 147         val = readl(ctrl_mod_mmap);
 148         if (enable)
 149                 val |= MEM_CS(cs);
 150         else
 151                 val &= MEM_CS_UNSELECT;
 152         writel(val, ctrl_mod_mmap);
 153 }
 154
 155 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 156                         const void *dout, void *din, unsigned long flags)
 157 {
 158         struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
 159         struct ti_qspi_priv *priv;
 160         struct udevice *bus;
 161         uint words = bitlen >> 3; /* fixed 8-bit word length */
 162         const uchar *txp = dout;
 163         uchar *rxp = din;
 164         uint status;
 165         int timeout;
 166         unsigned int cs = slave->cs;
 167
 168         bus = dev->parent;
 169         priv = dev_get_priv(bus);
 170
 171         if (cs > priv->num_cs) {
 172                 debug("invalid qspi chip select\n");
 173                 return -EINVAL;
 174         }
 175
 176         if (bitlen == 0)
 177                 return -1;
 178
 179         if (bitlen % 8) {
 180                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 181                 return -1;
 182         }
 183
 184         /* Setup command reg */
 185         priv->cmd = 0;
 186         priv->cmd |= QSPI_WLEN(8);
 187         priv->cmd |= QSPI_EN_CS(cs);
 188         if (priv->mode & SPI_3WIRE)
 189                 priv->cmd |= QSPI_3_PIN;
 190         priv->cmd |= 0xfff;
 191
 192         while (words) {
 193                 u8 xfer_len = 0;
 194
 195                 if (txp) {
 196                         u32 cmd = priv->cmd;
 197
 198                         if (words >= QSPI_WLEN_MAX_BYTES) {
 199                                 u32 *txbuf = (u32 *)txp;
 200                                 u32 data;
 201
 202                                 data = cpu_to_be32(*txbuf++);
 203                                 writel(data, &priv->base->data3);
 204                                 data = cpu_to_be32(*txbuf++);
 205                                 writel(data, &priv->base->data2);
 206                                 data = cpu_to_be32(*txbuf++);
 207                                 writel(data, &priv->base->data1);
 208                                 data = cpu_to_be32(*txbuf++);
 209                                 writel(data, &priv->base->data);
 210                                 cmd &= ~QSPI_WLEN_MASK;
 211                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 212                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 213                         } else {
 214                                 writeb(*txp, &priv->base->data);
 215                                 xfer_len = 1;
 216                         }
 217                         debug("tx cmd %08x dc %08x\n",
 218                               cmd | QSPI_WR_SNGL, priv->dc);
 219                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 220                         status = readl(&priv->base->status);
 221                         timeout = QSPI_TIMEOUT;
 222                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 223                                 if (--timeout < 0) {
 224                                         printf("spi_xfer: TX timeout!\n");
 225                                         return -1;
 226                                 }
 227                                 status = readl(&priv->base->status);
 228                         }
 229                         txp += xfer_len;
 230                         debug("tx done, status %08x\n", status);
 231                 }
 232                 if (rxp) {
 233                         debug("rx cmd %08x dc %08x\n",
 234                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 235                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 236                         status = readl(&priv->base->status);
 237                         timeout = QSPI_TIMEOUT;
 238                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 239                                 if (--timeout < 0) {
 240                                         printf("spi_xfer: RX timeout!\n");
 241                                         return -1;
 242                                 }
 243                                 status = readl(&priv->base->status);
 244                         }
 245                         *rxp++ = readl(&priv->base->data);
 246                         xfer_len = 1;
 247                         debug("rx done, status %08x, read %02x\n",
 248                               status, *(rxp-1));
 249                 }
 250                 words -= xfer_len;
 251         }
 252
 253         /* Terminate frame */
 254         if (flags & SPI_XFER_END)
 255                 ti_qspi_cs_deactivate(priv);
 256
 257         return 0;
 258 }
 259
 260 /* TODO: control from sf layer to here through dm-spi */
 261 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 262 {
 263 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 264         unsigned int                    addr = (unsigned int) (data);
 265         unsigned int                    edma_slot_num = 1;
 266
 267         /* Invalidate the area, so no writeback into the RAM races with DMA */
 268         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 269
 270         /* enable edma3 clocks */
 271         enable_edma3_clocks();
 272
 273         /* Call edma3 api to do actual DMA transfer     */
 274         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 275
 276         /* disable edma3 clocks */
 277         disable_edma3_clocks();
 278 #else
 279         memcpy_fromio(data, offset, len);
 280 #endif
 281
 282         *((unsigned int *)offset) += len;
 283 }
 284
 285 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
 286                                     u8 opcode, u8 data_nbits, u8 addr_width,
 287                                     u8 dummy_bytes)
 288 {
 289         u32 memval = opcode;
 290
 291         switch (data_nbits) {
 292         case 4:
 293                 memval |= QSPI_SETUP0_READ_QUAD;
 294                 break;
 295         case 2:
 296                 memval |= QSPI_SETUP0_READ_DUAL;
 297                 break;
 298         default:
 299                 memval |= QSPI_SETUP0_READ_NORMAL;
 300                 break;
 301         }
 302
 303         memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
 304                    dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
 305
 306         writel(memval, TI_QSPI_SETUP_REG(priv, cs));
 307 }
 308
 309 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 310 {
 311         struct ti_qspi_priv *priv = dev_get_priv(bus);
 312
 313         priv->dc = 0;
 314         if (mode & SPI_CPHA)
 315                 priv->dc |= QSPI_CKPHA(0);
 316         if (mode & SPI_CPOL)
 317                 priv->dc |= QSPI_CKPOL(0);
 318         if (mode & SPI_CS_HIGH)
 319                 priv->dc |= QSPI_CSPOL(0);
 320
 321         return 0;
 322 }
 323
 324 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
 325                                const struct spi_mem_op *op)
 326 {
 327         struct dm_spi_slave_plat *slave_plat;
 328         struct ti_qspi_priv *priv;
 329         struct udevice *bus;
 330         u32 from = 0;
 331         int ret = 0;
 332
 333         bus = slave->dev->parent;
 334         priv = dev_get_priv(bus);
 335         slave_plat = dev_get_parent_plat(slave->dev);
 336
 337         /* Only optimize read path. */
 338         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 339             !op->addr.nbytes || op->addr.nbytes > 4)
 340                 return -ENOTSUPP;
 341
 342         /* Address exceeds MMIO window size, fall back to regular mode. */
 343         from = op->addr.val;
 344         if (from + op->data.nbytes > priv->mmap_size)
 345                 return -ENOTSUPP;
 346
 347         ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
 348                                 op->data.buswidth, op->addr.nbytes,
 349                                 op->dummy.nbytes);
 350
 351         ti_qspi_copy_mmap((void *)op->data.buf.in,
 352                           (void *)priv->memory_map + from, op->data.nbytes);
 353
 354         return ret;
 355 }
 356
 357 static int ti_qspi_claim_bus(struct udevice *dev)
 358 {
 359         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 360         struct ti_qspi_priv *priv;
 361         struct udevice *bus;
 362
 363         bus = dev->parent;
 364         priv = dev_get_priv(bus);
 365
 366         if (slave_plat->cs > priv->num_cs) {
 367                 debug("invalid qspi chip select\n");
 368                 return -EINVAL;
 369         }
 370
 371         writel(MM_SWITCH, &priv->base->memswitch);
 372         if (priv->ctrl_mod_mmap)
 373                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 374                                        slave_plat->cs, true);
 375
 376         writel(priv->dc, &priv->base->dc);
 377         writel(0, &priv->base->cmd);
 378         writel(0, &priv->base->data);
 379
 380         priv->dc <<= slave_plat->cs * 8;
 381         writel(priv->dc, &priv->base->dc);
 382
 383         return 0;
 384 }
 385
 386 static int ti_qspi_release_bus(struct udevice *dev)
 387 {
 388         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 389         struct ti_qspi_priv *priv;
 390         struct udevice *bus;
 391
 392         bus = dev->parent;
 393         priv = dev_get_priv(bus);
 394
 395         writel(~MM_SWITCH, &priv->base->memswitch);
 396         if (priv->ctrl_mod_mmap)
 397                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 398                                        slave_plat->cs, false);
 399
 400         writel(0, &priv->base->dc);
 401         writel(0, &priv->base->cmd);
 402         writel(0, &priv->base->data);
 403         writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
 404
 405         return 0;
 406 }
 407
 408 static int ti_qspi_probe(struct udevice *bus)
 409 {
 410         struct ti_qspi_priv *priv = dev_get_priv(bus);
 411
 412         priv->fclk = dev_get_driver_data(bus);
 413
 414         return 0;
 415 }
 416
 417 static void *map_syscon_chipselects(struct udevice *bus)
 418 {
 419 #if CONFIG_IS_ENABLED(SYSCON)
 420         struct udevice *syscon;
 421         struct regmap *regmap;
 422         const fdt32_t *cell;
 423         int len, err;
 424
 425         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 426                                            "syscon-chipselects", &syscon);
 427         if (err) {
 428                 debug("%s: unable to find syscon device (%d)\n", __func__,
 429                       err);
 430                 return NULL;
 431         }
 432
 433         regmap = syscon_get_regmap(syscon);
 434         if (IS_ERR(regmap)) {
 435                 debug("%s: unable to find regmap (%ld)\n", __func__,
 436                       PTR_ERR(regmap));
 437                 return NULL;
 438         }
 439
 440         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 441                            "syscon-chipselects", &len);
 442         if (len < 2*sizeof(fdt32_t)) {
 443                 debug("%s: offset not available\n", __func__);
 444                 return NULL;
 445         }
 446
 447         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 448 #else
 449         fdt_addr_t addr;
 450         addr = devfdt_get_addr_index(bus, 2);
 451         return (addr == FDT_ADDR_T_NONE) ? NULL :
 452                 map_physmem(addr, 0, MAP_NOCACHE);
 453 #endif
 454 }
 455
 456 static int ti_qspi_of_to_plat(struct udevice *bus)
 457 {
 458         struct ti_qspi_priv *priv = dev_get_priv(bus);
 459         const void *blob = gd->fdt_blob;
 460         int node = dev_of_offset(bus);
 461         fdt_addr_t mmap_addr;
 462         fdt_addr_t mmap_size;
 463
 464         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 465         priv->base = map_physmem(dev_read_addr(bus),
 466                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 467         mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
 468         priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
 469         priv->mmap_size = mmap_size;
 470
 471         priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
 472         if (!priv->max_hz) {
 473                 debug("Error: Max frequency missing\n");
 474                 return -ENODEV;
 475         }
 476         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 477
 478         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 479               (int)priv->base, priv->max_hz);
 480
 481         return 0;
 482 }
 483
 484 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 485         .exec_op = ti_qspi_exec_mem_op,
 486 };
 487
 488 static const struct dm_spi_ops ti_qspi_ops = {
 489         .claim_bus      = ti_qspi_claim_bus,
 490         .release_bus    = ti_qspi_release_bus,
 491         .xfer           = ti_qspi_xfer,
 492         .set_speed      = ti_qspi_set_speed,
 493         .set_mode       = ti_qspi_set_mode,
 494         .mem_ops        = &ti_qspi_mem_ops,
 495 };
 496
 497 static const struct udevice_id ti_qspi_ids[] = {
 498         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 499         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 500         { }
 501 };
 502
 503 U_BOOT_DRIVER(ti_qspi) = {
 504         .name   = "ti_qspi",
 505         .id     = UCLASS_SPI,
 506         .of_match = ti_qspi_ids,
 507         .ops    = &ti_qspi_ops,
 508         .of_to_plat = ti_qspi_of_to_plat,
 509         .priv_auto      = sizeof(struct ti_qspi_priv),
 510         .probe  = ti_qspi_probe,
 511 };