4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
16 #include <asm/omap_gpio.h>
17 #include <asm/omap_common.h>
18 #include <asm/ti-common/ti-edma3.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* ti qpsi register bit masks */
23 #define QSPI_TIMEOUT 2000000
24 #define QSPI_FCLK 192000000
26 #define QSPI_CLK_EN BIT(31)
27 #define QSPI_CLK_DIV_MAX 0xffff
29 #define QSPI_EN_CS(n) (n << 28)
30 #define QSPI_WLEN(n) ((n-1) << 19)
31 #define QSPI_3_PIN BIT(18)
32 #define QSPI_RD_SNGL BIT(16)
33 #define QSPI_WR_SNGL (2 << 16)
34 #define QSPI_INVAL (4 << 16)
35 #define QSPI_RD_QUAD (7 << 16)
37 #define QSPI_DD(m, n) (m << (3 + n*8))
38 #define QSPI_CKPHA(n) (1 << (2 + n*8))
39 #define QSPI_CSPOL(n) (1 << (1 + n*8))
40 #define QSPI_CKPOL(n) (1 << (n*8))
42 #define QSPI_WC BIT(1)
43 #define QSPI_BUSY BIT(0)
44 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
45 #define QSPI_XFER_DONE QSPI_WC
46 #define MM_SWITCH 0x01
47 #define MEM_CS(cs) ((cs + 1) << 8)
48 #define MEM_CS_UNSELECT 0xfffff8ff
49 #define MMAP_START_ADDR_DRA 0x5c000000
50 #define MMAP_START_ADDR_AM43x 0x30000000
51 #define CORE_CTRL_IO 0x4a002558
53 #define QSPI_CMD_READ (0x3 << 0)
54 #define QSPI_CMD_READ_DUAL (0x6b << 0)
55 #define QSPI_CMD_READ_QUAD (0x6c << 0)
56 #define QSPI_CMD_READ_FAST (0x0b << 0)
57 #define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
58 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
59 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
60 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
61 #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
62 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
63 #define QSPI_CMD_WRITE (0x12 << 16)
64 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
66 /* ti qspi register set */
96 struct spi_slave slave;
102 struct ti_qspi_regs *base;
109 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
116 clk_div = (QSPI_FCLK / hz) - 1;
118 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
121 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
122 &priv->base->clk_ctrl);
124 /* assign clk_div values */
127 else if (clk_div > QSPI_CLK_DIV_MAX)
128 clk_div = QSPI_CLK_DIV_MAX;
131 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
134 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
136 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
137 /* dummy readl to ensure bus sync */
138 readl(&priv->base->cmd);
141 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
145 priv->dc |= QSPI_CKPHA(0);
147 priv->dc |= QSPI_CKPOL(0);
148 if (mode & SPI_CS_HIGH)
149 priv->dc |= QSPI_CSPOL(0);
154 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
156 writel(priv->dc, &priv->base->dc);
157 writel(0, &priv->base->cmd);
158 writel(0, &priv->base->data);
161 writel(priv->dc, &priv->base->dc);
166 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
168 writel(0, &priv->base->dc);
169 writel(0, &priv->base->cmd);
170 writel(0, &priv->base->data);
173 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
177 val = readl(ctrl_mod_mmap);
181 val &= MEM_CS_UNSELECT;
182 writel(val, ctrl_mod_mmap);
185 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
186 const void *dout, void *din, unsigned long flags,
189 uint words = bitlen >> 3; /* fixed 8-bit word length */
190 const uchar *txp = dout;
195 /* Setup mmap flags */
196 if (flags & SPI_XFER_MMAP) {
197 writel(MM_SWITCH, &priv->base->memswitch);
198 if (priv->ctrl_mod_mmap)
199 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
201 } else if (flags & SPI_XFER_MMAP_END) {
202 writel(~MM_SWITCH, &priv->base->memswitch);
203 if (priv->ctrl_mod_mmap)
204 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
212 debug("spi_xfer: Non byte aligned SPI transfer\n");
216 /* Setup command reg */
218 priv->cmd |= QSPI_WLEN(8);
219 priv->cmd |= QSPI_EN_CS(cs);
220 if (priv->mode & SPI_3WIRE)
221 priv->cmd |= QSPI_3_PIN;
224 /* FIXME: This delay is required for successfull
225 * completion of read/write/erase. Once its root
226 * caused, it will be remove from the driver.
233 debug("tx cmd %08x dc %08x data %02x\n",
234 priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
235 writel(*txp++, &priv->base->data);
236 writel(priv->cmd | QSPI_WR_SNGL,
238 status = readl(&priv->base->status);
239 timeout = QSPI_TIMEOUT;
240 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
242 printf("spi_xfer: TX timeout!\n");
245 status = readl(&priv->base->status);
247 debug("tx done, status %08x\n", status);
250 debug("rx cmd %08x dc %08x\n",
251 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
252 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
253 status = readl(&priv->base->status);
254 timeout = QSPI_TIMEOUT;
255 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
257 printf("spi_xfer: RX timeout!\n");
260 status = readl(&priv->base->status);
262 *rxp++ = readl(&priv->base->data);
263 debug("rx done, status %08x, read %02x\n",
268 /* Terminate frame */
269 if (flags & SPI_XFER_END)
270 ti_qspi_cs_deactivate(priv);
275 /* TODO: control from sf layer to here through dm-spi */
276 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
277 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
279 unsigned int addr = (unsigned int) (data);
280 unsigned int edma_slot_num = 1;
282 /* Invalidate the area, so no writeback into the RAM races with DMA */
283 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
285 /* enable edma3 clocks */
286 enable_edma3_clocks();
288 /* Call edma3 api to do actual DMA transfer */
289 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
291 /* disable edma3 clocks */
292 disable_edma3_clocks();
294 *((unsigned int *)offset) += len;
298 #ifndef CONFIG_DM_SPI
300 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
302 return container_of(slave, struct ti_qspi_priv, slave);
305 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
310 void spi_cs_activate(struct spi_slave *slave)
312 /* CS handled in xfer */
316 void spi_cs_deactivate(struct spi_slave *slave)
318 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
319 ti_qspi_cs_deactivate(priv);
327 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
331 #ifdef CONFIG_QSPI_QUAD_SUPPORT
332 struct spi_slave *slave = &priv->slave;
333 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
334 QSPI_SETUP0_NUM_D_BYTES_8_BITS |
335 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
336 QSPI_NUM_DUMMY_BITS);
337 slave->mode_rx = SPI_RX_QUAD;
339 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
340 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
341 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
345 writel(memval, &priv->base->setup0);
348 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
349 unsigned int max_hz, unsigned int mode)
351 struct ti_qspi_priv *priv;
354 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
355 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
358 priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
360 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
364 priv->base = (struct ti_qspi_regs *)QSPI_BASE;
366 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
367 priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
368 priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
370 priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
373 ti_spi_set_speed(priv, max_hz);
375 #ifdef CONFIG_TI_SPI_MMAP
376 ti_spi_setup_spi_register(priv);
382 void spi_free_slave(struct spi_slave *slave)
384 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
388 int spi_claim_bus(struct spi_slave *slave)
390 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
392 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
393 __ti_qspi_set_mode(priv, priv->mode);
394 return __ti_qspi_claim_bus(priv, priv->slave.cs);
396 void spi_release_bus(struct spi_slave *slave)
398 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
400 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
401 __ti_qspi_release_bus(priv);
404 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
405 void *din, unsigned long flags)
407 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
409 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
410 priv->slave.bus, priv->slave.cs, bitlen, flags);
411 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
414 #else /* CONFIG_DM_SPI */
416 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
417 struct spi_slave *slave,
421 u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
424 writel(0, &priv->base->setup0);
428 memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
432 memval |= QSPI_CMD_READ_QUAD;
433 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
434 memval |= QSPI_SETUP0_READ_QUAD;
435 slave->mode_rx = SPI_RX_QUAD;
438 memval |= QSPI_CMD_READ_DUAL;
439 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
440 memval |= QSPI_SETUP0_READ_DUAL;
443 memval |= QSPI_CMD_READ;
444 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
445 memval |= QSPI_SETUP0_READ_NORMAL;
449 writel(memval, &priv->base->setup0);
453 static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
455 struct ti_qspi_priv *priv = dev_get_priv(bus);
457 ti_spi_set_speed(priv, max_hz);
462 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
464 struct ti_qspi_priv *priv = dev_get_priv(bus);
465 return __ti_qspi_set_mode(priv, mode);
468 static int ti_qspi_claim_bus(struct udevice *dev)
470 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
471 struct spi_slave *slave = dev_get_parent_priv(dev);
472 struct ti_qspi_priv *priv;
476 priv = dev_get_priv(bus);
478 if (slave_plat->cs > priv->num_cs) {
479 debug("invalid qspi chip select\n");
483 __ti_qspi_setup_memorymap(priv, slave, true);
485 return __ti_qspi_claim_bus(priv, slave_plat->cs);
488 static int ti_qspi_release_bus(struct udevice *dev)
490 struct spi_slave *slave = dev_get_parent_priv(dev);
491 struct ti_qspi_priv *priv;
495 priv = dev_get_priv(bus);
497 __ti_qspi_setup_memorymap(priv, slave, false);
498 __ti_qspi_release_bus(priv);
503 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
504 const void *dout, void *din, unsigned long flags)
506 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
507 struct ti_qspi_priv *priv;
511 priv = dev_get_priv(bus);
513 if (slave->cs > priv->num_cs) {
514 debug("invalid qspi chip select\n");
518 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
521 static int ti_qspi_probe(struct udevice *bus)
523 /* Nothing to do in probe */
527 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
529 struct ti_qspi_priv *priv = dev_get_priv(bus);
530 const void *blob = gd->fdt_blob;
531 int node = bus->of_offset;
535 priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
537 priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
539 addr = dev_get_addr_index(bus, 2);
540 mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
541 priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
543 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
544 if (priv->max_hz < 0) {
545 debug("Error: Max frequency missing\n");
548 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
550 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
551 (int)priv->base, priv->max_hz);
556 static int ti_qspi_child_pre_probe(struct udevice *dev)
558 struct spi_slave *slave = dev_get_parent_priv(dev);
559 struct udevice *bus = dev_get_parent(dev);
560 struct ti_qspi_priv *priv = dev_get_priv(bus);
562 slave->memory_map = priv->memory_map;
566 static const struct dm_spi_ops ti_qspi_ops = {
567 .claim_bus = ti_qspi_claim_bus,
568 .release_bus = ti_qspi_release_bus,
569 .xfer = ti_qspi_xfer,
570 .set_speed = ti_qspi_set_speed,
571 .set_mode = ti_qspi_set_mode,
574 static const struct udevice_id ti_qspi_ids[] = {
575 { .compatible = "ti,dra7xxx-qspi" },
576 { .compatible = "ti,am4372-qspi" },
580 U_BOOT_DRIVER(ti_qspi) = {
583 .of_match = ti_qspi_ids,
585 .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
586 .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
587 .probe = ti_qspi_probe,
588 .child_pre_probe = ti_qspi_child_pre_probe,
590 #endif /* CONFIG_DM_SPI */