1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013, Texas Instruments, Incorporated
11 #include <asm/cache.h>
12 #include <asm/global_data.h>
14 #include <asm/arch/omap.h>
20 #include <asm/omap_gpio.h>
21 #include <asm/omap_common.h>
22 #include <asm/ti-common/ti-edma3.h>
23 #include <linux/bitops.h>
24 #include <linux/err.h>
25 #include <linux/kernel.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 /* ti qpsi register bit masks */
32 #define QSPI_TIMEOUT 2000000
33 /* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */
34 #define QSPI_FCLK (192000000 / 4)
35 #define QSPI_DRA7XX_FCLK 76800000
36 #define QSPI_WLEN_MAX_BITS 128
37 #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
38 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
40 #define QSPI_CLK_EN BIT(31)
41 #define QSPI_CLK_DIV_MAX 0xffff
43 #define QSPI_EN_CS(n) (n << 28)
44 #define QSPI_WLEN(n) ((n-1) << 19)
45 #define QSPI_3_PIN BIT(18)
46 #define QSPI_RD_SNGL BIT(16)
47 #define QSPI_WR_SNGL (2 << 16)
48 #define QSPI_INVAL (4 << 16)
49 #define QSPI_RD_QUAD (7 << 16)
51 #define QSPI_CKPHA(n) (1 << (2 + n*8))
52 #define QSPI_CSPOL(n) (1 << (1 + n*8))
53 #define QSPI_CKPOL(n) (1 << (n*8))
55 #define QSPI_WC BIT(1)
56 #define QSPI_BUSY BIT(0)
57 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
58 #define QSPI_XFER_DONE QSPI_WC
59 #define MM_SWITCH 0x01
60 #define MEM_CS(cs) ((cs + 1) << 8)
61 #define MEM_CS_UNSELECT 0xfffff8ff
63 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
64 #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
65 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
66 #define QSPI_SETUP0_ADDR_SHIFT (8)
67 #define QSPI_SETUP0_DBITS_SHIFT (10)
69 #define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
71 /* ti qspi register set */
104 struct ti_qspi_regs *base;
112 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
114 struct ti_qspi_priv *priv = dev_get_priv(bus);
120 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
122 /* truncate clk_div value to QSPI_CLK_DIV_MAX */
123 if (clk_div > QSPI_CLK_DIV_MAX)
124 clk_div = QSPI_CLK_DIV_MAX;
126 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
129 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
130 &priv->base->clk_ctrl);
131 /* enable SCLK and program the clk divider */
132 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
137 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
139 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
140 /* dummy readl to ensure bus sync */
141 readl(&priv->base->cmd);
144 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
148 val = readl(ctrl_mod_mmap);
152 val &= MEM_CS_UNSELECT;
153 writel(val, ctrl_mod_mmap);
156 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
157 const void *dout, void *din, unsigned long flags)
159 struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
160 struct ti_qspi_priv *priv;
162 uint words = bitlen >> 3; /* fixed 8-bit word length */
163 const uchar *txp = dout;
167 unsigned int cs = slave->cs;
170 priv = dev_get_priv(bus);
172 if (cs > priv->num_cs) {
173 debug("invalid qspi chip select\n");
181 debug("spi_xfer: Non byte aligned SPI transfer\n");
185 /* Setup command reg */
187 priv->cmd |= QSPI_WLEN(8);
188 priv->cmd |= QSPI_EN_CS(cs);
189 if (priv->mode & SPI_3WIRE)
190 priv->cmd |= QSPI_3_PIN;
199 if (words >= QSPI_WLEN_MAX_BYTES) {
200 u32 *txbuf = (u32 *)txp;
203 data = cpu_to_be32(*txbuf++);
204 writel(data, &priv->base->data3);
205 data = cpu_to_be32(*txbuf++);
206 writel(data, &priv->base->data2);
207 data = cpu_to_be32(*txbuf++);
208 writel(data, &priv->base->data1);
209 data = cpu_to_be32(*txbuf++);
210 writel(data, &priv->base->data);
211 cmd &= ~QSPI_WLEN_MASK;
212 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
213 xfer_len = QSPI_WLEN_MAX_BYTES;
215 writeb(*txp, &priv->base->data);
218 debug("tx cmd %08x dc %08x\n",
219 cmd | QSPI_WR_SNGL, priv->dc);
220 writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
221 status = readl(&priv->base->status);
222 timeout = QSPI_TIMEOUT;
223 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
225 printf("spi_xfer: TX timeout!\n");
228 status = readl(&priv->base->status);
231 debug("tx done, status %08x\n", status);
234 debug("rx cmd %08x dc %08x\n",
235 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
236 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
237 status = readl(&priv->base->status);
238 timeout = QSPI_TIMEOUT;
239 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
241 printf("spi_xfer: RX timeout!\n");
244 status = readl(&priv->base->status);
246 *rxp++ = readl(&priv->base->data);
248 debug("rx done, status %08x, read %02x\n",
254 /* Terminate frame */
255 if (flags & SPI_XFER_END)
256 ti_qspi_cs_deactivate(priv);
261 /* TODO: control from sf layer to here through dm-spi */
262 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
264 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
265 unsigned int addr = (unsigned int) (data);
266 unsigned int edma_slot_num = 1;
268 /* Invalidate the area, so no writeback into the RAM races with DMA */
269 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
271 /* enable edma3 clocks */
272 enable_edma3_clocks();
274 /* Call edma3 api to do actual DMA transfer */
275 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
277 /* disable edma3 clocks */
278 disable_edma3_clocks();
280 memcpy_fromio(data, offset, len);
283 *((unsigned int *)offset) += len;
286 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
287 u8 opcode, u8 data_nbits, u8 addr_width,
292 switch (data_nbits) {
294 memval |= QSPI_SETUP0_READ_QUAD;
297 memval |= QSPI_SETUP0_READ_DUAL;
300 memval |= QSPI_SETUP0_READ_NORMAL;
304 memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
305 dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
307 writel(memval, TI_QSPI_SETUP_REG(priv, cs));
310 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
312 struct ti_qspi_priv *priv = dev_get_priv(bus);
316 priv->dc |= QSPI_CKPHA(0);
318 priv->dc |= QSPI_CKPOL(0);
319 if (mode & SPI_CS_HIGH)
320 priv->dc |= QSPI_CSPOL(0);
325 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
326 const struct spi_mem_op *op)
328 struct dm_spi_slave_plat *slave_plat;
329 struct ti_qspi_priv *priv;
334 bus = slave->dev->parent;
335 priv = dev_get_priv(bus);
336 slave_plat = dev_get_parent_plat(slave->dev);
338 /* Only optimize read path. */
339 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
340 !op->addr.nbytes || op->addr.nbytes > 4)
343 /* Address exceeds MMIO window size, fall back to regular mode. */
345 if (from + op->data.nbytes > priv->mmap_size)
348 ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
349 op->data.buswidth, op->addr.nbytes,
352 ti_qspi_copy_mmap((void *)op->data.buf.in,
353 (void *)priv->memory_map + from, op->data.nbytes);
358 static int ti_qspi_claim_bus(struct udevice *dev)
360 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
361 struct ti_qspi_priv *priv;
365 priv = dev_get_priv(bus);
367 if (slave_plat->cs > priv->num_cs) {
368 debug("invalid qspi chip select\n");
372 writel(MM_SWITCH, &priv->base->memswitch);
373 if (priv->ctrl_mod_mmap)
374 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
375 slave_plat->cs, true);
377 writel(priv->dc, &priv->base->dc);
378 writel(0, &priv->base->cmd);
379 writel(0, &priv->base->data);
381 priv->dc <<= slave_plat->cs * 8;
382 writel(priv->dc, &priv->base->dc);
387 static int ti_qspi_release_bus(struct udevice *dev)
389 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
390 struct ti_qspi_priv *priv;
394 priv = dev_get_priv(bus);
396 writel(~MM_SWITCH, &priv->base->memswitch);
397 if (priv->ctrl_mod_mmap)
398 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
399 slave_plat->cs, false);
401 writel(0, &priv->base->dc);
402 writel(0, &priv->base->cmd);
403 writel(0, &priv->base->data);
404 writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
409 static int ti_qspi_probe(struct udevice *bus)
411 struct ti_qspi_priv *priv = dev_get_priv(bus);
413 priv->fclk = dev_get_driver_data(bus);
418 static void *map_syscon_chipselects(struct udevice *bus)
420 #if CONFIG_IS_ENABLED(SYSCON)
421 struct udevice *syscon;
422 struct regmap *regmap;
426 err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
427 "syscon-chipselects", &syscon);
429 debug("%s: unable to find syscon device (%d)\n", __func__,
434 regmap = syscon_get_regmap(syscon);
435 if (IS_ERR(regmap)) {
436 debug("%s: unable to find regmap (%ld)\n", __func__,
441 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
442 "syscon-chipselects", &len);
443 if (len < 2*sizeof(fdt32_t)) {
444 debug("%s: offset not available\n", __func__);
448 return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
451 addr = devfdt_get_addr_index(bus, 2);
452 return (addr == FDT_ADDR_T_NONE) ? NULL :
453 map_physmem(addr, 0, MAP_NOCACHE);
457 static int ti_qspi_of_to_plat(struct udevice *bus)
459 struct ti_qspi_priv *priv = dev_get_priv(bus);
460 const void *blob = gd->fdt_blob;
461 int node = dev_of_offset(bus);
462 fdt_addr_t mmap_addr;
463 fdt_addr_t mmap_size;
465 priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
466 priv->base = map_physmem(dev_read_addr(bus),
467 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
468 mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
469 priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
470 priv->mmap_size = mmap_size;
472 priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
474 debug("Error: Max frequency missing\n");
477 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
479 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
480 (int)priv->base, priv->max_hz);
485 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
486 .exec_op = ti_qspi_exec_mem_op,
489 static const struct dm_spi_ops ti_qspi_ops = {
490 .claim_bus = ti_qspi_claim_bus,
491 .release_bus = ti_qspi_release_bus,
492 .xfer = ti_qspi_xfer,
493 .set_speed = ti_qspi_set_speed,
494 .set_mode = ti_qspi_set_mode,
495 .mem_ops = &ti_qspi_mem_ops,
498 static const struct udevice_id ti_qspi_ids[] = {
499 { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
500 { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
504 U_BOOT_DRIVER(ti_qspi) = {
507 .of_match = ti_qspi_ids,
509 .of_to_plat = ti_qspi_of_to_plat,
510 .priv_auto = sizeof(struct ti_qspi_priv),
511 .probe = ti_qspi_probe,