1 // SPDX-License-Identifier: GPL-2.0
3 * NVIDIA Tegra SPI-SLINK controller
5 * Copyright (c) 2010-2013 NVIDIA Corporation
13 #include <asm/arch/clock.h>
14 #include <asm/arch-tegra/clk_rst.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include "tegra_spi.h"
21 DECLARE_GLOBAL_DATA_PTR;
24 #define SLINK_CMD_ENB BIT(31)
25 #define SLINK_CMD_GO BIT(30)
26 #define SLINK_CMD_M_S BIT(28)
27 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
28 #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
29 #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
30 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
31 #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
32 #define SLINK_CMD_CK_SDA BIT(21)
33 #define SLINK_CMD_CS_POL BIT(13)
34 #define SLINK_CMD_CS_VAL BIT(12)
35 #define SLINK_CMD_CS_SOFT BIT(11)
36 #define SLINK_CMD_BIT_LENGTH BIT(4)
37 #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
39 #define SLINK_CMD2_TXEN BIT(30)
40 #define SLINK_CMD2_RXEN BIT(31)
41 #define SLINK_CMD2_SS_EN BIT(18)
42 #define SLINK_CMD2_SS_EN_SHIFT 18
43 #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18)
44 #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17)
46 #define SLINK_STAT_BSY BIT(31)
47 #define SLINK_STAT_RDY BIT(30)
48 #define SLINK_STAT_ERR BIT(29)
49 #define SLINK_STAT_RXF_FLUSH BIT(27)
50 #define SLINK_STAT_TXF_FLUSH BIT(26)
51 #define SLINK_STAT_RXF_OVF BIT(25)
52 #define SLINK_STAT_TXF_UNR BIT(24)
53 #define SLINK_STAT_RXF_EMPTY BIT(23)
54 #define SLINK_STAT_RXF_FULL BIT(22)
55 #define SLINK_STAT_TXF_EMPTY BIT(21)
56 #define SLINK_STAT_TXF_FULL BIT(20)
57 #define SLINK_STAT_TXF_OVF BIT(19)
58 #define SLINK_STAT_RXF_UNR BIT(18)
59 #define SLINK_STAT_CUR_BLKCNT BIT(15)
61 #define SLINK_STAT2_RXF_FULL_CNT BIT(16)
62 #define SLINK_STAT2_TXF_FULL_CNT BIT(0)
64 #define SPI_TIMEOUT 1000
65 #define TEGRA_SPI_MAX_FREQ 52000000
68 u32 command; /* SLINK_COMMAND_0 register */
69 u32 command2; /* SLINK_COMMAND2_0 reg */
70 u32 status; /* SLINK_STATUS_0 register */
71 u32 reserved; /* Reserved offset 0C */
72 u32 mas_data; /* SLINK_MAS_DATA_0 reg */
73 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
74 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
75 u32 status2; /* SLINK_STATUS2_0 reg */
76 u32 rsvd[56]; /* 0x20 to 0xFF reserved */
77 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
78 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
79 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
82 struct tegra30_spi_priv {
83 struct spi_regs *regs;
88 int last_transaction_us;
91 struct tegra_spi_slave {
92 struct spi_slave slave;
93 struct tegra30_spi_priv *ctrl;
96 static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
98 struct tegra_spi_platdata *plat = bus->platdata;
99 const void *blob = gd->fdt_blob;
100 int node = dev_of_offset(bus);
102 plat->base = dev_read_addr(bus);
103 plat->periph_id = clock_decode_periph_id(bus);
105 if (plat->periph_id == PERIPH_ID_NONE) {
106 debug("%s: could not decode periph id %d\n", __func__,
108 return -FDT_ERR_NOTFOUND;
111 /* Use 500KHz as a suitable default */
112 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
114 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
115 "spi-deactivate-delay", 0);
116 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
117 __func__, plat->base, plat->periph_id, plat->frequency,
118 plat->deactivate_delay_us);
123 static int tegra30_spi_probe(struct udevice *bus)
125 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
126 struct tegra30_spi_priv *priv = dev_get_priv(bus);
128 priv->regs = (struct spi_regs *)plat->base;
130 priv->last_transaction_us = timer_get_us();
131 priv->freq = plat->frequency;
132 priv->periph_id = plat->periph_id;
134 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
135 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
141 static int tegra30_spi_claim_bus(struct udevice *dev)
143 struct udevice *bus = dev->parent;
144 struct tegra30_spi_priv *priv = dev_get_priv(bus);
145 struct spi_regs *regs = priv->regs;
148 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
149 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
152 /* Clear stale status here */
153 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
154 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
155 writel(reg, ®s->status);
156 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
158 /* Set master mode and sw controlled CS */
159 reg = readl(®s->command);
160 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
161 writel(reg, ®s->command);
162 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
167 static void spi_cs_activate(struct udevice *dev)
169 struct udevice *bus = dev->parent;
170 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
171 struct tegra30_spi_priv *priv = dev_get_priv(bus);
173 /* If it's too soon to do another transaction, wait */
174 if (pdata->deactivate_delay_us &&
175 priv->last_transaction_us) {
176 ulong delay_us; /* The delay completed so far */
177 delay_us = timer_get_us() - priv->last_transaction_us;
178 if (delay_us < pdata->deactivate_delay_us)
179 udelay(pdata->deactivate_delay_us - delay_us);
182 /* CS is negated on Tegra, so drive a 1 to get a 0 */
183 setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
186 static void spi_cs_deactivate(struct udevice *dev)
188 struct udevice *bus = dev->parent;
189 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
190 struct tegra30_spi_priv *priv = dev_get_priv(bus);
192 /* CS is negated on Tegra, so drive a 0 to get a 1 */
193 clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
195 /* Remember time of this transaction so we can honour the bus delay */
196 if (pdata->deactivate_delay_us)
197 priv->last_transaction_us = timer_get_us();
200 static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
201 const void *data_out, void *data_in,
204 struct udevice *bus = dev->parent;
205 struct tegra30_spi_priv *priv = dev_get_priv(bus);
206 struct spi_regs *regs = priv->regs;
207 u32 reg, tmpdout, tmpdin = 0;
208 const u8 *dout = data_out;
213 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
214 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
217 num_bytes = bitlen / 8;
221 reg = readl(®s->status);
222 writel(reg, ®s->status); /* Clear all SPI events via R/W */
223 debug("%s entry: STATUS = %08x\n", __func__, reg);
225 reg = readl(®s->status2);
226 writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */
227 debug("%s entry: STATUS2 = %08x\n", __func__, reg);
229 debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command));
231 clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
232 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
233 (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
234 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
236 if (flags & SPI_XFER_BEGIN)
237 spi_cs_activate(dev);
239 /* handle data in 32-bit chunks */
240 while (num_bytes > 0) {
246 bytes = (num_bytes > 4) ? 4 : num_bytes;
249 for (i = 0; i < bytes; ++i)
250 tmpdout = (tmpdout << 8) | dout[i];
256 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK,
258 writel(tmpdout, ®s->tx_fifo);
259 setbits_le32(®s->command, SLINK_CMD_GO);
262 * Wait for SPI transmit FIFO to empty, or to time out.
263 * The RX FIFO status will be read and cleared last
265 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
268 status = readl(®s->status);
270 /* We can exit when we've had both RX and TX activity */
271 if (is_read && (status & SLINK_STAT_TXF_EMPTY))
274 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
278 else if (!(status & SLINK_STAT_RXF_EMPTY)) {
279 tmpdin = readl(®s->rx_fifo);
282 /* swap bytes read in */
284 for (i = bytes - 1; i >= 0; --i) {
285 din[i] = tmpdin & 0xff;
293 if (tm >= SPI_TIMEOUT)
296 /* clear ACK RDY, etc. bits */
297 writel(readl(®s->status), ®s->status);
300 if (flags & SPI_XFER_END)
301 spi_cs_deactivate(dev);
303 debug("%s: transfer ended. Value=%08x, status = %08x\n",
304 __func__, tmpdin, readl(®s->status));
307 printf("%s: timeout during SPI transfer, tm %d\n",
315 static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
317 struct tegra_spi_platdata *plat = bus->platdata;
318 struct tegra30_spi_priv *priv = dev_get_priv(bus);
320 if (speed > plat->frequency)
321 speed = plat->frequency;
323 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
328 static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
330 struct tegra30_spi_priv *priv = dev_get_priv(bus);
331 struct spi_regs *regs = priv->regs;
334 reg = readl(®s->command);
336 /* Set CPOL and CPHA */
337 reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
339 reg |= SLINK_CMD_CK_SDA;
342 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
344 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
346 writel(reg, ®s->command);
349 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
354 static const struct dm_spi_ops tegra30_spi_ops = {
355 .claim_bus = tegra30_spi_claim_bus,
356 .xfer = tegra30_spi_xfer,
357 .set_speed = tegra30_spi_set_speed,
358 .set_mode = tegra30_spi_set_mode,
360 * cs_info is not needed, since we require all chip selects to be
361 * in the device tree explicitly
365 static const struct udevice_id tegra30_spi_ids[] = {
366 { .compatible = "nvidia,tegra20-slink" },
370 U_BOOT_DRIVER(tegra30_spi) = {
371 .name = "tegra20_slink",
373 .of_match = tegra30_spi_ids,
374 .ops = &tegra30_spi_ops,
375 .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
376 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
377 .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
378 .probe = tegra30_spi_probe,