drivers/spi/sun4i_spi.c

   1 /*
   2  * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
   3  * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
   4  * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
   5  *
   6  * (C) Copyright 2017 Olimex Ltd..
   7  * Stefan Mavrodiev <stefan@olimex.com>
   8  *
   9  * Based on linux spi driver. Original copyright follows:
  10  * linux/drivers/spi/spi-sun4i.c
  11  *
  12  * Copyright (C) 2012 - 2014 Allwinner Tech
  13  * Pan Nan <pannan@allwinnertech.com>
  14  *
  15  * Copyright (C) 2014 Maxime Ripard
  16  * Maxime Ripard <maxime.ripard@free-electrons.com>
  17  *
  18  * SPDX-License-Identifier:     GPL-2.0+
  19  */
  20
  21 #include <common.h>
  22 #include <dm.h>
  23 #include <spi.h>
  24 #include <errno.h>
  25 #include <fdt_support.h>
  26 #include <wait_bit.h>
  27
  28 #include <asm/bitops.h>
  29 #include <asm/gpio.h>
  30 #include <asm/io.h>
  31
  32 #include <asm/arch/clock.h>
  33
  34 #define SUN4I_FIFO_DEPTH        64
  35
  36 #define SUN4I_RXDATA_REG        0x00
  37
  38 #define SUN4I_TXDATA_REG        0x04
  39
  40 #define SUN4I_CTL_REG           0x08
  41 #define SUN4I_CTL_ENABLE                BIT(0)
  42 #define SUN4I_CTL_MASTER                BIT(1)
  43 #define SUN4I_CTL_CPHA                  BIT(2)
  44 #define SUN4I_CTL_CPOL                  BIT(3)
  45 #define SUN4I_CTL_CS_ACTIVE_LOW         BIT(4)
  46 #define SUN4I_CTL_LMTF                  BIT(6)
  47 #define SUN4I_CTL_TF_RST                BIT(8)
  48 #define SUN4I_CTL_RF_RST                BIT(9)
  49 #define SUN4I_CTL_XCH_MASK              0x0400
  50 #define SUN4I_CTL_XCH                   BIT(10)
  51 #define SUN4I_CTL_CS_MASK               0x3000
  52 #define SUN4I_CTL_CS(cs)                (((cs) << 12) & SUN4I_CTL_CS_MASK)
  53 #define SUN4I_CTL_DHB                   BIT(15)
  54 #define SUN4I_CTL_CS_MANUAL             BIT(16)
  55 #define SUN4I_CTL_CS_LEVEL              BIT(17)
  56 #define SUN4I_CTL_TP                    BIT(18)
  57
  58 #define SUN4I_INT_CTL_REG       0x0c
  59 #define SUN4I_INT_CTL_RF_F34            BIT(4)
  60 #define SUN4I_INT_CTL_TF_E34            BIT(12)
  61 #define SUN4I_INT_CTL_TC                BIT(16)
  62
  63 #define SUN4I_INT_STA_REG       0x10
  64
  65 #define SUN4I_DMA_CTL_REG       0x14
  66
  67 #define SUN4I_WAIT_REG          0x18
  68
  69 #define SUN4I_CLK_CTL_REG       0x1c
  70 #define SUN4I_CLK_CTL_CDR2_MASK         0xff
  71 #define SUN4I_CLK_CTL_CDR2(div)         ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  72 #define SUN4I_CLK_CTL_CDR1_MASK         0xf
  73 #define SUN4I_CLK_CTL_CDR1(div)         (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  74 #define SUN4I_CLK_CTL_DRS               BIT(12)
  75
  76 #define SUN4I_MAX_XFER_SIZE             0xffffff
  77
  78 #define SUN4I_BURST_CNT_REG     0x20
  79 #define SUN4I_BURST_CNT(cnt)            ((cnt) & SUN4I_MAX_XFER_SIZE)
  80
  81 #define SUN4I_XMIT_CNT_REG      0x24
  82 #define SUN4I_XMIT_CNT(cnt)             ((cnt) & SUN4I_MAX_XFER_SIZE)
  83
  84 #define SUN4I_FIFO_STA_REG      0x28
  85 #define SUN4I_FIFO_STA_RF_CNT_MASK      0x7f
  86 #define SUN4I_FIFO_STA_RF_CNT_BITS      0
  87 #define SUN4I_FIFO_STA_TF_CNT_MASK      0x7f
  88 #define SUN4I_FIFO_STA_TF_CNT_BITS      16
  89
  90 #define SUN4I_SPI_MAX_RATE      24000000
  91 #define SUN4I_SPI_MIN_RATE      3000
  92 #define SUN4I_SPI_DEFAULT_RATE  1000000
  93 #define SUN4I_SPI_TIMEOUT_US    1000000
  94
  95 /* sun4i spi register set */
  96 struct sun4i_spi_regs {
  97         u32 rxdata;
  98         u32 txdata;
  99         u32 ctl;
 100         u32 intctl;
 101         u32 st;
 102         u32 dmactl;
 103         u32 wait;
 104         u32 cctl;
 105         u32 bc;
 106         u32 tc;
 107         u32 fifo_sta;
 108 };
 109
 110 struct sun4i_spi_platdata {
 111         u32 base_addr;
 112         u32 max_hz;
 113 };
 114
 115 struct sun4i_spi_priv {
 116         struct sun4i_spi_regs *regs;
 117         u32 freq;
 118         u32 mode;
 119
 120         const u8 *tx_buf;
 121         u8 *rx_buf;
 122 };
 123
 124 DECLARE_GLOBAL_DATA_PTR;
 125
 126 static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
 127 {
 128         u8 byte;
 129
 130         while (len--) {
 131                 byte = readb(&priv->regs->rxdata);
 132                 *priv->rx_buf++ = byte;
 133         }
 134 }
 135
 136 static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
 137 {
 138         u8 byte;
 139
 140         while (len--) {
 141                 byte = priv->tx_buf ? *priv->tx_buf++ : 0;
 142                 writeb(byte, &priv->regs->txdata);
 143         }
 144 }
 145
 146 static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
 147 {
 148         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 149         u32 reg;
 150
 151         reg = readl(&priv->regs->ctl);
 152
 153         reg &= ~SUN4I_CTL_CS_MASK;
 154         reg |= SUN4I_CTL_CS(cs);
 155
 156         if (enable)
 157                 reg &= ~SUN4I_CTL_CS_LEVEL;
 158         else
 159                 reg |= SUN4I_CTL_CS_LEVEL;
 160
 161         writel(reg, &priv->regs->ctl);
 162 }
 163
 164 static int sun4i_spi_parse_pins(struct udevice *dev)
 165 {
 166         const void *fdt = gd->fdt_blob;
 167         const char *pin_name;
 168         const fdt32_t *list;
 169         u32 phandle;
 170         int drive, pull = 0, pin, i;
 171         int offset;
 172         int size;
 173
 174         list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
 175         if (!list) {
 176                 printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
 177                 return -EINVAL;
 178         }
 179
 180         while (size) {
 181                 phandle = fdt32_to_cpu(*list++);
 182                 size -= sizeof(*list);
 183
 184                 offset = fdt_node_offset_by_phandle(fdt, phandle);
 185                 if (offset < 0)
 186                         return offset;
 187
 188                 drive = fdt_getprop_u32_default_node(fdt, offset, 0,
 189                                                      "drive-strength", 0);
 190                 if (drive) {
 191                         if (drive <= 10)
 192                                 drive = 0;
 193                         else if (drive <= 20)
 194                                 drive = 1;
 195                         else if (drive <= 30)
 196                                 drive = 2;
 197                         else
 198                                 drive = 3;
 199                 } else {
 200                         drive = fdt_getprop_u32_default_node(fdt, offset, 0,
 201                                                              "allwinner,drive",
 202                                                               0);
 203                         drive = min(drive, 3);
 204                 }
 205
 206                 if (fdt_get_property(fdt, offset, "bias-disable", NULL))
 207                         pull = 0;
 208                 else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
 209                         pull = 1;
 210                 else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
 211                         pull = 2;
 212                 else
 213                         pull = fdt_getprop_u32_default_node(fdt, offset, 0,
 214                                                             "allwinner,pull",
 215                                                              0);
 216                 pull = min(pull, 2);
 217
 218                 for (i = 0; ; i++) {
 219                         pin_name = fdt_stringlist_get(fdt, offset,
 220                                                       "pins", i, NULL);
 221                         if (!pin_name) {
 222                                 pin_name = fdt_stringlist_get(fdt, offset,
 223                                                               "allwinner,pins",
 224                                                                i, NULL);
 225                                 if (!pin_name)
 226                                         break;
 227                         }
 228
 229                         pin = name_to_gpio(pin_name);
 230                         if (pin < 0)
 231                                 break;
 232
 233                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
 234                         sunxi_gpio_set_drv(pin, drive);
 235                         sunxi_gpio_set_pull(pin, pull);
 236                 }
 237         }
 238         return 0;
 239 }
 240
 241 static inline void sun4i_spi_enable_clock(void)
 242 {
 243         struct sunxi_ccm_reg *const ccm =
 244                 (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
 245
 246         setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
 247         writel((1 << 31), &ccm->spi0_clk_cfg);
 248 }
 249
 250 static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
 251 {
 252         struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
 253         int node = dev_of_offset(bus);
 254
 255         plat->base_addr = devfdt_get_addr(bus);
 256         plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
 257                                       "spi-max-frequency",
 258                                       SUN4I_SPI_DEFAULT_RATE);
 259
 260         if (plat->max_hz > SUN4I_SPI_MAX_RATE)
 261                 plat->max_hz = SUN4I_SPI_MAX_RATE;
 262
 263         return 0;
 264 }
 265
 266 static int sun4i_spi_probe(struct udevice *bus)
 267 {
 268         struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
 269         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 270
 271         sun4i_spi_enable_clock();
 272         sun4i_spi_parse_pins(bus);
 273
 274         priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;
 275         priv->freq = plat->max_hz;
 276
 277         return 0;
 278 }
 279
 280 static int sun4i_spi_claim_bus(struct udevice *dev)
 281 {
 282         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 283
 284         writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
 285                SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW,
 286                &priv->regs->ctl);
 287         return 0;
 288 }
 289
 290 static int sun4i_spi_release_bus(struct udevice *dev)
 291 {
 292         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 293         u32 reg;
 294
 295         reg = readl(&priv->regs->ctl);
 296         reg &= ~SUN4I_CTL_ENABLE;
 297         writel(reg, &priv->regs->ctl);
 298
 299         return 0;
 300 }
 301
 302 static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 303                           const void *dout, void *din, unsigned long flags)
 304 {
 305         struct udevice *bus = dev->parent;
 306         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 307         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 308
 309         u32 len = bitlen / 8;
 310         u32 reg;
 311         u8 nbytes;
 312         int ret;
 313
 314         priv->tx_buf = dout;
 315         priv->rx_buf = din;
 316
 317         if (bitlen % 8) {
 318                 debug("%s: non byte-aligned SPI transfer.\n", __func__);
 319                 return -ENAVAIL;
 320         }
 321
 322         if (flags & SPI_XFER_BEGIN)
 323                 sun4i_spi_set_cs(bus, slave_plat->cs, true);
 324
 325         reg = readl(&priv->regs->ctl);
 326
 327         /* Reset FIFOs */
 328         writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);
 329
 330         while (len) {
 331                 /* Setup the transfer now... */
 332                 nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));
 333
 334                 /* Setup the counters */
 335                 writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
 336                 writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);
 337
 338                 /* Fill the TX FIFO */
 339                 sun4i_spi_fill_fifo(priv, nbytes);
 340
 341                 /* Start the transfer */
 342                 reg = readl(&priv->regs->ctl);
 343                 writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
 344
 345                 /* Wait transfer to complete */
 346                 ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
 347                                         false, SUN4I_SPI_TIMEOUT_US, false);
 348                 if (ret) {
 349                         printf("ERROR: sun4i_spi: Timeout transferring data\n");
 350                         sun4i_spi_set_cs(bus, slave_plat->cs, false);
 351                         return ret;
 352                 }
 353
 354                 /* Drain the RX FIFO */
 355                 sun4i_spi_drain_fifo(priv, nbytes);
 356
 357                 len -= nbytes;
 358         }
 359
 360         if (flags & SPI_XFER_END)
 361                 sun4i_spi_set_cs(bus, slave_plat->cs, false);
 362
 363         return 0;
 364 }
 365
 366 static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
 367 {
 368         struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
 369         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 370         unsigned int div;
 371         u32 reg;
 372
 373         if (speed > plat->max_hz)
 374                 speed = plat->max_hz;
 375
 376         if (speed < SUN4I_SPI_MIN_RATE)
 377                 speed = SUN4I_SPI_MIN_RATE;
 378         /*
 379          * Setup clock divider.
 380          *
 381          * We have two choices there. Either we can use the clock
 382          * divide rate 1, which is calculated thanks to this formula:
 383          * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
 384          * Or we can use CDR2, which is calculated with the formula:
 385          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 386          * Whether we use the former or the latter is set through the
 387          * DRS bit.
 388          *
 389          * First try CDR2, and if we can't reach the expected
 390          * frequency, fall back to CDR1.
 391          */
 392
 393         div = SUN4I_SPI_MAX_RATE / (2 * speed);
 394         reg = readl(&priv->regs->cctl);
 395
 396         if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
 397                 if (div > 0)
 398                         div--;
 399
 400                 reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
 401                 reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
 402         } else {
 403                 div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
 404                 reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
 405                 reg |= SUN4I_CLK_CTL_CDR1(div);
 406         }
 407
 408         priv->freq = speed;
 409         writel(reg, &priv->regs->cctl);
 410
 411         return 0;
 412 }
 413
 414 static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
 415 {
 416         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 417         u32 reg;
 418
 419         reg = readl(&priv->regs->ctl);
 420         reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA);
 421
 422         if (mode & SPI_CPOL)
 423                 reg |= SUN4I_CTL_CPOL;
 424
 425         if (mode & SPI_CPHA)
 426                 reg |= SUN4I_CTL_CPHA;
 427
 428         priv->mode = mode;
 429         writel(reg, &priv->regs->ctl);
 430
 431         return 0;
 432 }
 433
 434 static const struct dm_spi_ops sun4i_spi_ops = {
 435         .claim_bus              = sun4i_spi_claim_bus,
 436         .release_bus            = sun4i_spi_release_bus,
 437         .xfer                   = sun4i_spi_xfer,
 438         .set_speed              = sun4i_spi_set_speed,
 439         .set_mode               = sun4i_spi_set_mode,
 440 };
 441
 442 static const struct udevice_id sun4i_spi_ids[] = {
 443         { .compatible = "allwinner,sun4i-a10-spi"  },
 444         { }
 445 };
 446
 447 U_BOOT_DRIVER(sun4i_spi) = {
 448         .name   = "sun4i_spi",
 449         .id     = UCLASS_SPI,
 450         .of_match       = sun4i_spi_ids,
 451         .ops    = &sun4i_spi_ops,
 452         .ofdata_to_platdata     = sun4i_spi_ofdata_to_platdata,
 453         .platdata_auto_alloc_size       = sizeof(struct sun4i_spi_platdata),
 454         .priv_auto_alloc_size   = sizeof(struct sun4i_spi_priv),
 455         .probe  = sun4i_spi_probe,
 456 };