drivers/spi/sun4i_spi.c

   1 /*
   2  * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
   3  * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
   4  * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
   5  *
   6  * (C) Copyright 2017 Olimex Ltd..
   7  * Stefan Mavrodiev <stefan@olimex.com>
   8  *
   9  * Based on linux spi driver. Original copyright follows:
  10  * linux/drivers/spi/spi-sun4i.c
  11  *
  12  * Copyright (C) 2012 - 2014 Allwinner Tech
  13  * Pan Nan <pannan@allwinnertech.com>
  14  *
  15  * Copyright (C) 2014 Maxime Ripard
  16  * Maxime Ripard <maxime.ripard@free-electrons.com>
  17  *
  18  * SPDX-License-Identifier:     GPL-2.0+
  19  */
  20
  21 #include <common.h>
  22 #include <dm.h>
  23 #include <spi.h>
  24 #include <errno.h>
  25 #include <fdt_support.h>
  26 #include <wait_bit.h>
  27
  28 #include <asm/bitops.h>
  29 #include <asm/gpio.h>
  30 #include <asm/io.h>
  31
  32 #include <asm/arch/clock.h>
  33
  34 #define SUN4I_FIFO_DEPTH        64
  35
  36 #define SUN4I_RXDATA_REG        0x00
  37
  38 #define SUN4I_TXDATA_REG        0x04
  39
  40 #define SUN4I_CTL_REG           0x08
  41 #define SUN4I_CTL_ENABLE                BIT(0)
  42 #define SUN4I_CTL_MASTER                BIT(1)
  43 #define SUN4I_CTL_CPHA                  BIT(2)
  44 #define SUN4I_CTL_CPOL                  BIT(3)
  45 #define SUN4I_CTL_CS_ACTIVE_LOW         BIT(4)
  46 #define SUN4I_CTL_LMTF                  BIT(6)
  47 #define SUN4I_CTL_TF_RST                BIT(8)
  48 #define SUN4I_CTL_RF_RST                BIT(9)
  49 #define SUN4I_CTL_XCH_MASK              0x0400
  50 #define SUN4I_CTL_XCH                   BIT(10)
  51 #define SUN4I_CTL_CS_MASK               0x3000
  52 #define SUN4I_CTL_CS(cs)                (((cs) << 12) & SUN4I_CTL_CS_MASK)
  53 #define SUN4I_CTL_DHB                   BIT(15)
  54 #define SUN4I_CTL_CS_MANUAL             BIT(16)
  55 #define SUN4I_CTL_CS_LEVEL              BIT(17)
  56 #define SUN4I_CTL_TP                    BIT(18)
  57
  58 #define SUN4I_INT_CTL_REG       0x0c
  59 #define SUN4I_INT_CTL_RF_F34            BIT(4)
  60 #define SUN4I_INT_CTL_TF_E34            BIT(12)
  61 #define SUN4I_INT_CTL_TC                BIT(16)
  62
  63 #define SUN4I_INT_STA_REG       0x10
  64
  65 #define SUN4I_DMA_CTL_REG       0x14
  66
  67 #define SUN4I_WAIT_REG          0x18
  68
  69 #define SUN4I_CLK_CTL_REG       0x1c
  70 #define SUN4I_CLK_CTL_CDR2_MASK         0xff
  71 #define SUN4I_CLK_CTL_CDR2(div)         ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  72 #define SUN4I_CLK_CTL_CDR1_MASK         0xf
  73 #define SUN4I_CLK_CTL_CDR1(div)         (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  74 #define SUN4I_CLK_CTL_DRS               BIT(12)
  75
  76 #define SUN4I_MAX_XFER_SIZE             0xffffff
  77
  78 #define SUN4I_BURST_CNT_REG     0x20
  79 #define SUN4I_BURST_CNT(cnt)            ((cnt) & SUN4I_MAX_XFER_SIZE)
  80
  81 #define SUN4I_XMIT_CNT_REG      0x24
  82 #define SUN4I_XMIT_CNT(cnt)             ((cnt) & SUN4I_MAX_XFER_SIZE)
  83
  84 #define SUN4I_FIFO_STA_REG      0x28
  85 #define SUN4I_FIFO_STA_RF_CNT_MASK      0x7f
  86 #define SUN4I_FIFO_STA_RF_CNT_BITS      0
  87 #define SUN4I_FIFO_STA_TF_CNT_MASK      0x7f
  88 #define SUN4I_FIFO_STA_TF_CNT_BITS      16
  89
  90 #define SUN4I_SPI_MAX_RATE      24000000
  91 #define SUN4I_SPI_MIN_RATE      3000
  92 #define SUN4I_SPI_DEFAULT_RATE  1000000
  93 #define SUN4I_SPI_TIMEOUT_US    1000000
  94
  95 /* sun4i spi register set */
  96 struct sun4i_spi_regs {
  97         u32 rxdata;
  98         u32 txdata;
  99         u32 ctl;
 100         u32 intctl;
 101         u32 st;
 102         u32 dmactl;
 103         u32 wait;
 104         u32 cctl;
 105         u32 bc;
 106         u32 tc;
 107         u32 fifo_sta;
 108 };
 109
 110 struct sun4i_spi_platdata {
 111         u32 base_addr;
 112         u32 max_hz;
 113 };
 114
 115 struct sun4i_spi_priv {
 116         struct sun4i_spi_regs *regs;
 117         u32 freq;
 118         u32 mode;
 119
 120         const u8 *tx_buf;
 121         u8 *rx_buf;
 122 };
 123
 124 DECLARE_GLOBAL_DATA_PTR;
 125
 126 static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
 127 {
 128         u8 byte;
 129
 130         while (len--) {
 131                 byte = readb(&priv->regs->rxdata);
 132                 if (priv->rx_buf)
 133                         *priv->rx_buf++ = byte;
 134         }
 135 }
 136
 137 static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
 138 {
 139         u8 byte;
 140
 141         while (len--) {
 142                 byte = priv->tx_buf ? *priv->tx_buf++ : 0;
 143                 writeb(byte, &priv->regs->txdata);
 144         }
 145 }
 146
 147 static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
 148 {
 149         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 150         u32 reg;
 151
 152         reg = readl(&priv->regs->ctl);
 153
 154         reg &= ~SUN4I_CTL_CS_MASK;
 155         reg |= SUN4I_CTL_CS(cs);
 156
 157         if (enable)
 158                 reg &= ~SUN4I_CTL_CS_LEVEL;
 159         else
 160                 reg |= SUN4I_CTL_CS_LEVEL;
 161
 162         writel(reg, &priv->regs->ctl);
 163 }
 164
 165 static int sun4i_spi_parse_pins(struct udevice *dev)
 166 {
 167         const void *fdt = gd->fdt_blob;
 168         const char *pin_name;
 169         const fdt32_t *list;
 170         u32 phandle;
 171         int drive, pull = 0, pin, i;
 172         int offset;
 173         int size;
 174
 175         list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
 176         if (!list) {
 177                 printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
 178                 return -EINVAL;
 179         }
 180
 181         while (size) {
 182                 phandle = fdt32_to_cpu(*list++);
 183                 size -= sizeof(*list);
 184
 185                 offset = fdt_node_offset_by_phandle(fdt, phandle);
 186                 if (offset < 0)
 187                         return offset;
 188
 189                 drive = fdt_getprop_u32_default_node(fdt, offset, 0,
 190                                                      "drive-strength", 0);
 191                 if (drive) {
 192                         if (drive <= 10)
 193                                 drive = 0;
 194                         else if (drive <= 20)
 195                                 drive = 1;
 196                         else if (drive <= 30)
 197                                 drive = 2;
 198                         else
 199                                 drive = 3;
 200                 } else {
 201                         drive = fdt_getprop_u32_default_node(fdt, offset, 0,
 202                                                              "allwinner,drive",
 203                                                               0);
 204                         drive = min(drive, 3);
 205                 }
 206
 207                 if (fdt_get_property(fdt, offset, "bias-disable", NULL))
 208                         pull = 0;
 209                 else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
 210                         pull = 1;
 211                 else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
 212                         pull = 2;
 213                 else
 214                         pull = fdt_getprop_u32_default_node(fdt, offset, 0,
 215                                                             "allwinner,pull",
 216                                                              0);
 217                 pull = min(pull, 2);
 218
 219                 for (i = 0; ; i++) {
 220                         pin_name = fdt_stringlist_get(fdt, offset,
 221                                                       "pins", i, NULL);
 222                         if (!pin_name) {
 223                                 pin_name = fdt_stringlist_get(fdt, offset,
 224                                                               "allwinner,pins",
 225                                                                i, NULL);
 226                                 if (!pin_name)
 227                                         break;
 228                         }
 229
 230                         pin = name_to_gpio(pin_name);
 231                         if (pin < 0)
 232                                 break;
 233
 234                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
 235                         sunxi_gpio_set_drv(pin, drive);
 236                         sunxi_gpio_set_pull(pin, pull);
 237                 }
 238         }
 239         return 0;
 240 }
 241
 242 static inline void sun4i_spi_enable_clock(void)
 243 {
 244         struct sunxi_ccm_reg *const ccm =
 245                 (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
 246
 247         setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
 248         writel((1 << 31), &ccm->spi0_clk_cfg);
 249 }
 250
 251 static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
 252 {
 253         struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
 254         int node = dev_of_offset(bus);
 255
 256         plat->base_addr = devfdt_get_addr(bus);
 257         plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
 258                                       "spi-max-frequency",
 259                                       SUN4I_SPI_DEFAULT_RATE);
 260
 261         if (plat->max_hz > SUN4I_SPI_MAX_RATE)
 262                 plat->max_hz = SUN4I_SPI_MAX_RATE;
 263
 264         return 0;
 265 }
 266
 267 static int sun4i_spi_probe(struct udevice *bus)
 268 {
 269         struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
 270         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 271
 272         sun4i_spi_enable_clock();
 273         sun4i_spi_parse_pins(bus);
 274
 275         priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;
 276         priv->freq = plat->max_hz;
 277
 278         return 0;
 279 }
 280
 281 static int sun4i_spi_claim_bus(struct udevice *dev)
 282 {
 283         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 284
 285         writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
 286                SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW,
 287                &priv->regs->ctl);
 288         return 0;
 289 }
 290
 291 static int sun4i_spi_release_bus(struct udevice *dev)
 292 {
 293         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 294         u32 reg;
 295
 296         reg = readl(&priv->regs->ctl);
 297         reg &= ~SUN4I_CTL_ENABLE;
 298         writel(reg, &priv->regs->ctl);
 299
 300         return 0;
 301 }
 302
 303 static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 304                           const void *dout, void *din, unsigned long flags)
 305 {
 306         struct udevice *bus = dev->parent;
 307         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 308         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 309
 310         u32 len = bitlen / 8;
 311         u32 reg;
 312         u8 nbytes;
 313         int ret;
 314
 315         priv->tx_buf = dout;
 316         priv->rx_buf = din;
 317
 318         if (bitlen % 8) {
 319                 debug("%s: non byte-aligned SPI transfer.\n", __func__);
 320                 return -ENAVAIL;
 321         }
 322
 323         if (flags & SPI_XFER_BEGIN)
 324                 sun4i_spi_set_cs(bus, slave_plat->cs, true);
 325
 326         reg = readl(&priv->regs->ctl);
 327
 328         /* Reset FIFOs */
 329         writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);
 330
 331         while (len) {
 332                 /* Setup the transfer now... */
 333                 nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));
 334
 335                 /* Setup the counters */
 336                 writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
 337                 writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);
 338
 339                 /* Fill the TX FIFO */
 340                 sun4i_spi_fill_fifo(priv, nbytes);
 341
 342                 /* Start the transfer */
 343                 reg = readl(&priv->regs->ctl);
 344                 writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
 345
 346                 /* Wait transfer to complete */
 347                 ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
 348                                         false, SUN4I_SPI_TIMEOUT_US, false);
 349                 if (ret) {
 350                         printf("ERROR: sun4i_spi: Timeout transferring data\n");
 351                         sun4i_spi_set_cs(bus, slave_plat->cs, false);
 352                         return ret;
 353                 }
 354
 355                 /* Drain the RX FIFO */
 356                 sun4i_spi_drain_fifo(priv, nbytes);
 357
 358                 len -= nbytes;
 359         }
 360
 361         if (flags & SPI_XFER_END)
 362                 sun4i_spi_set_cs(bus, slave_plat->cs, false);
 363
 364         return 0;
 365 }
 366
 367 static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
 368 {
 369         struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
 370         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 371         unsigned int div;
 372         u32 reg;
 373
 374         if (speed > plat->max_hz)
 375                 speed = plat->max_hz;
 376
 377         if (speed < SUN4I_SPI_MIN_RATE)
 378                 speed = SUN4I_SPI_MIN_RATE;
 379         /*
 380          * Setup clock divider.
 381          *
 382          * We have two choices there. Either we can use the clock
 383          * divide rate 1, which is calculated thanks to this formula:
 384          * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
 385          * Or we can use CDR2, which is calculated with the formula:
 386          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 387          * Whether we use the former or the latter is set through the
 388          * DRS bit.
 389          *
 390          * First try CDR2, and if we can't reach the expected
 391          * frequency, fall back to CDR1.
 392          */
 393
 394         div = SUN4I_SPI_MAX_RATE / (2 * speed);
 395         reg = readl(&priv->regs->cctl);
 396
 397         if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
 398                 if (div > 0)
 399                         div--;
 400
 401                 reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
 402                 reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
 403         } else {
 404                 div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
 405                 reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
 406                 reg |= SUN4I_CLK_CTL_CDR1(div);
 407         }
 408
 409         priv->freq = speed;
 410         writel(reg, &priv->regs->cctl);
 411
 412         return 0;
 413 }
 414
 415 static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
 416 {
 417         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 418         u32 reg;
 419
 420         reg = readl(&priv->regs->ctl);
 421         reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA);
 422
 423         if (mode & SPI_CPOL)
 424                 reg |= SUN4I_CTL_CPOL;
 425
 426         if (mode & SPI_CPHA)
 427                 reg |= SUN4I_CTL_CPHA;
 428
 429         priv->mode = mode;
 430         writel(reg, &priv->regs->ctl);
 431
 432         return 0;
 433 }
 434
 435 static const struct dm_spi_ops sun4i_spi_ops = {
 436         .claim_bus              = sun4i_spi_claim_bus,
 437         .release_bus            = sun4i_spi_release_bus,
 438         .xfer                   = sun4i_spi_xfer,
 439         .set_speed              = sun4i_spi_set_speed,
 440         .set_mode               = sun4i_spi_set_mode,
 441 };
 442
 443 static const struct udevice_id sun4i_spi_ids[] = {
 444         { .compatible = "allwinner,sun4i-a10-spi"  },
 445         { }
 446 };
 447
 448 U_BOOT_DRIVER(sun4i_spi) = {
 449         .name   = "sun4i_spi",
 450         .id     = UCLASS_SPI,
 451         .of_match       = sun4i_spi_ids,
 452         .ops    = &sun4i_spi_ops,
 453         .ofdata_to_platdata     = sun4i_spi_ofdata_to_platdata,
 454         .platdata_auto_alloc_size       = sizeof(struct sun4i_spi_platdata),
 455         .priv_auto_alloc_size   = sizeof(struct sun4i_spi_priv),
 456         .probe  = sun4i_spi_probe,
 457 };