1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
5 * Driver for STMicroelectronics Serial peripheral interface (SPI)
15 #include <dm/device_compat.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
21 #include <linux/bitfield.h>
22 #include <linux/iopoll.h>
24 /* STM32 SPI registers */
25 #define STM32_SPI_CR1 0x00
26 #define STM32_SPI_CR2 0x04
27 #define STM32_SPI_CFG1 0x08
28 #define STM32_SPI_CFG2 0x0C
29 #define STM32_SPI_SR 0x14
30 #define STM32_SPI_IFCR 0x18
31 #define STM32_SPI_TXDR 0x20
32 #define STM32_SPI_RXDR 0x30
33 #define STM32_SPI_I2SCFGR 0x50
35 /* STM32_SPI_CR1 bit fields */
36 #define SPI_CR1_SPE BIT(0)
37 #define SPI_CR1_MASRX BIT(8)
38 #define SPI_CR1_CSTART BIT(9)
39 #define SPI_CR1_CSUSP BIT(10)
40 #define SPI_CR1_HDDIR BIT(11)
41 #define SPI_CR1_SSI BIT(12)
43 /* STM32_SPI_CR2 bit fields */
44 #define SPI_CR2_TSIZE GENMASK(15, 0)
46 /* STM32_SPI_CFG1 bit fields */
47 #define SPI_CFG1_DSIZE GENMASK(4, 0)
48 #define SPI_CFG1_DSIZE_MIN 3
49 #define SPI_CFG1_FTHLV_SHIFT 5
50 #define SPI_CFG1_FTHLV GENMASK(8, 5)
51 #define SPI_CFG1_MBR_SHIFT 28
52 #define SPI_CFG1_MBR GENMASK(30, 28)
53 #define SPI_CFG1_MBR_MIN 0
54 #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
56 /* STM32_SPI_CFG2 bit fields */
57 #define SPI_CFG2_COMM_SHIFT 17
58 #define SPI_CFG2_COMM GENMASK(18, 17)
59 #define SPI_CFG2_MASTER BIT(22)
60 #define SPI_CFG2_LSBFRST BIT(23)
61 #define SPI_CFG2_CPHA BIT(24)
62 #define SPI_CFG2_CPOL BIT(25)
63 #define SPI_CFG2_SSM BIT(26)
64 #define SPI_CFG2_AFCNTR BIT(31)
66 /* STM32_SPI_SR bit fields */
67 #define SPI_SR_RXP BIT(0)
68 #define SPI_SR_TXP BIT(1)
69 #define SPI_SR_EOT BIT(3)
70 #define SPI_SR_TXTF BIT(4)
71 #define SPI_SR_OVR BIT(6)
72 #define SPI_SR_SUSP BIT(11)
73 #define SPI_SR_RXPLVL_SHIFT 13
74 #define SPI_SR_RXPLVL GENMASK(14, 13)
75 #define SPI_SR_RXWNE BIT(15)
77 /* STM32_SPI_IFCR bit fields */
78 #define SPI_IFCR_ALL GENMASK(11, 3)
80 /* STM32_SPI_I2SCFGR bit fields */
81 #define SPI_I2SCFGR_I2SMOD BIT(0)
83 #define MAX_CS_COUNT 4
85 /* SPI Master Baud Rate min/max divisor */
86 #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
87 #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
89 #define STM32_SPI_TIMEOUT_US 100000
91 /* SPI Communication mode */
92 #define SPI_FULL_DUPLEX 0
93 #define SPI_SIMPLEX_TX 1
94 #define SPI_SIMPLEX_RX 2
95 #define SPI_HALF_DUPLEX 3
97 struct stm32_spi_priv {
100 struct reset_ctl rst_ctl;
101 struct gpio_desc cs_gpios[MAX_CS_COUNT];
103 unsigned int fifo_size;
104 unsigned int cur_bpw;
106 unsigned int cur_xferlen; /* current transfer length in bytes */
107 unsigned int tx_len; /* number of data to be written in bytes */
108 unsigned int rx_len; /* number of data to be read in bytes */
109 const void *tx_buf; /* data to be written, or NULL */
110 void *rx_buf; /* data to be read, or NULL */
115 static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
117 while ((priv->tx_len > 0) &&
118 (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
119 u32 offs = priv->cur_xferlen - priv->tx_len;
121 if (priv->tx_len >= sizeof(u32) &&
122 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
123 const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
125 writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
126 priv->tx_len -= sizeof(u32);
127 } else if (priv->tx_len >= sizeof(u16) &&
128 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
129 const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
131 writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
132 priv->tx_len -= sizeof(u16);
134 const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
136 writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
137 priv->tx_len -= sizeof(u8);
141 debug("%s: %d bytes left\n", __func__, priv->tx_len);
144 static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
146 u32 sr = readl(priv->base + STM32_SPI_SR);
147 u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
149 while ((priv->rx_len > 0) &&
150 ((sr & SPI_SR_RXP) ||
151 ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
152 u32 offs = priv->cur_xferlen - priv->rx_len;
154 if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
155 (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
156 u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
158 *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
159 priv->rx_len -= sizeof(u32);
160 } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
161 (priv->rx_len >= sizeof(u16) ||
162 (!(sr & SPI_SR_RXWNE) &&
163 (rxplvl >= 2 || priv->cur_bpw > 8)))) {
164 u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
166 *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
167 priv->rx_len -= sizeof(u16);
169 u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
171 *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
172 priv->rx_len -= sizeof(u8);
175 sr = readl(priv->base + STM32_SPI_SR);
176 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
179 debug("%s: %d bytes left\n", __func__, priv->rx_len);
182 static int stm32_spi_enable(struct stm32_spi_priv *priv)
184 debug("%s\n", __func__);
186 /* Enable the SPI hardware */
187 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
192 static int stm32_spi_disable(struct stm32_spi_priv *priv)
194 debug("%s\n", __func__);
196 /* Disable the SPI hardware */
197 clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
202 static int stm32_spi_claim_bus(struct udevice *slave)
204 struct udevice *bus = dev_get_parent(slave);
205 struct stm32_spi_priv *priv = dev_get_priv(bus);
207 debug("%s\n", __func__);
209 /* Enable the SPI hardware */
210 return stm32_spi_enable(priv);
213 static int stm32_spi_release_bus(struct udevice *slave)
215 struct udevice *bus = dev_get_parent(slave);
216 struct stm32_spi_priv *priv = dev_get_priv(bus);
218 debug("%s\n", __func__);
220 /* Disable the SPI hardware */
221 return stm32_spi_disable(priv);
224 static void stm32_spi_stopxfer(struct udevice *dev)
226 struct stm32_spi_priv *priv = dev_get_priv(dev);
230 debug("%s\n", __func__);
232 cr1 = readl(priv->base + STM32_SPI_CR1);
234 if (!(cr1 & SPI_CR1_SPE))
237 /* Wait on EOT or suspend the flow */
238 ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
239 !(sr & SPI_SR_EOT), 100000);
241 if (cr1 & SPI_CR1_CSTART) {
242 writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
243 if (readl_poll_timeout(priv->base + STM32_SPI_SR,
244 sr, !(sr & SPI_SR_SUSP),
246 dev_err(dev, "Suspend request timeout\n");
250 /* clear status flags */
251 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
254 static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
256 struct stm32_spi_priv *priv = dev_get_priv(dev);
258 debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
260 if (cs >= MAX_CS_COUNT)
263 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
269 return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
272 static int stm32_spi_set_mode(struct udevice *bus, uint mode)
274 struct stm32_spi_priv *priv = dev_get_priv(bus);
275 u32 cfg2_clrb = 0, cfg2_setb = 0;
277 debug("%s: mode=%d\n", __func__, mode);
280 cfg2_setb |= SPI_CFG2_CPOL;
282 cfg2_clrb |= SPI_CFG2_CPOL;
285 cfg2_setb |= SPI_CFG2_CPHA;
287 cfg2_clrb |= SPI_CFG2_CPHA;
289 if (mode & SPI_LSB_FIRST)
290 cfg2_setb |= SPI_CFG2_LSBFRST;
292 cfg2_clrb |= SPI_CFG2_LSBFRST;
294 if (cfg2_clrb || cfg2_setb)
295 clrsetbits_le32(priv->base + STM32_SPI_CFG2,
296 cfg2_clrb, cfg2_setb);
298 if (mode & SPI_CS_HIGH)
299 priv->cs_high = true;
301 priv->cs_high = false;
305 static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
307 struct stm32_spi_priv *priv = dev_get_priv(dev);
308 u32 fthlv, half_fifo;
310 /* data packet should not exceed 1/2 of fifo space */
311 half_fifo = (priv->fifo_size / 2);
313 /* data_packet should not exceed transfer length */
314 fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
316 /* align packet size with data registers access */
317 fthlv -= (fthlv % 4);
321 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
322 (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
327 static int stm32_spi_set_speed(struct udevice *bus, uint hz)
329 struct stm32_spi_priv *priv = dev_get_priv(bus);
333 debug("%s: hz=%d\n", __func__, hz);
335 if (priv->cur_hz == hz)
338 div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
340 if (div < STM32_MBR_DIV_MIN ||
341 div > STM32_MBR_DIV_MAX)
344 /* Determine the first power of 2 greater than or equal to div */
348 mbrdiv = fls(div) - 1;
353 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
354 (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
361 static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
362 const void *dout, void *din, unsigned long flags)
364 struct udevice *bus = dev_get_parent(slave);
365 struct dm_spi_slave_platdata *slave_plat;
366 struct stm32_spi_priv *priv = dev_get_priv(bus);
373 xferlen = bitlen / 8;
375 if (xferlen <= SPI_CR2_TSIZE)
376 writel(xferlen, priv->base + STM32_SPI_CR2);
382 priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
383 priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
385 mode = SPI_FULL_DUPLEX;
387 mode = SPI_SIMPLEX_RX;
388 else if (!priv->rx_buf)
389 mode = SPI_SIMPLEX_TX;
391 if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
392 priv->cur_mode = mode;
393 priv->cur_xferlen = xferlen;
395 /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
396 stm32_spi_disable(priv);
398 clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
399 mode << SPI_CFG2_COMM_SHIFT);
401 stm32_spi_set_fthlv(bus, xferlen);
403 /* Enable the SPI hardware */
404 stm32_spi_enable(priv);
407 debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
408 priv->tx_len, priv->rx_len);
410 slave_plat = dev_get_parent_platdata(slave);
411 if (flags & SPI_XFER_BEGIN)
412 stm32_spi_set_cs(bus, slave_plat->cs, false);
414 /* Be sure to have data in fifo before starting data transfer */
416 stm32_spi_write_txfifo(priv);
418 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
421 sr = readl(priv->base + STM32_SPI_SR);
423 if (sr & SPI_SR_OVR) {
424 dev_err(bus, "Overrun: RX data lost\n");
429 if (sr & SPI_SR_SUSP) {
430 dev_warn(bus, "System too slow is limiting data throughput\n");
432 if (priv->rx_buf && priv->rx_len > 0)
433 stm32_spi_read_rxfifo(priv);
438 if (sr & SPI_SR_TXTF)
442 if (priv->tx_buf && priv->tx_len > 0)
443 stm32_spi_write_txfifo(priv);
446 if (priv->rx_buf && priv->rx_len > 0)
447 stm32_spi_read_rxfifo(priv);
449 if (sr & SPI_SR_EOT) {
450 if (priv->rx_buf && priv->rx_len > 0)
451 stm32_spi_read_rxfifo(priv);
455 writel(ifcr, priv->base + STM32_SPI_IFCR);
458 /* clear status flags */
459 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
460 stm32_spi_stopxfer(bus);
462 if (flags & SPI_XFER_END)
463 stm32_spi_set_cs(bus, slave_plat->cs, true);
468 static int stm32_spi_get_fifo_size(struct udevice *dev)
470 struct stm32_spi_priv *priv = dev_get_priv(dev);
473 stm32_spi_enable(priv);
475 while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
476 writeb(++count, priv->base + STM32_SPI_TXDR);
478 stm32_spi_disable(priv);
480 debug("%s %d x 8-bit fifo size\n", __func__, count);
485 static int stm32_spi_probe(struct udevice *dev)
487 struct stm32_spi_priv *priv = dev_get_priv(dev);
488 unsigned long clk_rate;
492 priv->base = dev_remap_addr(dev);
497 ret = clk_get_by_index(dev, 0, &priv->clk);
501 ret = clk_enable(&priv->clk);
505 clk_rate = clk_get_rate(&priv->clk);
511 priv->bus_clk_rate = clk_rate;
514 ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
518 reset_assert(&priv->rst_ctl);
520 reset_deassert(&priv->rst_ctl);
522 ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
523 ARRAY_SIZE(priv->cs_gpios), 0);
525 pr_err("Can't get %s cs gpios: %d", dev->name, ret);
529 priv->fifo_size = stm32_spi_get_fifo_size(dev);
531 priv->cur_mode = SPI_FULL_DUPLEX;
532 priv->cur_xferlen = 0;
533 priv->cur_bpw = SPI_DEFAULT_WORDLEN;
534 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
537 for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
538 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
541 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
542 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
545 /* Ensure I2SMOD bit is kept cleared */
546 clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
549 * - SS input value high
550 * - transmitter half duplex direction
551 * - automatic communication suspend when RX-Fifo is full
553 setbits_le32(priv->base + STM32_SPI_CR1,
554 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
557 * - Set the master mode (default Motorola mode)
558 * - Consider 1 master/n slaves configuration and
559 * SS input value is determined by the SSI bit
560 * - keep control of all associated GPIOs
562 setbits_le32(priv->base + STM32_SPI_CFG2,
563 SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
568 reset_free(&priv->rst_ctl);
571 clk_disable(&priv->clk);
572 clk_free(&priv->clk);
577 static int stm32_spi_remove(struct udevice *dev)
579 struct stm32_spi_priv *priv = dev_get_priv(dev);
582 stm32_spi_stopxfer(dev);
583 stm32_spi_disable(priv);
585 ret = reset_assert(&priv->rst_ctl);
589 reset_free(&priv->rst_ctl);
591 ret = clk_disable(&priv->clk);
595 clk_free(&priv->clk);
600 static const struct dm_spi_ops stm32_spi_ops = {
601 .claim_bus = stm32_spi_claim_bus,
602 .release_bus = stm32_spi_release_bus,
603 .set_mode = stm32_spi_set_mode,
604 .set_speed = stm32_spi_set_speed,
605 .xfer = stm32_spi_xfer,
608 static const struct udevice_id stm32_spi_ids[] = {
609 { .compatible = "st,stm32h7-spi", },
613 U_BOOT_DRIVER(stm32_spi) = {
616 .of_match = stm32_spi_ids,
617 .ops = &stm32_spi_ops,
618 .priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
619 .probe = stm32_spi_probe,
620 .remove = stm32_spi_remove,