1 // SPDX-License-Identifier: GPL-2.0+
5 * Michael Kurz, <michi.kurz@gmail.com>
15 #include <dm/device_compat.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/iopoll.h>
19 #include <linux/ioport.h>
20 #include <linux/sizes.h>
22 struct stm32_qspi_regs {
39 * QUADSPI control register
41 #define STM32_QSPI_CR_EN BIT(0)
42 #define STM32_QSPI_CR_ABORT BIT(1)
43 #define STM32_QSPI_CR_DMAEN BIT(2)
44 #define STM32_QSPI_CR_TCEN BIT(3)
45 #define STM32_QSPI_CR_SSHIFT BIT(4)
46 #define STM32_QSPI_CR_DFM BIT(6)
47 #define STM32_QSPI_CR_FSEL BIT(7)
48 #define STM32_QSPI_CR_FTHRES_SHIFT 8
49 #define STM32_QSPI_CR_TEIE BIT(16)
50 #define STM32_QSPI_CR_TCIE BIT(17)
51 #define STM32_QSPI_CR_FTIE BIT(18)
52 #define STM32_QSPI_CR_SMIE BIT(19)
53 #define STM32_QSPI_CR_TOIE BIT(20)
54 #define STM32_QSPI_CR_APMS BIT(22)
55 #define STM32_QSPI_CR_PMM BIT(23)
56 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
57 #define STM32_QSPI_CR_PRESCALER_SHIFT 24
60 * QUADSPI device configuration register
62 #define STM32_QSPI_DCR_CKMODE BIT(0)
63 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
64 #define STM32_QSPI_DCR_CSHT_SHIFT 8
65 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
66 #define STM32_QSPI_DCR_FSIZE_SHIFT 16
69 * QUADSPI status register
71 #define STM32_QSPI_SR_TEF BIT(0)
72 #define STM32_QSPI_SR_TCF BIT(1)
73 #define STM32_QSPI_SR_FTF BIT(2)
74 #define STM32_QSPI_SR_SMF BIT(3)
75 #define STM32_QSPI_SR_TOF BIT(4)
76 #define STM32_QSPI_SR_BUSY BIT(5)
79 * QUADSPI flag clear register
81 #define STM32_QSPI_FCR_CTEF BIT(0)
82 #define STM32_QSPI_FCR_CTCF BIT(1)
83 #define STM32_QSPI_FCR_CSMF BIT(3)
84 #define STM32_QSPI_FCR_CTOF BIT(4)
87 * QUADSPI communication configuration register
89 #define STM32_QSPI_CCR_DDRM BIT(31)
90 #define STM32_QSPI_CCR_DHHC BIT(30)
91 #define STM32_QSPI_CCR_SIOO BIT(28)
92 #define STM32_QSPI_CCR_FMODE_SHIFT 26
93 #define STM32_QSPI_CCR_DMODE_SHIFT 24
94 #define STM32_QSPI_CCR_DCYC_SHIFT 18
95 #define STM32_QSPI_CCR_ABSIZE_SHIFT 16
96 #define STM32_QSPI_CCR_ABMODE_SHIFT 14
97 #define STM32_QSPI_CCR_ADSIZE_SHIFT 12
98 #define STM32_QSPI_CCR_ADMODE_SHIFT 10
99 #define STM32_QSPI_CCR_IMODE_SHIFT 8
101 #define STM32_QSPI_CCR_IND_WRITE 0
102 #define STM32_QSPI_CCR_IND_READ 1
103 #define STM32_QSPI_CCR_MEM_MAP 3
105 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
106 #define STM32_QSPI_MAX_CHIP 2
108 #define STM32_QSPI_FIFO_TIMEOUT_US 30000
109 #define STM32_QSPI_CMD_TIMEOUT_US 1000000
110 #define STM32_BUSY_TIMEOUT_US 100000
111 #define STM32_ABT_TIMEOUT_US 100000
113 struct stm32_qspi_flash {
119 struct stm32_qspi_priv {
120 struct stm32_qspi_regs *regs;
121 struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
122 void __iomem *mm_base;
123 resource_size_t mm_size;
128 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
133 ret = readl_poll_timeout(&priv->regs->sr, sr,
134 !(sr & STM32_QSPI_SR_BUSY),
135 STM32_BUSY_TIMEOUT_US);
137 pr_err("busy timeout (stat:%#x)\n", sr);
142 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
143 const struct spi_mem_op *op)
148 if (!op->data.nbytes)
149 return _stm32_qspi_wait_for_not_busy(priv);
151 ret = readl_poll_timeout(&priv->regs->sr, sr,
152 sr & STM32_QSPI_SR_TCF,
153 STM32_QSPI_CMD_TIMEOUT_US);
155 pr_err("cmd timeout (stat:%#x)\n", sr);
156 } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
157 pr_err("transfer error (stat:%#x)\n", sr);
162 writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
167 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
172 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
177 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
178 const struct spi_mem_op *op)
180 void (*fifo)(u8 *val, void __iomem *addr);
181 u32 len = op->data.nbytes, sr;
185 if (op->data.dir == SPI_MEM_DATA_IN) {
186 fifo = _stm32_qspi_read_fifo;
187 buf = op->data.buf.in;
190 fifo = _stm32_qspi_write_fifo;
191 buf = (u8 *)op->data.buf.out;
195 ret = readl_poll_timeout(&priv->regs->sr, sr,
196 sr & STM32_QSPI_SR_FTF,
197 STM32_QSPI_FIFO_TIMEOUT_US);
199 pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
203 fifo(buf++, &priv->regs->dr);
209 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
210 const struct spi_mem_op *op)
212 memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
218 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
219 const struct spi_mem_op *op,
222 if (!op->data.nbytes)
225 if (mode == STM32_QSPI_CCR_MEM_MAP)
226 return stm32_qspi_mm(priv, op);
228 return _stm32_qspi_poll(priv, op);
231 static int _stm32_qspi_get_mode(u8 buswidth)
239 static int stm32_qspi_exec_op(struct spi_slave *slave,
240 const struct spi_mem_op *op)
242 struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
243 u32 cr, ccr, addr_max;
244 u8 mode = STM32_QSPI_CCR_IND_WRITE;
247 debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
248 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
249 op->dummy.buswidth, op->data.buswidth,
250 op->addr.val, op->data.nbytes);
252 ret = _stm32_qspi_wait_for_not_busy(priv);
256 addr_max = op->addr.val + op->data.nbytes + 1;
258 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
259 if (addr_max < priv->mm_size && op->addr.buswidth)
260 mode = STM32_QSPI_CCR_MEM_MAP;
262 mode = STM32_QSPI_CCR_IND_READ;
266 writel(op->data.nbytes - 1, &priv->regs->dlr);
268 ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
269 ccr |= op->cmd.opcode;
270 ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
271 << STM32_QSPI_CCR_IMODE_SHIFT);
273 if (op->addr.nbytes) {
274 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
275 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
276 << STM32_QSPI_CCR_ADMODE_SHIFT);
279 if (op->dummy.buswidth && op->dummy.nbytes)
280 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
281 << STM32_QSPI_CCR_DCYC_SHIFT);
284 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
285 << STM32_QSPI_CCR_DMODE_SHIFT);
287 writel(ccr, &priv->regs->ccr);
289 if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
290 writel(op->addr.val, &priv->regs->ar);
292 ret = _stm32_qspi_tx(priv, op, mode);
296 * -read memory map: prefetching must be stopped if we read the last
297 * byte of device (device size - fifo size). like device size is not
298 * knows, the prefetching is always stop.
300 if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
303 /* Wait end of tx in indirect mode */
304 ret = _stm32_qspi_wait_cmd(priv, op);
311 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
313 /* Wait clear of abort bit by hw */
314 timeout = readl_poll_timeout(&priv->regs->cr, cr,
315 !(cr & STM32_QSPI_CR_ABORT),
316 STM32_ABT_TIMEOUT_US);
318 writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
321 pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
326 static int stm32_qspi_probe(struct udevice *bus)
328 struct stm32_qspi_priv *priv = dev_get_priv(bus);
331 struct reset_ctl reset_ctl;
334 ret = dev_read_resource_byname(bus, "qspi", &res);
336 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
340 priv->regs = (struct stm32_qspi_regs *)res.start;
342 ret = dev_read_resource_byname(bus, "qspi_mm", &res);
344 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
348 priv->mm_base = (void __iomem *)res.start;
350 priv->mm_size = resource_size(&res);
351 if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
354 debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
355 __func__, priv->regs, priv->mm_base, priv->mm_size);
357 ret = clk_get_by_index(bus, 0, &clk);
361 ret = clk_enable(&clk);
363 dev_err(bus, "failed to enable clock\n");
367 priv->clock_rate = clk_get_rate(&clk);
368 if (!priv->clock_rate) {
373 ret = reset_get_by_index(bus, 0, &reset_ctl);
375 if (ret != -ENOENT) {
376 dev_err(bus, "failed to get reset\n");
381 /* Reset QSPI controller */
382 reset_assert(&reset_ctl);
384 reset_deassert(&reset_ctl);
389 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
391 /* Set dcr fsize to max address */
392 setbits_le32(&priv->regs->dcr,
393 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
398 static int stm32_qspi_claim_bus(struct udevice *dev)
400 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
401 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
402 int slave_cs = slave_plat->cs;
404 if (slave_cs >= STM32_QSPI_MAX_CHIP)
407 if (priv->cs_used != slave_cs) {
408 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
410 priv->cs_used = slave_cs;
412 if (flash->initialized) {
413 /* Set the configuration: speed + cs */
414 writel(flash->cr, &priv->regs->cr);
415 writel(flash->dcr, &priv->regs->dcr);
417 /* Set chip select */
418 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
419 priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
421 /* Save the configuration: speed + cs */
422 flash->cr = readl(&priv->regs->cr);
423 flash->dcr = readl(&priv->regs->dcr);
425 flash->initialized = true;
429 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
434 static int stm32_qspi_release_bus(struct udevice *dev)
436 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
438 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
443 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
445 struct stm32_qspi_priv *priv = dev_get_priv(bus);
446 u32 qspi_clk = priv->clock_rate;
454 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
460 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
461 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
463 ret = _stm32_qspi_wait_for_not_busy(priv);
467 clrsetbits_le32(&priv->regs->cr,
468 STM32_QSPI_CR_PRESCALER_MASK <<
469 STM32_QSPI_CR_PRESCALER_SHIFT,
470 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
472 clrsetbits_le32(&priv->regs->dcr,
473 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
474 csht << STM32_QSPI_DCR_CSHT_SHIFT);
476 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
477 (qspi_clk / (prescaler + 1)));
482 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
484 struct stm32_qspi_priv *priv = dev_get_priv(bus);
487 ret = _stm32_qspi_wait_for_not_busy(priv);
491 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
492 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
493 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
494 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
498 if (mode & SPI_CS_HIGH)
501 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
503 if (mode & SPI_RX_QUAD)
505 else if (mode & SPI_RX_DUAL)
508 debug("single, tx: ");
510 if (mode & SPI_TX_QUAD)
512 else if (mode & SPI_TX_DUAL)
520 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
521 .exec_op = stm32_qspi_exec_op,
524 static const struct dm_spi_ops stm32_qspi_ops = {
525 .claim_bus = stm32_qspi_claim_bus,
526 .release_bus = stm32_qspi_release_bus,
527 .set_speed = stm32_qspi_set_speed,
528 .set_mode = stm32_qspi_set_mode,
529 .mem_ops = &stm32_qspi_mem_ops,
532 static const struct udevice_id stm32_qspi_ids[] = {
533 { .compatible = "st,stm32f469-qspi" },
537 U_BOOT_DRIVER(stm32_qspi) = {
538 .name = "stm32_qspi",
540 .of_match = stm32_qspi_ids,
541 .ops = &stm32_qspi_ops,
542 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
543 .probe = stm32_qspi_probe,