drivers/spi/stm32_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016
   4  *
   5  * Michael Kurz, <michi.kurz@gmail.com>
   6  *
   7  * STM32 QSPI driver
   8  */
   9
  10 #define LOG_CATEGORY UCLASS_SPI
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <dm.h>
  15 #include <log.h>
  16 #include <reset.h>
  17 #include <spi.h>
  18 #include <spi-mem.h>
  19 #include <watchdog.h>
  20 #include <dm/device_compat.h>
  21 #include <linux/bitops.h>
  22 #include <linux/delay.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sizes.h>
  26
  27 struct stm32_qspi_regs {
  28         u32 cr;         /* 0x00 */
  29         u32 dcr;        /* 0x04 */
  30         u32 sr;         /* 0x08 */
  31         u32 fcr;        /* 0x0C */
  32         u32 dlr;        /* 0x10 */
  33         u32 ccr;        /* 0x14 */
  34         u32 ar;         /* 0x18 */
  35         u32 abr;        /* 0x1C */
  36         u32 dr;         /* 0x20 */
  37         u32 psmkr;      /* 0x24 */
  38         u32 psmar;      /* 0x28 */
  39         u32 pir;        /* 0x2C */
  40         u32 lptr;       /* 0x30 */
  41 };
  42
  43 /*
  44  * QUADSPI control register
  45  */
  46 #define STM32_QSPI_CR_EN                BIT(0)
  47 #define STM32_QSPI_CR_ABORT             BIT(1)
  48 #define STM32_QSPI_CR_DMAEN             BIT(2)
  49 #define STM32_QSPI_CR_TCEN              BIT(3)
  50 #define STM32_QSPI_CR_SSHIFT            BIT(4)
  51 #define STM32_QSPI_CR_DFM               BIT(6)
  52 #define STM32_QSPI_CR_FSEL              BIT(7)
  53 #define STM32_QSPI_CR_FTHRES_SHIFT      8
  54 #define STM32_QSPI_CR_TEIE              BIT(16)
  55 #define STM32_QSPI_CR_TCIE              BIT(17)
  56 #define STM32_QSPI_CR_FTIE              BIT(18)
  57 #define STM32_QSPI_CR_SMIE              BIT(19)
  58 #define STM32_QSPI_CR_TOIE              BIT(20)
  59 #define STM32_QSPI_CR_APMS              BIT(22)
  60 #define STM32_QSPI_CR_PMM               BIT(23)
  61 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
  62 #define STM32_QSPI_CR_PRESCALER_SHIFT   24
  63
  64 /*
  65  * QUADSPI device configuration register
  66  */
  67 #define STM32_QSPI_DCR_CKMODE           BIT(0)
  68 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
  69 #define STM32_QSPI_DCR_CSHT_SHIFT       8
  70 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
  71 #define STM32_QSPI_DCR_FSIZE_SHIFT      16
  72
  73 /*
  74  * QUADSPI status register
  75  */
  76 #define STM32_QSPI_SR_TEF               BIT(0)
  77 #define STM32_QSPI_SR_TCF               BIT(1)
  78 #define STM32_QSPI_SR_FTF               BIT(2)
  79 #define STM32_QSPI_SR_SMF               BIT(3)
  80 #define STM32_QSPI_SR_TOF               BIT(4)
  81 #define STM32_QSPI_SR_BUSY              BIT(5)
  82
  83 /*
  84  * QUADSPI flag clear register
  85  */
  86 #define STM32_QSPI_FCR_CTEF             BIT(0)
  87 #define STM32_QSPI_FCR_CTCF             BIT(1)
  88 #define STM32_QSPI_FCR_CSMF             BIT(3)
  89 #define STM32_QSPI_FCR_CTOF             BIT(4)
  90
  91 /*
  92  * QUADSPI communication configuration register
  93  */
  94 #define STM32_QSPI_CCR_DDRM             BIT(31)
  95 #define STM32_QSPI_CCR_DHHC             BIT(30)
  96 #define STM32_QSPI_CCR_SIOO             BIT(28)
  97 #define STM32_QSPI_CCR_FMODE_SHIFT      26
  98 #define STM32_QSPI_CCR_DMODE_SHIFT      24
  99 #define STM32_QSPI_CCR_DCYC_SHIFT       18
 100 #define STM32_QSPI_CCR_ABSIZE_SHIFT     16
 101 #define STM32_QSPI_CCR_ABMODE_SHIFT     14
 102 #define STM32_QSPI_CCR_ADSIZE_SHIFT     12
 103 #define STM32_QSPI_CCR_ADMODE_SHIFT     10
 104 #define STM32_QSPI_CCR_IMODE_SHIFT      8
 105
 106 #define STM32_QSPI_CCR_IND_WRITE        0
 107 #define STM32_QSPI_CCR_IND_READ         1
 108 #define STM32_QSPI_CCR_MEM_MAP          3
 109
 110 #define STM32_QSPI_MAX_MMAP_SZ          SZ_256M
 111 #define STM32_QSPI_MAX_CHIP             2
 112
 113 #define STM32_QSPI_FIFO_TIMEOUT_US      30000
 114 #define STM32_QSPI_CMD_TIMEOUT_US       1000000
 115 #define STM32_BUSY_TIMEOUT_US           100000
 116 #define STM32_ABT_TIMEOUT_US            100000
 117
 118 struct stm32_qspi_priv {
 119         struct stm32_qspi_regs *regs;
 120         void __iomem *mm_base;
 121         resource_size_t mm_size;
 122         ulong clock_rate;
 123         int cs_used;
 124 };
 125
 126 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
 127 {
 128         u32 sr;
 129         int ret;
 130
 131         ret = readl_poll_timeout(&priv->regs->sr, sr,
 132                                  !(sr & STM32_QSPI_SR_BUSY),
 133                                  STM32_BUSY_TIMEOUT_US);
 134         if (ret)
 135                 log_err("busy timeout (stat:%#x)\n", sr);
 136
 137         return ret;
 138 }
 139
 140 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
 141                                 const struct spi_mem_op *op)
 142 {
 143         u32 sr;
 144         int ret = 0;
 145
 146         ret = readl_poll_timeout(&priv->regs->sr, sr,
 147                                  sr & STM32_QSPI_SR_TCF,
 148                                  STM32_QSPI_CMD_TIMEOUT_US);
 149         if (ret) {
 150                 log_err("cmd timeout (stat:%#x)\n", sr);
 151         } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
 152                 log_err("transfer error (stat:%#x)\n", sr);
 153                 ret = -EIO;
 154         }
 155
 156         /* clear flags */
 157         writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
 158
 159         if (!ret)
 160                 ret = _stm32_qspi_wait_for_not_busy(priv);
 161
 162         return ret;
 163 }
 164
 165 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 166 {
 167         *val = readb(addr);
 168         schedule();
 169 }
 170
 171 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 172 {
 173         writeb(*val, addr);
 174 }
 175
 176 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
 177                             const struct spi_mem_op *op)
 178 {
 179         void (*fifo)(u8 *val, void __iomem *addr);
 180         u32 len = op->data.nbytes, sr;
 181         u8 *buf;
 182         int ret;
 183
 184         if (op->data.dir == SPI_MEM_DATA_IN) {
 185                 fifo = _stm32_qspi_read_fifo;
 186                 buf = op->data.buf.in;
 187
 188         } else {
 189                 fifo = _stm32_qspi_write_fifo;
 190                 buf = (u8 *)op->data.buf.out;
 191         }
 192
 193         while (len--) {
 194                 ret = readl_poll_timeout(&priv->regs->sr, sr,
 195                                          sr & STM32_QSPI_SR_FTF,
 196                                          STM32_QSPI_FIFO_TIMEOUT_US);
 197                 if (ret) {
 198                         log_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
 199                         return ret;
 200                 }
 201
 202                 fifo(buf++, &priv->regs->dr);
 203         }
 204
 205         return 0;
 206 }
 207
 208 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
 209                          const struct spi_mem_op *op)
 210 {
 211         memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
 212                       op->data.nbytes);
 213
 214         return 0;
 215 }
 216
 217 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
 218                           const struct spi_mem_op *op,
 219                           u8 mode)
 220 {
 221         if (!op->data.nbytes)
 222                 return 0;
 223
 224         if (mode == STM32_QSPI_CCR_MEM_MAP)
 225                 return stm32_qspi_mm(priv, op);
 226
 227         return _stm32_qspi_poll(priv, op);
 228 }
 229
 230 static int _stm32_qspi_get_mode(u8 buswidth)
 231 {
 232         if (buswidth == 4)
 233                 return 3;
 234
 235         return buswidth;
 236 }
 237
 238 static int stm32_qspi_exec_op(struct spi_slave *slave,
 239                               const struct spi_mem_op *op)
 240 {
 241         struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 242         u32 cr, ccr, addr_max;
 243         u8 mode = STM32_QSPI_CCR_IND_WRITE;
 244         int timeout, ret;
 245
 246         dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 247                 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 248                 op->dummy.buswidth, op->data.buswidth,
 249                 op->addr.val, op->data.nbytes);
 250
 251         addr_max = op->addr.val + op->data.nbytes + 1;
 252
 253         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
 254                 if (addr_max < priv->mm_size && op->addr.buswidth)
 255                         mode = STM32_QSPI_CCR_MEM_MAP;
 256                 else
 257                         mode = STM32_QSPI_CCR_IND_READ;
 258         }
 259
 260         if (op->data.nbytes)
 261                 writel(op->data.nbytes - 1, &priv->regs->dlr);
 262
 263         ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
 264         ccr |= op->cmd.opcode;
 265         ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
 266                 << STM32_QSPI_CCR_IMODE_SHIFT);
 267
 268         if (op->addr.nbytes) {
 269                 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
 270                 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
 271                         << STM32_QSPI_CCR_ADMODE_SHIFT);
 272         }
 273
 274         if (op->dummy.buswidth && op->dummy.nbytes)
 275                 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
 276                         << STM32_QSPI_CCR_DCYC_SHIFT);
 277
 278         if (op->data.nbytes)
 279                 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
 280                         << STM32_QSPI_CCR_DMODE_SHIFT);
 281
 282         writel(ccr, &priv->regs->ccr);
 283
 284         if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
 285                 writel(op->addr.val, &priv->regs->ar);
 286
 287         ret = _stm32_qspi_tx(priv, op, mode);
 288         /*
 289          * Abort in:
 290          * -error case
 291          * -read memory map: prefetching must be stopped if we read the last
 292          *  byte of device (device size - fifo size). like device size is not
 293          *  knows, the prefetching is always stop.
 294          */
 295         if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
 296                 goto abort;
 297
 298         /* Wait end of tx in indirect mode */
 299         ret = _stm32_qspi_wait_cmd(priv, op);
 300         if (ret)
 301                 goto abort;
 302
 303         return 0;
 304
 305 abort:
 306         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
 307
 308         /* Wait clear of abort bit by hw */
 309         timeout = readl_poll_timeout(&priv->regs->cr, cr,
 310                                      !(cr & STM32_QSPI_CR_ABORT),
 311                                      STM32_ABT_TIMEOUT_US);
 312
 313         writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
 314
 315         if (ret || timeout)
 316                 dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout);
 317
 318         return ret;
 319 }
 320
 321 static int stm32_qspi_probe(struct udevice *bus)
 322 {
 323         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 324         struct resource res;
 325         struct clk clk;
 326         struct reset_ctl reset_ctl;
 327         int ret;
 328
 329         ret = dev_read_resource_byname(bus, "qspi", &res);
 330         if (ret) {
 331                 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
 332                 return ret;
 333         }
 334
 335         priv->regs = (struct stm32_qspi_regs *)res.start;
 336
 337         ret = dev_read_resource_byname(bus, "qspi_mm", &res);
 338         if (ret) {
 339                 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
 340                 return ret;
 341         }
 342
 343         priv->mm_base = (void __iomem *)res.start;
 344
 345         priv->mm_size = resource_size(&res);
 346         if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
 347                 return -EINVAL;
 348
 349         dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
 350                 priv->regs, priv->mm_base, priv->mm_size);
 351
 352         ret = clk_get_by_index(bus, 0, &clk);
 353         if (ret < 0)
 354                 return ret;
 355
 356         ret = clk_enable(&clk);
 357         if (ret) {
 358                 dev_err(bus, "failed to enable clock\n");
 359                 return ret;
 360         }
 361
 362         priv->clock_rate = clk_get_rate(&clk);
 363         if (!priv->clock_rate) {
 364                 clk_disable(&clk);
 365                 return -EINVAL;
 366         }
 367
 368         ret = reset_get_by_index(bus, 0, &reset_ctl);
 369         if (ret) {
 370                 if (ret != -ENOENT) {
 371                         dev_err(bus, "failed to get reset\n");
 372                         clk_disable(&clk);
 373                         return ret;
 374                 }
 375         } else {
 376                 /* Reset QSPI controller */
 377                 reset_assert(&reset_ctl);
 378                 udelay(2);
 379                 reset_deassert(&reset_ctl);
 380         }
 381
 382         priv->cs_used = -1;
 383
 384         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 385
 386         /* Set dcr fsize to max address */
 387         setbits_le32(&priv->regs->dcr,
 388                      STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
 389
 390         return 0;
 391 }
 392
 393 static int stm32_qspi_claim_bus(struct udevice *dev)
 394 {
 395         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 396         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 397         int slave_cs = slave_plat->cs;
 398
 399         if (slave_cs >= STM32_QSPI_MAX_CHIP)
 400                 return -ENODEV;
 401
 402         if (priv->cs_used != slave_cs) {
 403                 priv->cs_used = slave_cs;
 404
 405                 /* Set chip select */
 406                 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
 407                                 priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
 408         }
 409
 410         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 411
 412         return 0;
 413 }
 414
 415 static int stm32_qspi_release_bus(struct udevice *dev)
 416 {
 417         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 418
 419         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 420
 421         return 0;
 422 }
 423
 424 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 425 {
 426         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 427         u32 qspi_clk = priv->clock_rate;
 428         u32 prescaler = 255;
 429         u32 csht;
 430         int ret;
 431
 432         if (speed > 0) {
 433                 prescaler = 0;
 434                 if (qspi_clk) {
 435                         prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 436                         if (prescaler > 255)
 437                                 prescaler = 255;
 438                 }
 439         }
 440
 441         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 442         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 443
 444         ret = _stm32_qspi_wait_for_not_busy(priv);
 445         if (ret)
 446                 return ret;
 447
 448         clrsetbits_le32(&priv->regs->cr,
 449                         STM32_QSPI_CR_PRESCALER_MASK <<
 450                         STM32_QSPI_CR_PRESCALER_SHIFT,
 451                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 452
 453         clrsetbits_le32(&priv->regs->dcr,
 454                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 455                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
 456
 457         dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs,
 458                 (qspi_clk / (prescaler + 1)));
 459
 460         return 0;
 461 }
 462
 463 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
 464 {
 465         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 466         int ret;
 467         const char *str_rx, *str_tx;
 468
 469         ret = _stm32_qspi_wait_for_not_busy(priv);
 470         if (ret)
 471                 return ret;
 472
 473         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
 474                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 475         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
 476                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 477         else
 478                 return -ENODEV;
 479
 480         if (mode & SPI_CS_HIGH)
 481                 return -ENODEV;
 482
 483         if (mode & SPI_RX_QUAD)
 484                 str_rx = "quad";
 485         else if (mode & SPI_RX_DUAL)
 486                 str_rx = "dual";
 487         else
 488                 str_rx = "single";
 489
 490         if (mode & SPI_TX_QUAD)
 491                 str_tx = "quad";
 492         else if (mode & SPI_TX_DUAL)
 493                 str_tx = "dual";
 494         else
 495                 str_tx = "single";
 496
 497         dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n",
 498                 priv->regs, mode, str_rx, str_tx);
 499
 500         return 0;
 501 }
 502
 503 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 504         .exec_op = stm32_qspi_exec_op,
 505 };
 506
 507 static const struct dm_spi_ops stm32_qspi_ops = {
 508         .claim_bus      = stm32_qspi_claim_bus,
 509         .release_bus    = stm32_qspi_release_bus,
 510         .set_speed      = stm32_qspi_set_speed,
 511         .set_mode       = stm32_qspi_set_mode,
 512         .mem_ops        = &stm32_qspi_mem_ops,
 513 };
 514
 515 static const struct udevice_id stm32_qspi_ids[] = {
 516         { .compatible = "st,stm32f469-qspi" },
 517         { }
 518 };
 519
 520 U_BOOT_DRIVER(stm32_qspi) = {
 521         .name = "stm32_qspi",
 522         .id = UCLASS_SPI,
 523         .of_match = stm32_qspi_ids,
 524         .ops = &stm32_qspi_ops,
 525         .priv_auto      = sizeof(struct stm32_qspi_priv),
 526         .probe = stm32_qspi_probe,
 527 };