drivers/spi/stm32_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016
   4  *
   5  * Michael Kurz, <michi.kurz@gmail.com>
   6  *
   7  * STM32 QSPI driver
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <reset.h>
  13 #include <spi-mem.h>
  14 #include <dm/device_compat.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/ioport.h>
  17 #include <linux/sizes.h>
  18
  19 struct stm32_qspi_regs {
  20         u32 cr;         /* 0x00 */
  21         u32 dcr;        /* 0x04 */
  22         u32 sr;         /* 0x08 */
  23         u32 fcr;        /* 0x0C */
  24         u32 dlr;        /* 0x10 */
  25         u32 ccr;        /* 0x14 */
  26         u32 ar;         /* 0x18 */
  27         u32 abr;        /* 0x1C */
  28         u32 dr;         /* 0x20 */
  29         u32 psmkr;      /* 0x24 */
  30         u32 psmar;      /* 0x28 */
  31         u32 pir;        /* 0x2C */
  32         u32 lptr;       /* 0x30 */
  33 };
  34
  35 /*
  36  * QUADSPI control register
  37  */
  38 #define STM32_QSPI_CR_EN                BIT(0)
  39 #define STM32_QSPI_CR_ABORT             BIT(1)
  40 #define STM32_QSPI_CR_DMAEN             BIT(2)
  41 #define STM32_QSPI_CR_TCEN              BIT(3)
  42 #define STM32_QSPI_CR_SSHIFT            BIT(4)
  43 #define STM32_QSPI_CR_DFM               BIT(6)
  44 #define STM32_QSPI_CR_FSEL              BIT(7)
  45 #define STM32_QSPI_CR_FTHRES_SHIFT      8
  46 #define STM32_QSPI_CR_TEIE              BIT(16)
  47 #define STM32_QSPI_CR_TCIE              BIT(17)
  48 #define STM32_QSPI_CR_FTIE              BIT(18)
  49 #define STM32_QSPI_CR_SMIE              BIT(19)
  50 #define STM32_QSPI_CR_TOIE              BIT(20)
  51 #define STM32_QSPI_CR_APMS              BIT(22)
  52 #define STM32_QSPI_CR_PMM               BIT(23)
  53 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
  54 #define STM32_QSPI_CR_PRESCALER_SHIFT   24
  55
  56 /*
  57  * QUADSPI device configuration register
  58  */
  59 #define STM32_QSPI_DCR_CKMODE           BIT(0)
  60 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
  61 #define STM32_QSPI_DCR_CSHT_SHIFT       8
  62 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
  63 #define STM32_QSPI_DCR_FSIZE_SHIFT      16
  64
  65 /*
  66  * QUADSPI status register
  67  */
  68 #define STM32_QSPI_SR_TEF               BIT(0)
  69 #define STM32_QSPI_SR_TCF               BIT(1)
  70 #define STM32_QSPI_SR_FTF               BIT(2)
  71 #define STM32_QSPI_SR_SMF               BIT(3)
  72 #define STM32_QSPI_SR_TOF               BIT(4)
  73 #define STM32_QSPI_SR_BUSY              BIT(5)
  74
  75 /*
  76  * QUADSPI flag clear register
  77  */
  78 #define STM32_QSPI_FCR_CTEF             BIT(0)
  79 #define STM32_QSPI_FCR_CTCF             BIT(1)
  80 #define STM32_QSPI_FCR_CSMF             BIT(3)
  81 #define STM32_QSPI_FCR_CTOF             BIT(4)
  82
  83 /*
  84  * QUADSPI communication configuration register
  85  */
  86 #define STM32_QSPI_CCR_DDRM             BIT(31)
  87 #define STM32_QSPI_CCR_DHHC             BIT(30)
  88 #define STM32_QSPI_CCR_SIOO             BIT(28)
  89 #define STM32_QSPI_CCR_FMODE_SHIFT      26
  90 #define STM32_QSPI_CCR_DMODE_SHIFT      24
  91 #define STM32_QSPI_CCR_DCYC_SHIFT       18
  92 #define STM32_QSPI_CCR_ABSIZE_SHIFT     16
  93 #define STM32_QSPI_CCR_ABMODE_SHIFT     14
  94 #define STM32_QSPI_CCR_ADSIZE_SHIFT     12
  95 #define STM32_QSPI_CCR_ADMODE_SHIFT     10
  96 #define STM32_QSPI_CCR_IMODE_SHIFT      8
  97
  98 #define STM32_QSPI_CCR_IND_WRITE        0
  99 #define STM32_QSPI_CCR_IND_READ         1
 100 #define STM32_QSPI_CCR_MEM_MAP          3
 101
 102 #define STM32_QSPI_MAX_MMAP_SZ          SZ_256M
 103 #define STM32_QSPI_MAX_CHIP             2
 104
 105 #define STM32_QSPI_FIFO_TIMEOUT_US      30000
 106 #define STM32_QSPI_CMD_TIMEOUT_US       1000000
 107 #define STM32_BUSY_TIMEOUT_US           100000
 108 #define STM32_ABT_TIMEOUT_US            100000
 109
 110 struct stm32_qspi_flash {
 111         u32 cr;
 112         u32 dcr;
 113         bool initialized;
 114 };
 115
 116 struct stm32_qspi_priv {
 117         struct stm32_qspi_regs *regs;
 118         struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
 119         void __iomem *mm_base;
 120         resource_size_t mm_size;
 121         ulong clock_rate;
 122         int cs_used;
 123 };
 124
 125 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
 126 {
 127         u32 sr;
 128         int ret;
 129
 130         ret = readl_poll_timeout(&priv->regs->sr, sr,
 131                                  !(sr & STM32_QSPI_SR_BUSY),
 132                                  STM32_BUSY_TIMEOUT_US);
 133         if (ret)
 134                 pr_err("busy timeout (stat:%#x)\n", sr);
 135
 136         return ret;
 137 }
 138
 139 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
 140                                 const struct spi_mem_op *op)
 141 {
 142         u32 sr;
 143         int ret;
 144
 145         if (!op->data.nbytes)
 146                 return _stm32_qspi_wait_for_not_busy(priv);
 147
 148         ret = readl_poll_timeout(&priv->regs->sr, sr,
 149                                  sr & STM32_QSPI_SR_TCF,
 150                                  STM32_QSPI_CMD_TIMEOUT_US);
 151         if (ret) {
 152                 pr_err("cmd timeout (stat:%#x)\n", sr);
 153         } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
 154                 pr_err("transfer error (stat:%#x)\n", sr);
 155                 ret = -EIO;
 156         }
 157
 158         /* clear flags */
 159         writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
 160
 161         return ret;
 162 }
 163
 164 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 165 {
 166         *val = readb(addr);
 167 }
 168
 169 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 170 {
 171         writeb(*val, addr);
 172 }
 173
 174 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
 175                             const struct spi_mem_op *op)
 176 {
 177         void (*fifo)(u8 *val, void __iomem *addr);
 178         u32 len = op->data.nbytes, sr;
 179         u8 *buf;
 180         int ret;
 181
 182         if (op->data.dir == SPI_MEM_DATA_IN) {
 183                 fifo = _stm32_qspi_read_fifo;
 184                 buf = op->data.buf.in;
 185
 186         } else {
 187                 fifo = _stm32_qspi_write_fifo;
 188                 buf = (u8 *)op->data.buf.out;
 189         }
 190
 191         while (len--) {
 192                 ret = readl_poll_timeout(&priv->regs->sr, sr,
 193                                          sr & STM32_QSPI_SR_FTF,
 194                                          STM32_QSPI_FIFO_TIMEOUT_US);
 195                 if (ret) {
 196                         pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
 197                         return ret;
 198                 }
 199
 200                 fifo(buf++, &priv->regs->dr);
 201         }
 202
 203         return 0;
 204 }
 205
 206 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
 207                          const struct spi_mem_op *op)
 208 {
 209         memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
 210                       op->data.nbytes);
 211
 212         return 0;
 213 }
 214
 215 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
 216                           const struct spi_mem_op *op,
 217                           u8 mode)
 218 {
 219         if (!op->data.nbytes)
 220                 return 0;
 221
 222         if (mode == STM32_QSPI_CCR_MEM_MAP)
 223                 return stm32_qspi_mm(priv, op);
 224
 225         return _stm32_qspi_poll(priv, op);
 226 }
 227
 228 static int _stm32_qspi_get_mode(u8 buswidth)
 229 {
 230         if (buswidth == 4)
 231                 return 3;
 232
 233         return buswidth;
 234 }
 235
 236 static int stm32_qspi_exec_op(struct spi_slave *slave,
 237                               const struct spi_mem_op *op)
 238 {
 239         struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 240         u32 cr, ccr, addr_max;
 241         u8 mode = STM32_QSPI_CCR_IND_WRITE;
 242         int timeout, ret;
 243
 244         debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 245               __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 246               op->dummy.buswidth, op->data.buswidth,
 247               op->addr.val, op->data.nbytes);
 248
 249         ret = _stm32_qspi_wait_for_not_busy(priv);
 250         if (ret)
 251                 return ret;
 252
 253         addr_max = op->addr.val + op->data.nbytes + 1;
 254
 255         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
 256                 if (addr_max < priv->mm_size && op->addr.buswidth)
 257                         mode = STM32_QSPI_CCR_MEM_MAP;
 258                 else
 259                         mode = STM32_QSPI_CCR_IND_READ;
 260         }
 261
 262         if (op->data.nbytes)
 263                 writel(op->data.nbytes - 1, &priv->regs->dlr);
 264
 265         ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
 266         ccr |= op->cmd.opcode;
 267         ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
 268                 << STM32_QSPI_CCR_IMODE_SHIFT);
 269
 270         if (op->addr.nbytes) {
 271                 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
 272                 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
 273                         << STM32_QSPI_CCR_ADMODE_SHIFT);
 274         }
 275
 276         if (op->dummy.buswidth && op->dummy.nbytes)
 277                 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
 278                         << STM32_QSPI_CCR_DCYC_SHIFT);
 279
 280         if (op->data.nbytes)
 281                 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
 282                         << STM32_QSPI_CCR_DMODE_SHIFT);
 283
 284         writel(ccr, &priv->regs->ccr);
 285
 286         if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
 287                 writel(op->addr.val, &priv->regs->ar);
 288
 289         ret = _stm32_qspi_tx(priv, op, mode);
 290         /*
 291          * Abort in:
 292          * -error case
 293          * -read memory map: prefetching must be stopped if we read the last
 294          *  byte of device (device size - fifo size). like device size is not
 295          *  knows, the prefetching is always stop.
 296          */
 297         if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
 298                 goto abort;
 299
 300         /* Wait end of tx in indirect mode */
 301         ret = _stm32_qspi_wait_cmd(priv, op);
 302         if (ret)
 303                 goto abort;
 304
 305         return 0;
 306
 307 abort:
 308         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
 309
 310         /* Wait clear of abort bit by hw */
 311         timeout = readl_poll_timeout(&priv->regs->cr, cr,
 312                                      !(cr & STM32_QSPI_CR_ABORT),
 313                                      STM32_ABT_TIMEOUT_US);
 314
 315         writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
 316
 317         if (ret || timeout)
 318                 pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
 319
 320         return ret;
 321 }
 322
 323 static int stm32_qspi_probe(struct udevice *bus)
 324 {
 325         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 326         struct resource res;
 327         struct clk clk;
 328         struct reset_ctl reset_ctl;
 329         int ret;
 330
 331         ret = dev_read_resource_byname(bus, "qspi", &res);
 332         if (ret) {
 333                 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
 334                 return ret;
 335         }
 336
 337         priv->regs = (struct stm32_qspi_regs *)res.start;
 338
 339         ret = dev_read_resource_byname(bus, "qspi_mm", &res);
 340         if (ret) {
 341                 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
 342                 return ret;
 343         }
 344
 345         priv->mm_base = (void __iomem *)res.start;
 346
 347         priv->mm_size = resource_size(&res);
 348         if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
 349                 return -EINVAL;
 350
 351         debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
 352               __func__, priv->regs, priv->mm_base, priv->mm_size);
 353
 354         ret = clk_get_by_index(bus, 0, &clk);
 355         if (ret < 0)
 356                 return ret;
 357
 358         ret = clk_enable(&clk);
 359         if (ret) {
 360                 dev_err(bus, "failed to enable clock\n");
 361                 return ret;
 362         }
 363
 364         priv->clock_rate = clk_get_rate(&clk);
 365         if (!priv->clock_rate) {
 366                 clk_disable(&clk);
 367                 return -EINVAL;
 368         }
 369
 370         ret = reset_get_by_index(bus, 0, &reset_ctl);
 371         if (ret) {
 372                 if (ret != -ENOENT) {
 373                         dev_err(bus, "failed to get reset\n");
 374                         clk_disable(&clk);
 375                         return ret;
 376                 }
 377         } else {
 378                 /* Reset QSPI controller */
 379                 reset_assert(&reset_ctl);
 380                 udelay(2);
 381                 reset_deassert(&reset_ctl);
 382         }
 383
 384         priv->cs_used = -1;
 385
 386         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 387
 388         /* Set dcr fsize to max address */
 389         setbits_le32(&priv->regs->dcr,
 390                      STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
 391
 392         return 0;
 393 }
 394
 395 static int stm32_qspi_claim_bus(struct udevice *dev)
 396 {
 397         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 398         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 399         int slave_cs = slave_plat->cs;
 400
 401         if (slave_cs >= STM32_QSPI_MAX_CHIP)
 402                 return -ENODEV;
 403
 404         if (priv->cs_used != slave_cs) {
 405                 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
 406
 407                 priv->cs_used = slave_cs;
 408
 409                 if (flash->initialized) {
 410                         /* Set the configuration: speed + cs */
 411                         writel(flash->cr, &priv->regs->cr);
 412                         writel(flash->dcr, &priv->regs->dcr);
 413                 } else {
 414                         /* Set chip select */
 415                         clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
 416                                         priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
 417
 418                         /* Save the configuration: speed + cs */
 419                         flash->cr = readl(&priv->regs->cr);
 420                         flash->dcr = readl(&priv->regs->dcr);
 421
 422                         flash->initialized = true;
 423                 }
 424         }
 425
 426         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 427
 428         return 0;
 429 }
 430
 431 static int stm32_qspi_release_bus(struct udevice *dev)
 432 {
 433         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 434
 435         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 436
 437         return 0;
 438 }
 439
 440 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 441 {
 442         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 443         u32 qspi_clk = priv->clock_rate;
 444         u32 prescaler = 255;
 445         u32 csht;
 446         int ret;
 447
 448         if (speed > 0) {
 449                 prescaler = 0;
 450                 if (qspi_clk) {
 451                         prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 452                         if (prescaler > 255)
 453                                 prescaler = 255;
 454                 }
 455         }
 456
 457         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 458         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 459
 460         ret = _stm32_qspi_wait_for_not_busy(priv);
 461         if (ret)
 462                 return ret;
 463
 464         clrsetbits_le32(&priv->regs->cr,
 465                         STM32_QSPI_CR_PRESCALER_MASK <<
 466                         STM32_QSPI_CR_PRESCALER_SHIFT,
 467                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 468
 469         clrsetbits_le32(&priv->regs->dcr,
 470                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 471                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
 472
 473         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
 474               (qspi_clk / (prescaler + 1)));
 475
 476         return 0;
 477 }
 478
 479 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
 480 {
 481         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 482         int ret;
 483
 484         ret = _stm32_qspi_wait_for_not_busy(priv);
 485         if (ret)
 486                 return ret;
 487
 488         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
 489                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 490         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
 491                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 492         else
 493                 return -ENODEV;
 494
 495         if (mode & SPI_CS_HIGH)
 496                 return -ENODEV;
 497
 498         debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
 499
 500         if (mode & SPI_RX_QUAD)
 501                 debug("quad, tx: ");
 502         else if (mode & SPI_RX_DUAL)
 503                 debug("dual, tx: ");
 504         else
 505                 debug("single, tx: ");
 506
 507         if (mode & SPI_TX_QUAD)
 508                 debug("quad\n");
 509         else if (mode & SPI_TX_DUAL)
 510                 debug("dual\n");
 511         else
 512                 debug("single\n");
 513
 514         return 0;
 515 }
 516
 517 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 518         .exec_op = stm32_qspi_exec_op,
 519 };
 520
 521 static const struct dm_spi_ops stm32_qspi_ops = {
 522         .claim_bus      = stm32_qspi_claim_bus,
 523         .release_bus    = stm32_qspi_release_bus,
 524         .set_speed      = stm32_qspi_set_speed,
 525         .set_mode       = stm32_qspi_set_mode,
 526         .mem_ops        = &stm32_qspi_mem_ops,
 527 };
 528
 529 static const struct udevice_id stm32_qspi_ids[] = {
 530         { .compatible = "st,stm32f469-qspi" },
 531         { }
 532 };
 533
 534 U_BOOT_DRIVER(stm32_qspi) = {
 535         .name = "stm32_qspi",
 536         .id = UCLASS_SPI,
 537         .of_match = stm32_qspi_ids,
 538         .ops = &stm32_qspi_ops,
 539         .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
 540         .probe = stm32_qspi_probe,
 541 };