drivers/spi/stm32_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016
   4  *
   5  * Michael Kurz, <michi.kurz@gmail.com>
   6  *
   7  * STM32 QSPI driver
   8  */
   9
  10 #define LOG_CATEGORY UCLASS_SPI
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <dm.h>
  15 #include <log.h>
  16 #include <reset.h>
  17 #include <spi.h>
  18 #include <spi-mem.h>
  19 #include <watchdog.h>
  20 #include <dm/device_compat.h>
  21 #include <linux/bitops.h>
  22 #include <linux/delay.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sizes.h>
  26
  27 struct stm32_qspi_regs {
  28         u32 cr;         /* 0x00 */
  29         u32 dcr;        /* 0x04 */
  30         u32 sr;         /* 0x08 */
  31         u32 fcr;        /* 0x0C */
  32         u32 dlr;        /* 0x10 */
  33         u32 ccr;        /* 0x14 */
  34         u32 ar;         /* 0x18 */
  35         u32 abr;        /* 0x1C */
  36         u32 dr;         /* 0x20 */
  37         u32 psmkr;      /* 0x24 */
  38         u32 psmar;      /* 0x28 */
  39         u32 pir;        /* 0x2C */
  40         u32 lptr;       /* 0x30 */
  41 };
  42
  43 /*
  44  * QUADSPI control register
  45  */
  46 #define STM32_QSPI_CR_EN                BIT(0)
  47 #define STM32_QSPI_CR_ABORT             BIT(1)
  48 #define STM32_QSPI_CR_DMAEN             BIT(2)
  49 #define STM32_QSPI_CR_TCEN              BIT(3)
  50 #define STM32_QSPI_CR_SSHIFT            BIT(4)
  51 #define STM32_QSPI_CR_DFM               BIT(6)
  52 #define STM32_QSPI_CR_FSEL              BIT(7)
  53 #define STM32_QSPI_CR_FTHRES_SHIFT      8
  54 #define STM32_QSPI_CR_TEIE              BIT(16)
  55 #define STM32_QSPI_CR_TCIE              BIT(17)
  56 #define STM32_QSPI_CR_FTIE              BIT(18)
  57 #define STM32_QSPI_CR_SMIE              BIT(19)
  58 #define STM32_QSPI_CR_TOIE              BIT(20)
  59 #define STM32_QSPI_CR_APMS              BIT(22)
  60 #define STM32_QSPI_CR_PMM               BIT(23)
  61 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
  62 #define STM32_QSPI_CR_PRESCALER_SHIFT   24
  63
  64 /*
  65  * QUADSPI device configuration register
  66  */
  67 #define STM32_QSPI_DCR_CKMODE           BIT(0)
  68 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
  69 #define STM32_QSPI_DCR_CSHT_SHIFT       8
  70 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
  71 #define STM32_QSPI_DCR_FSIZE_SHIFT      16
  72
  73 /*
  74  * QUADSPI status register
  75  */
  76 #define STM32_QSPI_SR_TEF               BIT(0)
  77 #define STM32_QSPI_SR_TCF               BIT(1)
  78 #define STM32_QSPI_SR_FTF               BIT(2)
  79 #define STM32_QSPI_SR_SMF               BIT(3)
  80 #define STM32_QSPI_SR_TOF               BIT(4)
  81 #define STM32_QSPI_SR_BUSY              BIT(5)
  82
  83 /*
  84  * QUADSPI flag clear register
  85  */
  86 #define STM32_QSPI_FCR_CTEF             BIT(0)
  87 #define STM32_QSPI_FCR_CTCF             BIT(1)
  88 #define STM32_QSPI_FCR_CSMF             BIT(3)
  89 #define STM32_QSPI_FCR_CTOF             BIT(4)
  90
  91 /*
  92  * QUADSPI communication configuration register
  93  */
  94 #define STM32_QSPI_CCR_DDRM             BIT(31)
  95 #define STM32_QSPI_CCR_DHHC             BIT(30)
  96 #define STM32_QSPI_CCR_SIOO             BIT(28)
  97 #define STM32_QSPI_CCR_FMODE_SHIFT      26
  98 #define STM32_QSPI_CCR_DMODE_SHIFT      24
  99 #define STM32_QSPI_CCR_DCYC_SHIFT       18
 100 #define STM32_QSPI_CCR_ABSIZE_SHIFT     16
 101 #define STM32_QSPI_CCR_ABMODE_SHIFT     14
 102 #define STM32_QSPI_CCR_ADSIZE_SHIFT     12
 103 #define STM32_QSPI_CCR_ADMODE_SHIFT     10
 104 #define STM32_QSPI_CCR_IMODE_SHIFT      8
 105
 106 #define STM32_QSPI_CCR_IND_WRITE        0
 107 #define STM32_QSPI_CCR_IND_READ         1
 108 #define STM32_QSPI_CCR_MEM_MAP          3
 109
 110 #define STM32_QSPI_MAX_MMAP_SZ          SZ_256M
 111 #define STM32_QSPI_MAX_CHIP             2
 112
 113 #define STM32_QSPI_FIFO_TIMEOUT_US      30000
 114 #define STM32_QSPI_CMD_TIMEOUT_US       1000000
 115 #define STM32_BUSY_TIMEOUT_US           100000
 116 #define STM32_ABT_TIMEOUT_US            100000
 117
 118 struct stm32_qspi_flash {
 119         u32 cr;
 120         u32 dcr;
 121         bool initialized;
 122 };
 123
 124 struct stm32_qspi_priv {
 125         struct stm32_qspi_regs *regs;
 126         struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
 127         void __iomem *mm_base;
 128         resource_size_t mm_size;
 129         ulong clock_rate;
 130         int cs_used;
 131 };
 132
 133 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
 134 {
 135         u32 sr;
 136         int ret;
 137
 138         ret = readl_poll_timeout(&priv->regs->sr, sr,
 139                                  !(sr & STM32_QSPI_SR_BUSY),
 140                                  STM32_BUSY_TIMEOUT_US);
 141         if (ret)
 142                 log_err("busy timeout (stat:%#x)\n", sr);
 143
 144         return ret;
 145 }
 146
 147 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
 148                                 const struct spi_mem_op *op)
 149 {
 150         u32 sr;
 151         int ret;
 152
 153         if (!op->data.nbytes)
 154                 return _stm32_qspi_wait_for_not_busy(priv);
 155
 156         ret = readl_poll_timeout(&priv->regs->sr, sr,
 157                                  sr & STM32_QSPI_SR_TCF,
 158                                  STM32_QSPI_CMD_TIMEOUT_US);
 159         if (ret) {
 160                 log_err("cmd timeout (stat:%#x)\n", sr);
 161         } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
 162                 log_err("transfer error (stat:%#x)\n", sr);
 163                 ret = -EIO;
 164         }
 165
 166         /* clear flags */
 167         writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
 168
 169         return ret;
 170 }
 171
 172 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 173 {
 174         *val = readb(addr);
 175         WATCHDOG_RESET();
 176 }
 177
 178 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 179 {
 180         writeb(*val, addr);
 181 }
 182
 183 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
 184                             const struct spi_mem_op *op)
 185 {
 186         void (*fifo)(u8 *val, void __iomem *addr);
 187         u32 len = op->data.nbytes, sr;
 188         u8 *buf;
 189         int ret;
 190
 191         if (op->data.dir == SPI_MEM_DATA_IN) {
 192                 fifo = _stm32_qspi_read_fifo;
 193                 buf = op->data.buf.in;
 194
 195         } else {
 196                 fifo = _stm32_qspi_write_fifo;
 197                 buf = (u8 *)op->data.buf.out;
 198         }
 199
 200         while (len--) {
 201                 ret = readl_poll_timeout(&priv->regs->sr, sr,
 202                                          sr & STM32_QSPI_SR_FTF,
 203                                          STM32_QSPI_FIFO_TIMEOUT_US);
 204                 if (ret) {
 205                         log_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
 206                         return ret;
 207                 }
 208
 209                 fifo(buf++, &priv->regs->dr);
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
 216                          const struct spi_mem_op *op)
 217 {
 218         memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
 219                       op->data.nbytes);
 220
 221         return 0;
 222 }
 223
 224 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
 225                           const struct spi_mem_op *op,
 226                           u8 mode)
 227 {
 228         if (!op->data.nbytes)
 229                 return 0;
 230
 231         if (mode == STM32_QSPI_CCR_MEM_MAP)
 232                 return stm32_qspi_mm(priv, op);
 233
 234         return _stm32_qspi_poll(priv, op);
 235 }
 236
 237 static int _stm32_qspi_get_mode(u8 buswidth)
 238 {
 239         if (buswidth == 4)
 240                 return 3;
 241
 242         return buswidth;
 243 }
 244
 245 static int stm32_qspi_exec_op(struct spi_slave *slave,
 246                               const struct spi_mem_op *op)
 247 {
 248         struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 249         u32 cr, ccr, addr_max;
 250         u8 mode = STM32_QSPI_CCR_IND_WRITE;
 251         int timeout, ret;
 252
 253         dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 254                 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 255                 op->dummy.buswidth, op->data.buswidth,
 256                 op->addr.val, op->data.nbytes);
 257
 258         ret = _stm32_qspi_wait_for_not_busy(priv);
 259         if (ret)
 260                 return ret;
 261
 262         addr_max = op->addr.val + op->data.nbytes + 1;
 263
 264         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
 265                 if (addr_max < priv->mm_size && op->addr.buswidth)
 266                         mode = STM32_QSPI_CCR_MEM_MAP;
 267                 else
 268                         mode = STM32_QSPI_CCR_IND_READ;
 269         }
 270
 271         if (op->data.nbytes)
 272                 writel(op->data.nbytes - 1, &priv->regs->dlr);
 273
 274         ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
 275         ccr |= op->cmd.opcode;
 276         ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
 277                 << STM32_QSPI_CCR_IMODE_SHIFT);
 278
 279         if (op->addr.nbytes) {
 280                 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
 281                 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
 282                         << STM32_QSPI_CCR_ADMODE_SHIFT);
 283         }
 284
 285         if (op->dummy.buswidth && op->dummy.nbytes)
 286                 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
 287                         << STM32_QSPI_CCR_DCYC_SHIFT);
 288
 289         if (op->data.nbytes)
 290                 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
 291                         << STM32_QSPI_CCR_DMODE_SHIFT);
 292
 293         writel(ccr, &priv->regs->ccr);
 294
 295         if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
 296                 writel(op->addr.val, &priv->regs->ar);
 297
 298         ret = _stm32_qspi_tx(priv, op, mode);
 299         /*
 300          * Abort in:
 301          * -error case
 302          * -read memory map: prefetching must be stopped if we read the last
 303          *  byte of device (device size - fifo size). like device size is not
 304          *  knows, the prefetching is always stop.
 305          */
 306         if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
 307                 goto abort;
 308
 309         /* Wait end of tx in indirect mode */
 310         ret = _stm32_qspi_wait_cmd(priv, op);
 311         if (ret)
 312                 goto abort;
 313
 314         return 0;
 315
 316 abort:
 317         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
 318
 319         /* Wait clear of abort bit by hw */
 320         timeout = readl_poll_timeout(&priv->regs->cr, cr,
 321                                      !(cr & STM32_QSPI_CR_ABORT),
 322                                      STM32_ABT_TIMEOUT_US);
 323
 324         writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
 325
 326         if (ret || timeout)
 327                 dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout);
 328
 329         return ret;
 330 }
 331
 332 static int stm32_qspi_probe(struct udevice *bus)
 333 {
 334         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 335         struct resource res;
 336         struct clk clk;
 337         struct reset_ctl reset_ctl;
 338         int ret;
 339
 340         ret = dev_read_resource_byname(bus, "qspi", &res);
 341         if (ret) {
 342                 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
 343                 return ret;
 344         }
 345
 346         priv->regs = (struct stm32_qspi_regs *)res.start;
 347
 348         ret = dev_read_resource_byname(bus, "qspi_mm", &res);
 349         if (ret) {
 350                 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
 351                 return ret;
 352         }
 353
 354         priv->mm_base = (void __iomem *)res.start;
 355
 356         priv->mm_size = resource_size(&res);
 357         if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
 358                 return -EINVAL;
 359
 360         dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
 361                 priv->regs, priv->mm_base, priv->mm_size);
 362
 363         ret = clk_get_by_index(bus, 0, &clk);
 364         if (ret < 0)
 365                 return ret;
 366
 367         ret = clk_enable(&clk);
 368         if (ret) {
 369                 dev_err(bus, "failed to enable clock\n");
 370                 return ret;
 371         }
 372
 373         priv->clock_rate = clk_get_rate(&clk);
 374         if (!priv->clock_rate) {
 375                 clk_disable(&clk);
 376                 return -EINVAL;
 377         }
 378
 379         ret = reset_get_by_index(bus, 0, &reset_ctl);
 380         if (ret) {
 381                 if (ret != -ENOENT) {
 382                         dev_err(bus, "failed to get reset\n");
 383                         clk_disable(&clk);
 384                         return ret;
 385                 }
 386         } else {
 387                 /* Reset QSPI controller */
 388                 reset_assert(&reset_ctl);
 389                 udelay(2);
 390                 reset_deassert(&reset_ctl);
 391         }
 392
 393         priv->cs_used = -1;
 394
 395         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 396
 397         /* Set dcr fsize to max address */
 398         setbits_le32(&priv->regs->dcr,
 399                      STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
 400
 401         return 0;
 402 }
 403
 404 static int stm32_qspi_claim_bus(struct udevice *dev)
 405 {
 406         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 407         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 408         int slave_cs = slave_plat->cs;
 409
 410         if (slave_cs >= STM32_QSPI_MAX_CHIP)
 411                 return -ENODEV;
 412
 413         if (priv->cs_used != slave_cs) {
 414                 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
 415
 416                 priv->cs_used = slave_cs;
 417
 418                 if (flash->initialized) {
 419                         /* Set the configuration: speed + cs */
 420                         writel(flash->cr, &priv->regs->cr);
 421                         writel(flash->dcr, &priv->regs->dcr);
 422                 } else {
 423                         /* Set chip select */
 424                         clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
 425                                         priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
 426
 427                         /* Save the configuration: speed + cs */
 428                         flash->cr = readl(&priv->regs->cr);
 429                         flash->dcr = readl(&priv->regs->dcr);
 430
 431                         flash->initialized = true;
 432                 }
 433         }
 434
 435         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 436
 437         return 0;
 438 }
 439
 440 static int stm32_qspi_release_bus(struct udevice *dev)
 441 {
 442         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 443
 444         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 445
 446         return 0;
 447 }
 448
 449 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 450 {
 451         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 452         u32 qspi_clk = priv->clock_rate;
 453         u32 prescaler = 255;
 454         u32 csht;
 455         int ret;
 456
 457         if (speed > 0) {
 458                 prescaler = 0;
 459                 if (qspi_clk) {
 460                         prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 461                         if (prescaler > 255)
 462                                 prescaler = 255;
 463                 }
 464         }
 465
 466         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 467         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 468
 469         ret = _stm32_qspi_wait_for_not_busy(priv);
 470         if (ret)
 471                 return ret;
 472
 473         clrsetbits_le32(&priv->regs->cr,
 474                         STM32_QSPI_CR_PRESCALER_MASK <<
 475                         STM32_QSPI_CR_PRESCALER_SHIFT,
 476                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 477
 478         clrsetbits_le32(&priv->regs->dcr,
 479                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 480                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
 481
 482         dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs,
 483                 (qspi_clk / (prescaler + 1)));
 484
 485         return 0;
 486 }
 487
 488 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
 489 {
 490         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 491         int ret;
 492         const char *str_rx, *str_tx;
 493
 494         ret = _stm32_qspi_wait_for_not_busy(priv);
 495         if (ret)
 496                 return ret;
 497
 498         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
 499                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 500         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
 501                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 502         else
 503                 return -ENODEV;
 504
 505         if (mode & SPI_CS_HIGH)
 506                 return -ENODEV;
 507
 508         if (mode & SPI_RX_QUAD)
 509                 str_rx = "quad";
 510         else if (mode & SPI_RX_DUAL)
 511                 str_rx = "dual";
 512         else
 513                 str_rx = "single";
 514
 515         if (mode & SPI_TX_QUAD)
 516                 str_tx = "quad";
 517         else if (mode & SPI_TX_DUAL)
 518                 str_tx = "dual";
 519         else
 520                 str_tx = "single";
 521
 522         dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n",
 523                 priv->regs, mode, str_rx, str_tx);
 524
 525         return 0;
 526 }
 527
 528 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 529         .exec_op = stm32_qspi_exec_op,
 530 };
 531
 532 static const struct dm_spi_ops stm32_qspi_ops = {
 533         .claim_bus      = stm32_qspi_claim_bus,
 534         .release_bus    = stm32_qspi_release_bus,
 535         .set_speed      = stm32_qspi_set_speed,
 536         .set_mode       = stm32_qspi_set_mode,
 537         .mem_ops        = &stm32_qspi_mem_ops,
 538 };
 539
 540 static const struct udevice_id stm32_qspi_ids[] = {
 541         { .compatible = "st,stm32f469-qspi" },
 542         { }
 543 };
 544
 545 U_BOOT_DRIVER(stm32_qspi) = {
 546         .name = "stm32_qspi",
 547         .id = UCLASS_SPI,
 548         .of_match = stm32_qspi_ids,
 549         .ops = &stm32_qspi_ops,
 550         .priv_auto      = sizeof(struct stm32_qspi_priv),
 551         .probe = stm32_qspi_probe,
 552 };