spi: stm32_qspi: Add chip select management
[platform/kernel/u-boot.git] / drivers / spi / stm32_qspi.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2016
4  *
5  * Michael Kurz, <michi.kurz@gmail.com>
6  *
7  * STM32 QSPI driver
8  */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <malloc.h>
15 #include <spi.h>
16 #include <spi_flash.h>
17 #include <asm/io.h>
18 #include <asm/arch/stm32.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 struct stm32_qspi_regs {
23         u32 cr;         /* 0x00 */
24         u32 dcr;        /* 0x04 */
25         u32 sr;         /* 0x08 */
26         u32 fcr;        /* 0x0C */
27         u32 dlr;        /* 0x10 */
28         u32 ccr;        /* 0x14 */
29         u32 ar;         /* 0x18 */
30         u32 abr;        /* 0x1C */
31         u32 dr;         /* 0x20 */
32         u32 psmkr;      /* 0x24 */
33         u32 psmar;      /* 0x28 */
34         u32 pir;        /* 0x2C */
35         u32 lptr;       /* 0x30 */
36 };
37
38 /*
39  * QUADSPI control register
40  */
41 #define STM32_QSPI_CR_EN                BIT(0)
42 #define STM32_QSPI_CR_ABORT             BIT(1)
43 #define STM32_QSPI_CR_DMAEN             BIT(2)
44 #define STM32_QSPI_CR_TCEN              BIT(3)
45 #define STM32_QSPI_CR_SSHIFT            BIT(4)
46 #define STM32_QSPI_CR_DFM               BIT(6)
47 #define STM32_QSPI_CR_FSEL              BIT(7)
48 #define STM32_QSPI_CR_FTHRES_MASK       GENMASK(4, 0)
49 #define STM32_QSPI_CR_FTHRES_SHIFT      (8)
50 #define STM32_QSPI_CR_TEIE              BIT(16)
51 #define STM32_QSPI_CR_TCIE              BIT(17)
52 #define STM32_QSPI_CR_FTIE              BIT(18)
53 #define STM32_QSPI_CR_SMIE              BIT(19)
54 #define STM32_QSPI_CR_TOIE              BIT(20)
55 #define STM32_QSPI_CR_APMS              BIT(22)
56 #define STM32_QSPI_CR_PMM               BIT(23)
57 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
58 #define STM32_QSPI_CR_PRESCALER_SHIFT   (24)
59
60 /*
61  * QUADSPI device configuration register
62  */
63 #define STM32_QSPI_DCR_CKMODE           BIT(0)
64 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
65 #define STM32_QSPI_DCR_CSHT_SHIFT       (8)
66 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
67 #define STM32_QSPI_DCR_FSIZE_SHIFT      (16)
68
69 /*
70  * QUADSPI status register
71  */
72 #define STM32_QSPI_SR_TEF               BIT(0)
73 #define STM32_QSPI_SR_TCF               BIT(1)
74 #define STM32_QSPI_SR_FTF               BIT(2)
75 #define STM32_QSPI_SR_SMF               BIT(3)
76 #define STM32_QSPI_SR_TOF               BIT(4)
77 #define STM32_QSPI_SR_BUSY              BIT(5)
78 #define STM32_QSPI_SR_FLEVEL_MASK       GENMASK(5, 0)
79 #define STM32_QSPI_SR_FLEVEL_SHIFT      (8)
80
81 /*
82  * QUADSPI flag clear register
83  */
84 #define STM32_QSPI_FCR_CTEF             BIT(0)
85 #define STM32_QSPI_FCR_CTCF             BIT(1)
86 #define STM32_QSPI_FCR_CSMF             BIT(3)
87 #define STM32_QSPI_FCR_CTOF             BIT(4)
88
89 /*
90  * QUADSPI communication configuration register
91  */
92 #define STM32_QSPI_CCR_DDRM             BIT(31)
93 #define STM32_QSPI_CCR_DHHC             BIT(30)
94 #define STM32_QSPI_CCR_SIOO             BIT(28)
95 #define STM32_QSPI_CCR_FMODE_SHIFT      (26)
96 #define STM32_QSPI_CCR_DMODE_SHIFT      (24)
97 #define STM32_QSPI_CCR_DCYC_SHIFT       (18)
98 #define STM32_QSPI_CCR_DCYC_MASK        GENMASK(4, 0)
99 #define STM32_QSPI_CCR_ABSIZE_SHIFT     (16)
100 #define STM32_QSPI_CCR_ABMODE_SHIFT     (14)
101 #define STM32_QSPI_CCR_ADSIZE_SHIFT     (12)
102 #define STM32_QSPI_CCR_ADMODE_SHIFT     (10)
103 #define STM32_QSPI_CCR_IMODE_SHIFT      (8)
104 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
105
106 enum STM32_QSPI_CCR_IMODE {
107         STM32_QSPI_CCR_IMODE_NONE = 0,
108         STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
109         STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
110         STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
111 };
112
113 enum STM32_QSPI_CCR_ADMODE {
114         STM32_QSPI_CCR_ADMODE_NONE = 0,
115         STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
116         STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
117         STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
118 };
119
120 enum STM32_QSPI_CCR_ADSIZE {
121         STM32_QSPI_CCR_ADSIZE_8BIT = 0,
122         STM32_QSPI_CCR_ADSIZE_16BIT = 1,
123         STM32_QSPI_CCR_ADSIZE_24BIT = 2,
124         STM32_QSPI_CCR_ADSIZE_32BIT = 3,
125 };
126
127 enum STM32_QSPI_CCR_ABMODE {
128         STM32_QSPI_CCR_ABMODE_NONE = 0,
129         STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
130         STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
131         STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
132 };
133
134 enum STM32_QSPI_CCR_ABSIZE {
135         STM32_QSPI_CCR_ABSIZE_8BIT = 0,
136         STM32_QSPI_CCR_ABSIZE_16BIT = 1,
137         STM32_QSPI_CCR_ABSIZE_24BIT = 2,
138         STM32_QSPI_CCR_ABSIZE_32BIT = 3,
139 };
140
141 enum STM32_QSPI_CCR_DMODE {
142         STM32_QSPI_CCR_DMODE_NONE = 0,
143         STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
144         STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
145         STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
146 };
147
148 enum STM32_QSPI_CCR_FMODE {
149         STM32_QSPI_CCR_IND_WRITE = 0,
150         STM32_QSPI_CCR_IND_READ = 1,
151         STM32_QSPI_CCR_AUTO_POLL = 2,
152         STM32_QSPI_CCR_MEM_MAP = 3,
153 };
154
155 /* default SCK frequency, unit: HZ */
156 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
157
158 #define STM32_MAX_NORCHIP 2
159
160 struct stm32_qspi_platdata {
161         u32 base;
162         u32 memory_map;
163         u32 max_hz;
164 };
165
166 struct stm32_qspi_priv {
167         struct stm32_qspi_regs *regs;
168         ulong clock_rate;
169         u32 max_hz;
170         u32 mode;
171
172         u32 command;
173         u32 address;
174         u32 dummycycles;
175 #define CMD_HAS_ADR     BIT(24)
176 #define CMD_HAS_DUMMY   BIT(25)
177 #define CMD_HAS_DATA    BIT(26)
178 };
179
180 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
181 {
182         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
183 }
184
185 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
186 {
187         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
188 }
189
190 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
191 {
192         while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
193                 ;
194 }
195
196 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
197 {
198         while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
199                 ;
200 }
201
202 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
203 {
204         while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
205                 ;
206 }
207
208 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
209 {
210         u32 fsize = fls(size) - 1;
211
212         clrsetbits_le32(&priv->regs->dcr,
213                         STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
214                         fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
215 }
216
217 static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
218 {
219         clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
220                         cs ? STM32_QSPI_CR_FSEL : 0);
221 }
222
223 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
224 {
225         unsigned int ccr_reg = 0;
226         u8 imode, admode, dmode;
227         u32 mode = priv->mode;
228         u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
229
230         imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
231         admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
232
233         if (mode & SPI_RX_QUAD) {
234                 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
235                 if (mode & SPI_TX_QUAD) {
236                         imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
237                         admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
238                 }
239         } else if (mode & SPI_RX_DUAL) {
240                 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
241                 if (mode & SPI_TX_DUAL) {
242                         imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
243                         admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
244                 }
245         } else {
246                 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
247         }
248
249         if (priv->command & CMD_HAS_DATA)
250                 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
251
252         if (priv->command & CMD_HAS_DUMMY)
253                 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
254                                 << STM32_QSPI_CCR_DCYC_SHIFT);
255
256         if (priv->command & CMD_HAS_ADR) {
257                 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
258                                 << STM32_QSPI_CCR_ADSIZE_SHIFT);
259                 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
260         }
261         ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
262         ccr_reg |= cmd;
263         return ccr_reg;
264 }
265
266 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
267                                     struct spi_flash *flash)
268 {
269         unsigned int ccr_reg;
270
271         priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
272                         | CMD_HAS_DUMMY;
273         priv->dummycycles = flash->dummy_byte * 8;
274
275         ccr_reg = _stm32_qspi_gen_ccr(priv);
276         ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
277
278         _stm32_qspi_wait_for_not_busy(priv);
279
280         writel(ccr_reg, &priv->regs->ccr);
281
282         priv->dummycycles = 0;
283 }
284
285 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
286 {
287         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
288 }
289
290 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
291                                         u32 length)
292 {
293         writel(length - 1, &priv->regs->dlr);
294 }
295
296 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
297 {
298         writel(cr_reg, &priv->regs->ccr);
299
300         if (priv->command & CMD_HAS_ADR)
301                 writel(priv->address, &priv->regs->ar);
302 }
303
304 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
305                             struct spi_flash *flash, unsigned int bitlen,
306                             const u8 *dout, u8 *din, unsigned long flags)
307 {
308         unsigned int words = bitlen / 8;
309         u32 ccr_reg;
310         int i;
311
312         if (flags & SPI_XFER_MMAP) {
313                 _stm32_qspi_enable_mmap(priv, flash);
314                 return 0;
315         } else if (flags & SPI_XFER_MMAP_END) {
316                 _stm32_qspi_disable_mmap(priv);
317                 return 0;
318         }
319
320         if (bitlen == 0)
321                 return -1;
322
323         if (bitlen % 8) {
324                 debug("spi_xfer: Non byte aligned SPI transfer\n");
325                 return -1;
326         }
327
328         if (dout && din) {
329                 debug("spi_xfer: QSPI cannot have data in and data out set\n");
330                 return -1;
331         }
332
333         if (!dout && (flags & SPI_XFER_BEGIN)) {
334                 debug("spi_xfer: QSPI transfer must begin with command\n");
335                 return -1;
336         }
337
338         if (dout) {
339                 if (flags & SPI_XFER_BEGIN) {
340                         /* data is command */
341                         priv->command = dout[0] | CMD_HAS_DATA;
342                         if (words >= 4) {
343                                 /* address is here too */
344                                 priv->address = (dout[1] << 16) |
345                                                 (dout[2] << 8) | dout[3];
346                                 priv->command |= CMD_HAS_ADR;
347                         }
348
349                         if (words > 4) {
350                                 /* rest is dummy bytes */
351                                 priv->dummycycles = (words - 4) * 8;
352                                 priv->command |= CMD_HAS_DUMMY;
353                         }
354
355                         if (flags & SPI_XFER_END) {
356                                 /* command without data */
357                                 priv->command &= ~(CMD_HAS_DATA);
358                         }
359                 }
360
361                 if (flags & SPI_XFER_END) {
362                         ccr_reg = _stm32_qspi_gen_ccr(priv);
363                         ccr_reg |= STM32_QSPI_CCR_IND_WRITE
364                                         << STM32_QSPI_CCR_FMODE_SHIFT;
365
366                         _stm32_qspi_wait_for_not_busy(priv);
367
368                         if (priv->command & CMD_HAS_DATA)
369                                 _stm32_qspi_set_xfer_length(priv, words);
370
371                         _stm32_qspi_start_xfer(priv, ccr_reg);
372
373                         debug("%s: write: ccr:0x%08x adr:0x%08x\n",
374                               __func__, priv->regs->ccr, priv->regs->ar);
375
376                         if (priv->command & CMD_HAS_DATA) {
377                                 _stm32_qspi_wait_for_ftf(priv);
378
379                                 debug("%s: words:%d data:", __func__, words);
380
381                                 i = 0;
382                                 while (words > i) {
383                                         writeb(dout[i], &priv->regs->dr);
384                                         debug("%02x ", dout[i]);
385                                         i++;
386                                 }
387                                 debug("\n");
388
389                                 _stm32_qspi_wait_for_complete(priv);
390                         } else {
391                                 _stm32_qspi_wait_for_not_busy(priv);
392                         }
393                 }
394         } else if (din) {
395                 ccr_reg = _stm32_qspi_gen_ccr(priv);
396                 ccr_reg |= STM32_QSPI_CCR_IND_READ
397                                 << STM32_QSPI_CCR_FMODE_SHIFT;
398
399                 _stm32_qspi_wait_for_not_busy(priv);
400
401                 _stm32_qspi_set_xfer_length(priv, words);
402
403                 _stm32_qspi_start_xfer(priv, ccr_reg);
404
405                 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
406                       priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
407
408                 debug("%s: data:", __func__);
409
410                 i = 0;
411                 while (words > i) {
412                         din[i] = readb(&priv->regs->dr);
413                         debug("%02x ", din[i]);
414                         i++;
415                 }
416                 debug("\n");
417         }
418
419         return 0;
420 }
421
422 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
423 {
424         struct fdt_resource res_regs, res_mem;
425         struct stm32_qspi_platdata *plat = bus->platdata;
426         const void *blob = gd->fdt_blob;
427         int node = dev_of_offset(bus);
428         int ret;
429
430         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
431                                      "qspi", &res_regs);
432         if (ret) {
433                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
434                 return -ENOMEM;
435         }
436         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
437                                      "qspi_mm", &res_mem);
438         if (ret) {
439                 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
440                 return -ENOMEM;
441         }
442
443         plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
444                                         STM32_QSPI_DEFAULT_SCK_FREQ);
445
446         plat->base = res_regs.start;
447         plat->memory_map = res_mem.start;
448
449         debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
450               __func__,
451               plat->base,
452               plat->memory_map,
453               plat->max_hz
454               );
455
456         return 0;
457 }
458
459 static int stm32_qspi_probe(struct udevice *bus)
460 {
461         struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
462         struct stm32_qspi_priv *priv = dev_get_priv(bus);
463         struct dm_spi_bus *dm_spi_bus;
464         struct clk clk;
465         int ret;
466
467         dm_spi_bus = bus->uclass_priv;
468
469         dm_spi_bus->max_hz = plat->max_hz;
470
471         priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
472
473         priv->max_hz = plat->max_hz;
474
475         ret = clk_get_by_index(bus, 0, &clk);
476         if (ret < 0)
477                 return ret;
478
479         ret = clk_enable(&clk);
480
481         if (ret) {
482                 dev_err(bus, "failed to enable clock\n");
483                 return ret;
484         }
485
486         priv->clock_rate = clk_get_rate(&clk);
487         if (priv->clock_rate < 0) {
488                 clk_disable(&clk);
489                 return priv->clock_rate;
490         }
491
492
493         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
494
495         return 0;
496 }
497
498 static int stm32_qspi_remove(struct udevice *bus)
499 {
500         return 0;
501 }
502
503 static int stm32_qspi_claim_bus(struct udevice *dev)
504 {
505         struct stm32_qspi_priv *priv;
506         struct udevice *bus;
507         struct spi_flash *flash;
508         struct dm_spi_slave_platdata *slave_plat;
509
510         bus = dev->parent;
511         priv = dev_get_priv(bus);
512         flash = dev_get_uclass_priv(dev);
513         slave_plat = dev_get_parent_platdata(dev);
514
515         if (slave_plat->cs >= STM32_MAX_NORCHIP)
516                 return -ENODEV;
517
518         _stm32_qspi_set_cs(priv, slave_plat->cs);
519
520         _stm32_qspi_set_flash_size(priv, flash->size);
521
522         _stm32_qspi_enable(priv);
523
524         return 0;
525 }
526
527 static int stm32_qspi_release_bus(struct udevice *dev)
528 {
529         struct stm32_qspi_priv *priv;
530         struct udevice *bus;
531
532         bus = dev->parent;
533         priv = dev_get_priv(bus);
534
535         _stm32_qspi_disable(priv);
536
537         return 0;
538 }
539
540 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
541                            const void *dout, void *din, unsigned long flags)
542 {
543         struct stm32_qspi_priv *priv;
544         struct udevice *bus;
545         struct spi_flash *flash;
546
547         bus = dev->parent;
548         priv = dev_get_priv(bus);
549         flash = dev_get_uclass_priv(dev);
550
551         return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
552                                 (u8 *)din, flags);
553 }
554
555 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
556 {
557         struct stm32_qspi_platdata *plat = bus->platdata;
558         struct stm32_qspi_priv *priv = dev_get_priv(bus);
559         u32 qspi_clk = priv->clock_rate;
560         u32 prescaler = 255;
561         u32 csht;
562
563         if (speed > plat->max_hz)
564                 speed = plat->max_hz;
565
566         if (speed > 0) {
567                 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
568                 if (prescaler > 255)
569                         prescaler = 255;
570                 else if (prescaler < 0)
571                         prescaler = 0;
572         }
573
574         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
575         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
576
577         _stm32_qspi_wait_for_not_busy(priv);
578
579         clrsetbits_le32(&priv->regs->cr,
580                         STM32_QSPI_CR_PRESCALER_MASK <<
581                         STM32_QSPI_CR_PRESCALER_SHIFT,
582                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
583
584         clrsetbits_le32(&priv->regs->dcr,
585                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
586                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
587
588         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
589               (qspi_clk / (prescaler + 1)));
590
591         return 0;
592 }
593
594 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
595 {
596         struct stm32_qspi_priv *priv = dev_get_priv(bus);
597
598         _stm32_qspi_wait_for_not_busy(priv);
599
600         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
601                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
602         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
603                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
604         else
605                 return -ENODEV;
606
607         if (mode & SPI_CS_HIGH)
608                 return -ENODEV;
609
610         if (mode & SPI_RX_QUAD)
611                 priv->mode |= SPI_RX_QUAD;
612         else if (mode & SPI_RX_DUAL)
613                 priv->mode |= SPI_RX_DUAL;
614         else
615                 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
616
617         if (mode & SPI_TX_QUAD)
618                 priv->mode |= SPI_TX_QUAD;
619         else if (mode & SPI_TX_DUAL)
620                 priv->mode |= SPI_TX_DUAL;
621         else
622                 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
623
624         debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
625
626         if (mode & SPI_RX_QUAD)
627                 debug("quad, tx: ");
628         else if (mode & SPI_RX_DUAL)
629                 debug("dual, tx: ");
630         else
631                 debug("single, tx: ");
632
633         if (mode & SPI_TX_QUAD)
634                 debug("quad\n");
635         else if (mode & SPI_TX_DUAL)
636                 debug("dual\n");
637         else
638                 debug("single\n");
639
640         return 0;
641 }
642
643 static const struct dm_spi_ops stm32_qspi_ops = {
644         .claim_bus      = stm32_qspi_claim_bus,
645         .release_bus    = stm32_qspi_release_bus,
646         .xfer           = stm32_qspi_xfer,
647         .set_speed      = stm32_qspi_set_speed,
648         .set_mode       = stm32_qspi_set_mode,
649 };
650
651 static const struct udevice_id stm32_qspi_ids[] = {
652         { .compatible = "st,stm32-qspi" },
653         { .compatible = "st,stm32f469-qspi" },
654         { }
655 };
656
657 U_BOOT_DRIVER(stm32_qspi) = {
658         .name   = "stm32_qspi",
659         .id     = UCLASS_SPI,
660         .of_match = stm32_qspi_ids,
661         .ops    = &stm32_qspi_ops,
662         .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
663         .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
664         .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
665         .probe  = stm32_qspi_probe,
666         .remove = stm32_qspi_remove,
667 };