drivers/spi/stm32_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016
   4  *
   5  * Michael Kurz, <michi.kurz@gmail.com>
   6  *
   7  * STM32 QSPI driver
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <spi.h>
  16 #include <spi_flash.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/stm32.h>
  19 #include <linux/ioport.h>
  20
  21 struct stm32_qspi_regs {
  22         u32 cr;         /* 0x00 */
  23         u32 dcr;        /* 0x04 */
  24         u32 sr;         /* 0x08 */
  25         u32 fcr;        /* 0x0C */
  26         u32 dlr;        /* 0x10 */
  27         u32 ccr;        /* 0x14 */
  28         u32 ar;         /* 0x18 */
  29         u32 abr;        /* 0x1C */
  30         u32 dr;         /* 0x20 */
  31         u32 psmkr;      /* 0x24 */
  32         u32 psmar;      /* 0x28 */
  33         u32 pir;        /* 0x2C */
  34         u32 lptr;       /* 0x30 */
  35 };
  36
  37 /*
  38  * QUADSPI control register
  39  */
  40 #define STM32_QSPI_CR_EN                BIT(0)
  41 #define STM32_QSPI_CR_ABORT             BIT(1)
  42 #define STM32_QSPI_CR_DMAEN             BIT(2)
  43 #define STM32_QSPI_CR_TCEN              BIT(3)
  44 #define STM32_QSPI_CR_SSHIFT            BIT(4)
  45 #define STM32_QSPI_CR_DFM               BIT(6)
  46 #define STM32_QSPI_CR_FSEL              BIT(7)
  47 #define STM32_QSPI_CR_FTHRES_MASK       GENMASK(4, 0)
  48 #define STM32_QSPI_CR_FTHRES_SHIFT      (8)
  49 #define STM32_QSPI_CR_TEIE              BIT(16)
  50 #define STM32_QSPI_CR_TCIE              BIT(17)
  51 #define STM32_QSPI_CR_FTIE              BIT(18)
  52 #define STM32_QSPI_CR_SMIE              BIT(19)
  53 #define STM32_QSPI_CR_TOIE              BIT(20)
  54 #define STM32_QSPI_CR_APMS              BIT(22)
  55 #define STM32_QSPI_CR_PMM               BIT(23)
  56 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
  57 #define STM32_QSPI_CR_PRESCALER_SHIFT   (24)
  58
  59 /*
  60  * QUADSPI device configuration register
  61  */
  62 #define STM32_QSPI_DCR_CKMODE           BIT(0)
  63 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
  64 #define STM32_QSPI_DCR_CSHT_SHIFT       (8)
  65 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
  66 #define STM32_QSPI_DCR_FSIZE_SHIFT      (16)
  67
  68 /*
  69  * QUADSPI status register
  70  */
  71 #define STM32_QSPI_SR_TEF               BIT(0)
  72 #define STM32_QSPI_SR_TCF               BIT(1)
  73 #define STM32_QSPI_SR_FTF               BIT(2)
  74 #define STM32_QSPI_SR_SMF               BIT(3)
  75 #define STM32_QSPI_SR_TOF               BIT(4)
  76 #define STM32_QSPI_SR_BUSY              BIT(5)
  77 #define STM32_QSPI_SR_FLEVEL_MASK       GENMASK(5, 0)
  78 #define STM32_QSPI_SR_FLEVEL_SHIFT      (8)
  79
  80 /*
  81  * QUADSPI flag clear register
  82  */
  83 #define STM32_QSPI_FCR_CTEF             BIT(0)
  84 #define STM32_QSPI_FCR_CTCF             BIT(1)
  85 #define STM32_QSPI_FCR_CSMF             BIT(3)
  86 #define STM32_QSPI_FCR_CTOF             BIT(4)
  87
  88 /*
  89  * QUADSPI communication configuration register
  90  */
  91 #define STM32_QSPI_CCR_DDRM             BIT(31)
  92 #define STM32_QSPI_CCR_DHHC             BIT(30)
  93 #define STM32_QSPI_CCR_SIOO             BIT(28)
  94 #define STM32_QSPI_CCR_FMODE_SHIFT      (26)
  95 #define STM32_QSPI_CCR_DMODE_SHIFT      (24)
  96 #define STM32_QSPI_CCR_DCYC_SHIFT       (18)
  97 #define STM32_QSPI_CCR_DCYC_MASK        GENMASK(4, 0)
  98 #define STM32_QSPI_CCR_ABSIZE_SHIFT     (16)
  99 #define STM32_QSPI_CCR_ABMODE_SHIFT     (14)
 100 #define STM32_QSPI_CCR_ADSIZE_SHIFT     (12)
 101 #define STM32_QSPI_CCR_ADMODE_SHIFT     (10)
 102 #define STM32_QSPI_CCR_IMODE_SHIFT      (8)
 103 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
 104
 105 enum STM32_QSPI_CCR_IMODE {
 106         STM32_QSPI_CCR_IMODE_NONE = 0,
 107         STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
 108         STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
 109         STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
 110 };
 111
 112 enum STM32_QSPI_CCR_ADMODE {
 113         STM32_QSPI_CCR_ADMODE_NONE = 0,
 114         STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
 115         STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
 116         STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
 117 };
 118
 119 enum STM32_QSPI_CCR_ADSIZE {
 120         STM32_QSPI_CCR_ADSIZE_8BIT = 0,
 121         STM32_QSPI_CCR_ADSIZE_16BIT = 1,
 122         STM32_QSPI_CCR_ADSIZE_24BIT = 2,
 123         STM32_QSPI_CCR_ADSIZE_32BIT = 3,
 124 };
 125
 126 enum STM32_QSPI_CCR_ABMODE {
 127         STM32_QSPI_CCR_ABMODE_NONE = 0,
 128         STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
 129         STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
 130         STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
 131 };
 132
 133 enum STM32_QSPI_CCR_ABSIZE {
 134         STM32_QSPI_CCR_ABSIZE_8BIT = 0,
 135         STM32_QSPI_CCR_ABSIZE_16BIT = 1,
 136         STM32_QSPI_CCR_ABSIZE_24BIT = 2,
 137         STM32_QSPI_CCR_ABSIZE_32BIT = 3,
 138 };
 139
 140 enum STM32_QSPI_CCR_DMODE {
 141         STM32_QSPI_CCR_DMODE_NONE = 0,
 142         STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
 143         STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
 144         STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
 145 };
 146
 147 enum STM32_QSPI_CCR_FMODE {
 148         STM32_QSPI_CCR_IND_WRITE = 0,
 149         STM32_QSPI_CCR_IND_READ = 1,
 150         STM32_QSPI_CCR_AUTO_POLL = 2,
 151         STM32_QSPI_CCR_MEM_MAP = 3,
 152 };
 153
 154 /* default SCK frequency, unit: HZ */
 155 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
 156
 157 #define STM32_MAX_NORCHIP 2
 158
 159 struct stm32_qspi_platdata {
 160         u32 base;
 161         u32 memory_map;
 162         u32 max_hz;
 163 };
 164
 165 struct stm32_qspi_priv {
 166         struct stm32_qspi_regs *regs;
 167         ulong clock_rate;
 168         u32 max_hz;
 169         u32 mode;
 170
 171         u32 command;
 172         u32 address;
 173         u32 dummycycles;
 174 #define CMD_HAS_ADR     BIT(24)
 175 #define CMD_HAS_DUMMY   BIT(25)
 176 #define CMD_HAS_DATA    BIT(26)
 177 };
 178
 179 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
 180 {
 181         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 182 }
 183
 184 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
 185 {
 186         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 187 }
 188
 189 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
 190 {
 191         while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
 192                 ;
 193 }
 194
 195 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
 196 {
 197         while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
 198                 ;
 199 }
 200
 201 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
 202 {
 203         while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
 204                 ;
 205 }
 206
 207 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
 208 {
 209         u32 fsize = fls(size) - 1;
 210
 211         clrsetbits_le32(&priv->regs->dcr,
 212                         STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
 213                         fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
 214 }
 215
 216 static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
 217 {
 218         clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
 219                         cs ? STM32_QSPI_CR_FSEL : 0);
 220 }
 221
 222 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 223 {
 224         unsigned int ccr_reg = 0;
 225         u8 imode, admode, dmode;
 226         u32 mode = priv->mode;
 227         u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
 228
 229         imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
 230         admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
 231
 232         if (mode & SPI_RX_QUAD) {
 233                 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
 234                 if (mode & SPI_TX_QUAD) {
 235                         imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
 236                         admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
 237                 }
 238         } else if (mode & SPI_RX_DUAL) {
 239                 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
 240                 if (mode & SPI_TX_DUAL) {
 241                         imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
 242                         admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
 243                 }
 244         } else {
 245                 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
 246         }
 247
 248         if (priv->command & CMD_HAS_DATA)
 249                 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
 250
 251         if (priv->command & CMD_HAS_DUMMY)
 252                 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
 253                                 << STM32_QSPI_CCR_DCYC_SHIFT);
 254
 255         if (priv->command & CMD_HAS_ADR) {
 256                 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
 257                                 << STM32_QSPI_CCR_ADSIZE_SHIFT);
 258                 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
 259         }
 260         ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
 261         ccr_reg |= cmd;
 262         return ccr_reg;
 263 }
 264
 265 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
 266                                     struct spi_flash *flash)
 267 {
 268         unsigned int ccr_reg;
 269
 270         priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
 271                         | CMD_HAS_DUMMY;
 272         priv->dummycycles = flash->dummy_byte * 8;
 273
 274         ccr_reg = _stm32_qspi_gen_ccr(priv);
 275         ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
 276
 277         _stm32_qspi_wait_for_not_busy(priv);
 278
 279         writel(ccr_reg, &priv->regs->ccr);
 280
 281         priv->dummycycles = 0;
 282 }
 283
 284 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
 285 {
 286         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
 287 }
 288
 289 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
 290                                         u32 length)
 291 {
 292         writel(length - 1, &priv->regs->dlr);
 293 }
 294
 295 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
 296 {
 297         writel(cr_reg, &priv->regs->ccr);
 298
 299         if (priv->command & CMD_HAS_ADR)
 300                 writel(priv->address, &priv->regs->ar);
 301 }
 302
 303 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 304                             struct spi_flash *flash, unsigned int bitlen,
 305                             const u8 *dout, u8 *din, unsigned long flags)
 306 {
 307         unsigned int words = bitlen / 8;
 308         u32 ccr_reg;
 309         int i;
 310
 311         if (flags & SPI_XFER_MMAP) {
 312                 _stm32_qspi_enable_mmap(priv, flash);
 313                 return 0;
 314         } else if (flags & SPI_XFER_MMAP_END) {
 315                 _stm32_qspi_disable_mmap(priv);
 316                 return 0;
 317         }
 318
 319         if (bitlen == 0)
 320                 return -1;
 321
 322         if (bitlen % 8) {
 323                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 324                 return -1;
 325         }
 326
 327         if (dout && din) {
 328                 debug("spi_xfer: QSPI cannot have data in and data out set\n");
 329                 return -1;
 330         }
 331
 332         if (!dout && (flags & SPI_XFER_BEGIN)) {
 333                 debug("spi_xfer: QSPI transfer must begin with command\n");
 334                 return -1;
 335         }
 336
 337         if (dout) {
 338                 if (flags & SPI_XFER_BEGIN) {
 339                         /* data is command */
 340                         priv->command = dout[0] | CMD_HAS_DATA;
 341                         if (words >= 4) {
 342                                 /* address is here too */
 343                                 priv->address = (dout[1] << 16) |
 344                                                 (dout[2] << 8) | dout[3];
 345                                 priv->command |= CMD_HAS_ADR;
 346                         }
 347
 348                         if (words > 4) {
 349                                 /* rest is dummy bytes */
 350                                 priv->dummycycles = (words - 4) * 8;
 351                                 priv->command |= CMD_HAS_DUMMY;
 352                         }
 353
 354                         if (flags & SPI_XFER_END) {
 355                                 /* command without data */
 356                                 priv->command &= ~(CMD_HAS_DATA);
 357                         }
 358                 }
 359
 360                 if (flags & SPI_XFER_END) {
 361                         ccr_reg = _stm32_qspi_gen_ccr(priv);
 362                         ccr_reg |= STM32_QSPI_CCR_IND_WRITE
 363                                         << STM32_QSPI_CCR_FMODE_SHIFT;
 364
 365                         _stm32_qspi_wait_for_not_busy(priv);
 366
 367                         if (priv->command & CMD_HAS_DATA)
 368                                 _stm32_qspi_set_xfer_length(priv, words);
 369
 370                         _stm32_qspi_start_xfer(priv, ccr_reg);
 371
 372                         debug("%s: write: ccr:0x%08x adr:0x%08x\n",
 373                               __func__, priv->regs->ccr, priv->regs->ar);
 374
 375                         if (priv->command & CMD_HAS_DATA) {
 376                                 _stm32_qspi_wait_for_ftf(priv);
 377
 378                                 debug("%s: words:%d data:", __func__, words);
 379
 380                                 i = 0;
 381                                 while (words > i) {
 382                                         writeb(dout[i], &priv->regs->dr);
 383                                         debug("%02x ", dout[i]);
 384                                         i++;
 385                                 }
 386                                 debug("\n");
 387
 388                                 _stm32_qspi_wait_for_complete(priv);
 389                         } else {
 390                                 _stm32_qspi_wait_for_not_busy(priv);
 391                         }
 392                 }
 393         } else if (din) {
 394                 ccr_reg = _stm32_qspi_gen_ccr(priv);
 395                 ccr_reg |= STM32_QSPI_CCR_IND_READ
 396                                 << STM32_QSPI_CCR_FMODE_SHIFT;
 397
 398                 _stm32_qspi_wait_for_not_busy(priv);
 399
 400                 _stm32_qspi_set_xfer_length(priv, words);
 401
 402                 _stm32_qspi_start_xfer(priv, ccr_reg);
 403
 404                 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
 405                       priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
 406
 407                 debug("%s: data:", __func__);
 408
 409                 i = 0;
 410                 while (words > i) {
 411                         din[i] = readb(&priv->regs->dr);
 412                         debug("%02x ", din[i]);
 413                         i++;
 414                 }
 415                 debug("\n");
 416         }
 417
 418         return 0;
 419 }
 420
 421 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
 422 {
 423         struct resource res_regs, res_mem;
 424         struct stm32_qspi_platdata *plat = bus->platdata;
 425         int ret;
 426
 427         ret = dev_read_resource_byname(bus, "qspi", &res_regs);
 428         if (ret) {
 429                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
 430                 return -ENOMEM;
 431         }
 432         ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
 433         if (ret) {
 434                 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
 435                 return -ENOMEM;
 436         }
 437
 438         plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
 439                                             STM32_QSPI_DEFAULT_SCK_FREQ);
 440
 441         plat->base = res_regs.start;
 442         plat->memory_map = res_mem.start;
 443
 444         debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
 445               __func__,
 446               plat->base,
 447               plat->memory_map,
 448               plat->max_hz
 449               );
 450
 451         return 0;
 452 }
 453
 454 static int stm32_qspi_probe(struct udevice *bus)
 455 {
 456         struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
 457         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 458         struct dm_spi_bus *dm_spi_bus;
 459         struct clk clk;
 460         int ret;
 461
 462         dm_spi_bus = bus->uclass_priv;
 463
 464         dm_spi_bus->max_hz = plat->max_hz;
 465
 466         priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
 467
 468         priv->max_hz = plat->max_hz;
 469
 470         ret = clk_get_by_index(bus, 0, &clk);
 471         if (ret < 0)
 472                 return ret;
 473
 474         ret = clk_enable(&clk);
 475
 476         if (ret) {
 477                 dev_err(bus, "failed to enable clock\n");
 478                 return ret;
 479         }
 480
 481         priv->clock_rate = clk_get_rate(&clk);
 482         if (priv->clock_rate < 0) {
 483                 clk_disable(&clk);
 484                 return priv->clock_rate;
 485         }
 486
 487
 488         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 489
 490         return 0;
 491 }
 492
 493 static int stm32_qspi_remove(struct udevice *bus)
 494 {
 495         return 0;
 496 }
 497
 498 static int stm32_qspi_claim_bus(struct udevice *dev)
 499 {
 500         struct stm32_qspi_priv *priv;
 501         struct udevice *bus;
 502         struct spi_flash *flash;
 503         struct dm_spi_slave_platdata *slave_plat;
 504
 505         bus = dev->parent;
 506         priv = dev_get_priv(bus);
 507         flash = dev_get_uclass_priv(dev);
 508         slave_plat = dev_get_parent_platdata(dev);
 509
 510         if (slave_plat->cs >= STM32_MAX_NORCHIP)
 511                 return -ENODEV;
 512
 513         _stm32_qspi_set_cs(priv, slave_plat->cs);
 514
 515         _stm32_qspi_set_flash_size(priv, flash->size);
 516
 517         _stm32_qspi_enable(priv);
 518
 519         return 0;
 520 }
 521
 522 static int stm32_qspi_release_bus(struct udevice *dev)
 523 {
 524         struct stm32_qspi_priv *priv;
 525         struct udevice *bus;
 526
 527         bus = dev->parent;
 528         priv = dev_get_priv(bus);
 529
 530         _stm32_qspi_disable(priv);
 531
 532         return 0;
 533 }
 534
 535 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 536                            const void *dout, void *din, unsigned long flags)
 537 {
 538         struct stm32_qspi_priv *priv;
 539         struct udevice *bus;
 540         struct spi_flash *flash;
 541
 542         bus = dev->parent;
 543         priv = dev_get_priv(bus);
 544         flash = dev_get_uclass_priv(dev);
 545
 546         return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
 547                                 (u8 *)din, flags);
 548 }
 549
 550 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 551 {
 552         struct stm32_qspi_platdata *plat = bus->platdata;
 553         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 554         u32 qspi_clk = priv->clock_rate;
 555         u32 prescaler = 255;
 556         u32 csht;
 557
 558         if (speed > plat->max_hz)
 559                 speed = plat->max_hz;
 560
 561         if (speed > 0) {
 562                 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 563                 if (prescaler > 255)
 564                         prescaler = 255;
 565                 else if (prescaler < 0)
 566                         prescaler = 0;
 567         }
 568
 569         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 570         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 571
 572         _stm32_qspi_wait_for_not_busy(priv);
 573
 574         clrsetbits_le32(&priv->regs->cr,
 575                         STM32_QSPI_CR_PRESCALER_MASK <<
 576                         STM32_QSPI_CR_PRESCALER_SHIFT,
 577                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 578
 579         clrsetbits_le32(&priv->regs->dcr,
 580                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 581                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
 582
 583         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
 584               (qspi_clk / (prescaler + 1)));
 585
 586         return 0;
 587 }
 588
 589 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
 590 {
 591         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 592
 593         _stm32_qspi_wait_for_not_busy(priv);
 594
 595         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
 596                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 597         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
 598                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 599         else
 600                 return -ENODEV;
 601
 602         if (mode & SPI_CS_HIGH)
 603                 return -ENODEV;
 604
 605         if (mode & SPI_RX_QUAD)
 606                 priv->mode |= SPI_RX_QUAD;
 607         else if (mode & SPI_RX_DUAL)
 608                 priv->mode |= SPI_RX_DUAL;
 609         else
 610                 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
 611
 612         if (mode & SPI_TX_QUAD)
 613                 priv->mode |= SPI_TX_QUAD;
 614         else if (mode & SPI_TX_DUAL)
 615                 priv->mode |= SPI_TX_DUAL;
 616         else
 617                 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
 618
 619         debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
 620
 621         if (mode & SPI_RX_QUAD)
 622                 debug("quad, tx: ");
 623         else if (mode & SPI_RX_DUAL)
 624                 debug("dual, tx: ");
 625         else
 626                 debug("single, tx: ");
 627
 628         if (mode & SPI_TX_QUAD)
 629                 debug("quad\n");
 630         else if (mode & SPI_TX_DUAL)
 631                 debug("dual\n");
 632         else
 633                 debug("single\n");
 634
 635         return 0;
 636 }
 637
 638 static const struct dm_spi_ops stm32_qspi_ops = {
 639         .claim_bus      = stm32_qspi_claim_bus,
 640         .release_bus    = stm32_qspi_release_bus,
 641         .xfer           = stm32_qspi_xfer,
 642         .set_speed      = stm32_qspi_set_speed,
 643         .set_mode       = stm32_qspi_set_mode,
 644 };
 645
 646 static const struct udevice_id stm32_qspi_ids[] = {
 647         { .compatible = "st,stm32-qspi" },
 648         { .compatible = "st,stm32f469-qspi" },
 649         { }
 650 };
 651
 652 U_BOOT_DRIVER(stm32_qspi) = {
 653         .name   = "stm32_qspi",
 654         .id     = UCLASS_SPI,
 655         .of_match = stm32_qspi_ids,
 656         .ops    = &stm32_qspi_ops,
 657         .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
 658         .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
 659         .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
 660         .probe  = stm32_qspi_probe,
 661         .remove = stm32_qspi_remove,
 662 };