Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
[platform/kernel/u-boot.git] / drivers / spi / stm32_qspi.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2016
4  *
5  * Michael Kurz, <michi.kurz@gmail.com>
6  *
7  * STM32 QSPI driver
8  */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <reset.h>
13 #include <spi-mem.h>
14 #include <linux/iopoll.h>
15 #include <linux/ioport.h>
16 #include <linux/sizes.h>
17
18 struct stm32_qspi_regs {
19         u32 cr;         /* 0x00 */
20         u32 dcr;        /* 0x04 */
21         u32 sr;         /* 0x08 */
22         u32 fcr;        /* 0x0C */
23         u32 dlr;        /* 0x10 */
24         u32 ccr;        /* 0x14 */
25         u32 ar;         /* 0x18 */
26         u32 abr;        /* 0x1C */
27         u32 dr;         /* 0x20 */
28         u32 psmkr;      /* 0x24 */
29         u32 psmar;      /* 0x28 */
30         u32 pir;        /* 0x2C */
31         u32 lptr;       /* 0x30 */
32 };
33
34 /*
35  * QUADSPI control register
36  */
37 #define STM32_QSPI_CR_EN                BIT(0)
38 #define STM32_QSPI_CR_ABORT             BIT(1)
39 #define STM32_QSPI_CR_DMAEN             BIT(2)
40 #define STM32_QSPI_CR_TCEN              BIT(3)
41 #define STM32_QSPI_CR_SSHIFT            BIT(4)
42 #define STM32_QSPI_CR_DFM               BIT(6)
43 #define STM32_QSPI_CR_FSEL              BIT(7)
44 #define STM32_QSPI_CR_FTHRES_SHIFT      8
45 #define STM32_QSPI_CR_TEIE              BIT(16)
46 #define STM32_QSPI_CR_TCIE              BIT(17)
47 #define STM32_QSPI_CR_FTIE              BIT(18)
48 #define STM32_QSPI_CR_SMIE              BIT(19)
49 #define STM32_QSPI_CR_TOIE              BIT(20)
50 #define STM32_QSPI_CR_APMS              BIT(22)
51 #define STM32_QSPI_CR_PMM               BIT(23)
52 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
53 #define STM32_QSPI_CR_PRESCALER_SHIFT   24
54
55 /*
56  * QUADSPI device configuration register
57  */
58 #define STM32_QSPI_DCR_CKMODE           BIT(0)
59 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
60 #define STM32_QSPI_DCR_CSHT_SHIFT       8
61 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
62 #define STM32_QSPI_DCR_FSIZE_SHIFT      16
63
64 /*
65  * QUADSPI status register
66  */
67 #define STM32_QSPI_SR_TEF               BIT(0)
68 #define STM32_QSPI_SR_TCF               BIT(1)
69 #define STM32_QSPI_SR_FTF               BIT(2)
70 #define STM32_QSPI_SR_SMF               BIT(3)
71 #define STM32_QSPI_SR_TOF               BIT(4)
72 #define STM32_QSPI_SR_BUSY              BIT(5)
73
74 /*
75  * QUADSPI flag clear register
76  */
77 #define STM32_QSPI_FCR_CTEF             BIT(0)
78 #define STM32_QSPI_FCR_CTCF             BIT(1)
79 #define STM32_QSPI_FCR_CSMF             BIT(3)
80 #define STM32_QSPI_FCR_CTOF             BIT(4)
81
82 /*
83  * QUADSPI communication configuration register
84  */
85 #define STM32_QSPI_CCR_DDRM             BIT(31)
86 #define STM32_QSPI_CCR_DHHC             BIT(30)
87 #define STM32_QSPI_CCR_SIOO             BIT(28)
88 #define STM32_QSPI_CCR_FMODE_SHIFT      26
89 #define STM32_QSPI_CCR_DMODE_SHIFT      24
90 #define STM32_QSPI_CCR_DCYC_SHIFT       18
91 #define STM32_QSPI_CCR_ABSIZE_SHIFT     16
92 #define STM32_QSPI_CCR_ABMODE_SHIFT     14
93 #define STM32_QSPI_CCR_ADSIZE_SHIFT     12
94 #define STM32_QSPI_CCR_ADMODE_SHIFT     10
95 #define STM32_QSPI_CCR_IMODE_SHIFT      8
96
97 #define STM32_QSPI_CCR_IND_WRITE        0
98 #define STM32_QSPI_CCR_IND_READ         1
99 #define STM32_QSPI_CCR_MEM_MAP          3
100
101 #define STM32_QSPI_MAX_MMAP_SZ          SZ_256M
102 #define STM32_QSPI_MAX_CHIP             2
103
104 #define STM32_QSPI_FIFO_TIMEOUT_US      30000
105 #define STM32_QSPI_CMD_TIMEOUT_US       1000000
106 #define STM32_BUSY_TIMEOUT_US           100000
107 #define STM32_ABT_TIMEOUT_US            100000
108
109 struct stm32_qspi_flash {
110         u32 cr;
111         u32 dcr;
112         bool initialized;
113 };
114
115 struct stm32_qspi_priv {
116         struct stm32_qspi_regs *regs;
117         struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
118         void __iomem *mm_base;
119         resource_size_t mm_size;
120         ulong clock_rate;
121         int cs_used;
122 };
123
124 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
125 {
126         u32 sr;
127         int ret;
128
129         ret = readl_poll_timeout(&priv->regs->sr, sr,
130                                  !(sr & STM32_QSPI_SR_BUSY),
131                                  STM32_BUSY_TIMEOUT_US);
132         if (ret)
133                 pr_err("busy timeout (stat:%#x)\n", sr);
134
135         return ret;
136 }
137
138 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
139                                 const struct spi_mem_op *op)
140 {
141         u32 sr;
142         int ret;
143
144         if (!op->data.nbytes)
145                 return _stm32_qspi_wait_for_not_busy(priv);
146
147         ret = readl_poll_timeout(&priv->regs->sr, sr,
148                                  sr & STM32_QSPI_SR_TCF,
149                                  STM32_QSPI_CMD_TIMEOUT_US);
150         if (ret) {
151                 pr_err("cmd timeout (stat:%#x)\n", sr);
152         } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
153                 pr_err("transfer error (stat:%#x)\n", sr);
154                 ret = -EIO;
155         }
156
157         /* clear flags */
158         writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
159
160         return ret;
161 }
162
163 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
164 {
165         *val = readb(addr);
166 }
167
168 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
169 {
170         writeb(*val, addr);
171 }
172
173 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
174                             const struct spi_mem_op *op)
175 {
176         void (*fifo)(u8 *val, void __iomem *addr);
177         u32 len = op->data.nbytes, sr;
178         u8 *buf;
179         int ret;
180
181         if (op->data.dir == SPI_MEM_DATA_IN) {
182                 fifo = _stm32_qspi_read_fifo;
183                 buf = op->data.buf.in;
184
185         } else {
186                 fifo = _stm32_qspi_write_fifo;
187                 buf = (u8 *)op->data.buf.out;
188         }
189
190         while (len--) {
191                 ret = readl_poll_timeout(&priv->regs->sr, sr,
192                                          sr & STM32_QSPI_SR_FTF,
193                                          STM32_QSPI_FIFO_TIMEOUT_US);
194                 if (ret) {
195                         pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
196                         return ret;
197                 }
198
199                 fifo(buf++, &priv->regs->dr);
200         }
201
202         return 0;
203 }
204
205 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
206                          const struct spi_mem_op *op)
207 {
208         memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
209                       op->data.nbytes);
210
211         return 0;
212 }
213
214 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
215                           const struct spi_mem_op *op,
216                           u8 mode)
217 {
218         if (!op->data.nbytes)
219                 return 0;
220
221         if (mode == STM32_QSPI_CCR_MEM_MAP)
222                 return stm32_qspi_mm(priv, op);
223
224         return _stm32_qspi_poll(priv, op);
225 }
226
227 static int _stm32_qspi_get_mode(u8 buswidth)
228 {
229         if (buswidth == 4)
230                 return 3;
231
232         return buswidth;
233 }
234
235 static int stm32_qspi_exec_op(struct spi_slave *slave,
236                               const struct spi_mem_op *op)
237 {
238         struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
239         u32 cr, ccr, addr_max;
240         u8 mode = STM32_QSPI_CCR_IND_WRITE;
241         int timeout, ret;
242
243         debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
244               __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
245               op->dummy.buswidth, op->data.buswidth,
246               op->addr.val, op->data.nbytes);
247
248         ret = _stm32_qspi_wait_for_not_busy(priv);
249         if (ret)
250                 return ret;
251
252         addr_max = op->addr.val + op->data.nbytes + 1;
253
254         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
255                 if (addr_max < priv->mm_size && op->addr.buswidth)
256                         mode = STM32_QSPI_CCR_MEM_MAP;
257                 else
258                         mode = STM32_QSPI_CCR_IND_READ;
259         }
260
261         if (op->data.nbytes)
262                 writel(op->data.nbytes - 1, &priv->regs->dlr);
263
264         ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
265         ccr |= op->cmd.opcode;
266         ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
267                 << STM32_QSPI_CCR_IMODE_SHIFT);
268
269         if (op->addr.nbytes) {
270                 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
271                 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
272                         << STM32_QSPI_CCR_ADMODE_SHIFT);
273         }
274
275         if (op->dummy.buswidth && op->dummy.nbytes)
276                 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
277                         << STM32_QSPI_CCR_DCYC_SHIFT);
278
279         if (op->data.nbytes)
280                 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
281                         << STM32_QSPI_CCR_DMODE_SHIFT);
282
283         writel(ccr, &priv->regs->ccr);
284
285         if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
286                 writel(op->addr.val, &priv->regs->ar);
287
288         ret = _stm32_qspi_tx(priv, op, mode);
289         /*
290          * Abort in:
291          * -error case
292          * -read memory map: prefetching must be stopped if we read the last
293          *  byte of device (device size - fifo size). like device size is not
294          *  knows, the prefetching is always stop.
295          */
296         if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
297                 goto abort;
298
299         /* Wait end of tx in indirect mode */
300         ret = _stm32_qspi_wait_cmd(priv, op);
301         if (ret)
302                 goto abort;
303
304         return 0;
305
306 abort:
307         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
308
309         /* Wait clear of abort bit by hw */
310         timeout = readl_poll_timeout(&priv->regs->cr, cr,
311                                      !(cr & STM32_QSPI_CR_ABORT),
312                                      STM32_ABT_TIMEOUT_US);
313
314         writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
315
316         if (ret || timeout)
317                 pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
318
319         return ret;
320 }
321
322 static int stm32_qspi_probe(struct udevice *bus)
323 {
324         struct stm32_qspi_priv *priv = dev_get_priv(bus);
325         struct resource res;
326         struct clk clk;
327         struct reset_ctl reset_ctl;
328         int ret;
329
330         ret = dev_read_resource_byname(bus, "qspi", &res);
331         if (ret) {
332                 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
333                 return ret;
334         }
335
336         priv->regs = (struct stm32_qspi_regs *)res.start;
337
338         ret = dev_read_resource_byname(bus, "qspi_mm", &res);
339         if (ret) {
340                 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
341                 return ret;
342         }
343
344         priv->mm_base = (void __iomem *)res.start;
345
346         priv->mm_size = resource_size(&res);
347         if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
348                 return -EINVAL;
349
350         debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
351               __func__, priv->regs, priv->mm_base, priv->mm_size);
352
353         ret = clk_get_by_index(bus, 0, &clk);
354         if (ret < 0)
355                 return ret;
356
357         ret = clk_enable(&clk);
358         if (ret) {
359                 dev_err(bus, "failed to enable clock\n");
360                 return ret;
361         }
362
363         priv->clock_rate = clk_get_rate(&clk);
364         if (!priv->clock_rate) {
365                 clk_disable(&clk);
366                 return -EINVAL;
367         }
368
369         ret = reset_get_by_index(bus, 0, &reset_ctl);
370         if (ret) {
371                 if (ret != -ENOENT) {
372                         dev_err(bus, "failed to get reset\n");
373                         clk_disable(&clk);
374                         return ret;
375                 }
376         } else {
377                 /* Reset QSPI controller */
378                 reset_assert(&reset_ctl);
379                 udelay(2);
380                 reset_deassert(&reset_ctl);
381         }
382
383         priv->cs_used = -1;
384
385         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
386
387         /* Set dcr fsize to max address */
388         setbits_le32(&priv->regs->dcr,
389                      STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
390
391         return 0;
392 }
393
394 static int stm32_qspi_claim_bus(struct udevice *dev)
395 {
396         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
397         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
398         int slave_cs = slave_plat->cs;
399
400         if (slave_cs >= STM32_QSPI_MAX_CHIP)
401                 return -ENODEV;
402
403         if (priv->cs_used != slave_cs) {
404                 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
405
406                 priv->cs_used = slave_cs;
407
408                 if (flash->initialized) {
409                         /* Set the configuration: speed + cs */
410                         writel(flash->cr, &priv->regs->cr);
411                         writel(flash->dcr, &priv->regs->dcr);
412                 } else {
413                         /* Set chip select */
414                         clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
415                                         priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
416
417                         /* Save the configuration: speed + cs */
418                         flash->cr = readl(&priv->regs->cr);
419                         flash->dcr = readl(&priv->regs->dcr);
420
421                         flash->initialized = true;
422                 }
423         }
424
425         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
426
427         return 0;
428 }
429
430 static int stm32_qspi_release_bus(struct udevice *dev)
431 {
432         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
433
434         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
435
436         return 0;
437 }
438
439 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
440 {
441         struct stm32_qspi_priv *priv = dev_get_priv(bus);
442         u32 qspi_clk = priv->clock_rate;
443         u32 prescaler = 255;
444         u32 csht;
445         int ret;
446
447         if (speed > 0) {
448                 prescaler = 0;
449                 if (qspi_clk) {
450                         prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
451                         if (prescaler > 255)
452                                 prescaler = 255;
453                 }
454         }
455
456         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
457         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
458
459         ret = _stm32_qspi_wait_for_not_busy(priv);
460         if (ret)
461                 return ret;
462
463         clrsetbits_le32(&priv->regs->cr,
464                         STM32_QSPI_CR_PRESCALER_MASK <<
465                         STM32_QSPI_CR_PRESCALER_SHIFT,
466                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
467
468         clrsetbits_le32(&priv->regs->dcr,
469                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
470                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
471
472         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
473               (qspi_clk / (prescaler + 1)));
474
475         return 0;
476 }
477
478 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
479 {
480         struct stm32_qspi_priv *priv = dev_get_priv(bus);
481         int ret;
482
483         ret = _stm32_qspi_wait_for_not_busy(priv);
484         if (ret)
485                 return ret;
486
487         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
488                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
489         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
490                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
491         else
492                 return -ENODEV;
493
494         if (mode & SPI_CS_HIGH)
495                 return -ENODEV;
496
497         debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
498
499         if (mode & SPI_RX_QUAD)
500                 debug("quad, tx: ");
501         else if (mode & SPI_RX_DUAL)
502                 debug("dual, tx: ");
503         else
504                 debug("single, tx: ");
505
506         if (mode & SPI_TX_QUAD)
507                 debug("quad\n");
508         else if (mode & SPI_TX_DUAL)
509                 debug("dual\n");
510         else
511                 debug("single\n");
512
513         return 0;
514 }
515
516 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
517         .exec_op = stm32_qspi_exec_op,
518 };
519
520 static const struct dm_spi_ops stm32_qspi_ops = {
521         .claim_bus      = stm32_qspi_claim_bus,
522         .release_bus    = stm32_qspi_release_bus,
523         .set_speed      = stm32_qspi_set_speed,
524         .set_mode       = stm32_qspi_set_mode,
525         .mem_ops        = &stm32_qspi_mem_ops,
526 };
527
528 static const struct udevice_id stm32_qspi_ids[] = {
529         { .compatible = "st,stm32-qspi" },
530         { .compatible = "st,stm32f469-qspi" },
531         { }
532 };
533
534 U_BOOT_DRIVER(stm32_qspi) = {
535         .name = "stm32_qspi",
536         .id = UCLASS_SPI,
537         .of_match = stm32_qspi_ids,
538         .ops = &stm32_qspi_ops,
539         .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
540         .probe = stm32_qspi_probe,
541 };