1 // SPDX-License-Identifier: GPL-2.0+
5 * Michael Kurz, <michi.kurz@gmail.com>
16 #include <spi_flash.h>
18 #include <asm/arch/stm32.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 struct stm32_qspi_regs {
39 * QUADSPI control register
41 #define STM32_QSPI_CR_EN BIT(0)
42 #define STM32_QSPI_CR_ABORT BIT(1)
43 #define STM32_QSPI_CR_DMAEN BIT(2)
44 #define STM32_QSPI_CR_TCEN BIT(3)
45 #define STM32_QSPI_CR_SSHIFT BIT(4)
46 #define STM32_QSPI_CR_DFM BIT(6)
47 #define STM32_QSPI_CR_FSEL BIT(7)
48 #define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
49 #define STM32_QSPI_CR_FTHRES_SHIFT (8)
50 #define STM32_QSPI_CR_TEIE BIT(16)
51 #define STM32_QSPI_CR_TCIE BIT(17)
52 #define STM32_QSPI_CR_FTIE BIT(18)
53 #define STM32_QSPI_CR_SMIE BIT(19)
54 #define STM32_QSPI_CR_TOIE BIT(20)
55 #define STM32_QSPI_CR_APMS BIT(22)
56 #define STM32_QSPI_CR_PMM BIT(23)
57 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
58 #define STM32_QSPI_CR_PRESCALER_SHIFT (24)
61 * QUADSPI device configuration register
63 #define STM32_QSPI_DCR_CKMODE BIT(0)
64 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
65 #define STM32_QSPI_DCR_CSHT_SHIFT (8)
66 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
67 #define STM32_QSPI_DCR_FSIZE_SHIFT (16)
70 * QUADSPI status register
72 #define STM32_QSPI_SR_TEF BIT(0)
73 #define STM32_QSPI_SR_TCF BIT(1)
74 #define STM32_QSPI_SR_FTF BIT(2)
75 #define STM32_QSPI_SR_SMF BIT(3)
76 #define STM32_QSPI_SR_TOF BIT(4)
77 #define STM32_QSPI_SR_BUSY BIT(5)
78 #define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
79 #define STM32_QSPI_SR_FLEVEL_SHIFT (8)
82 * QUADSPI flag clear register
84 #define STM32_QSPI_FCR_CTEF BIT(0)
85 #define STM32_QSPI_FCR_CTCF BIT(1)
86 #define STM32_QSPI_FCR_CSMF BIT(3)
87 #define STM32_QSPI_FCR_CTOF BIT(4)
90 * QUADSPI communication configuration register
92 #define STM32_QSPI_CCR_DDRM BIT(31)
93 #define STM32_QSPI_CCR_DHHC BIT(30)
94 #define STM32_QSPI_CCR_SIOO BIT(28)
95 #define STM32_QSPI_CCR_FMODE_SHIFT (26)
96 #define STM32_QSPI_CCR_DMODE_SHIFT (24)
97 #define STM32_QSPI_CCR_DCYC_SHIFT (18)
98 #define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
99 #define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
100 #define STM32_QSPI_CCR_ABMODE_SHIFT (14)
101 #define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
102 #define STM32_QSPI_CCR_ADMODE_SHIFT (10)
103 #define STM32_QSPI_CCR_IMODE_SHIFT (8)
104 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
106 enum STM32_QSPI_CCR_IMODE {
107 STM32_QSPI_CCR_IMODE_NONE = 0,
108 STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
109 STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
110 STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
113 enum STM32_QSPI_CCR_ADMODE {
114 STM32_QSPI_CCR_ADMODE_NONE = 0,
115 STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
116 STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
117 STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
120 enum STM32_QSPI_CCR_ADSIZE {
121 STM32_QSPI_CCR_ADSIZE_8BIT = 0,
122 STM32_QSPI_CCR_ADSIZE_16BIT = 1,
123 STM32_QSPI_CCR_ADSIZE_24BIT = 2,
124 STM32_QSPI_CCR_ADSIZE_32BIT = 3,
127 enum STM32_QSPI_CCR_ABMODE {
128 STM32_QSPI_CCR_ABMODE_NONE = 0,
129 STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
130 STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
131 STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
134 enum STM32_QSPI_CCR_ABSIZE {
135 STM32_QSPI_CCR_ABSIZE_8BIT = 0,
136 STM32_QSPI_CCR_ABSIZE_16BIT = 1,
137 STM32_QSPI_CCR_ABSIZE_24BIT = 2,
138 STM32_QSPI_CCR_ABSIZE_32BIT = 3,
141 enum STM32_QSPI_CCR_DMODE {
142 STM32_QSPI_CCR_DMODE_NONE = 0,
143 STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
144 STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
145 STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
148 enum STM32_QSPI_CCR_FMODE {
149 STM32_QSPI_CCR_IND_WRITE = 0,
150 STM32_QSPI_CCR_IND_READ = 1,
151 STM32_QSPI_CCR_AUTO_POLL = 2,
152 STM32_QSPI_CCR_MEM_MAP = 3,
155 /* default SCK frequency, unit: HZ */
156 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
158 struct stm32_qspi_platdata {
164 struct stm32_qspi_priv {
165 struct stm32_qspi_regs *regs;
173 #define CMD_HAS_ADR BIT(24)
174 #define CMD_HAS_DUMMY BIT(25)
175 #define CMD_HAS_DATA BIT(26)
178 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
180 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
183 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
185 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
188 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
190 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
194 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
196 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
200 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
202 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
206 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
208 u32 fsize = fls(size) - 1;
210 clrsetbits_le32(&priv->regs->dcr,
211 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
212 fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
215 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
217 unsigned int ccr_reg = 0;
218 u8 imode, admode, dmode;
219 u32 mode = priv->mode;
220 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
222 imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
223 admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
225 if (mode & SPI_RX_QUAD) {
226 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
227 if (mode & SPI_TX_QUAD) {
228 imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
229 admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
231 } else if (mode & SPI_RX_DUAL) {
232 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
233 if (mode & SPI_TX_DUAL) {
234 imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
235 admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
238 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
241 if (priv->command & CMD_HAS_DATA)
242 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
244 if (priv->command & CMD_HAS_DUMMY)
245 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
246 << STM32_QSPI_CCR_DCYC_SHIFT);
248 if (priv->command & CMD_HAS_ADR) {
249 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
250 << STM32_QSPI_CCR_ADSIZE_SHIFT);
251 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
253 ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
258 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
259 struct spi_flash *flash)
261 unsigned int ccr_reg;
263 priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
265 priv->dummycycles = flash->dummy_byte * 8;
267 ccr_reg = _stm32_qspi_gen_ccr(priv);
268 ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
270 _stm32_qspi_wait_for_not_busy(priv);
272 writel(ccr_reg, &priv->regs->ccr);
274 priv->dummycycles = 0;
277 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
279 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
282 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
285 writel(length - 1, &priv->regs->dlr);
288 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
290 writel(cr_reg, &priv->regs->ccr);
292 if (priv->command & CMD_HAS_ADR)
293 writel(priv->address, &priv->regs->ar);
296 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
297 struct spi_flash *flash, unsigned int bitlen,
298 const u8 *dout, u8 *din, unsigned long flags)
300 unsigned int words = bitlen / 8;
304 if (flags & SPI_XFER_MMAP) {
305 _stm32_qspi_enable_mmap(priv, flash);
307 } else if (flags & SPI_XFER_MMAP_END) {
308 _stm32_qspi_disable_mmap(priv);
316 debug("spi_xfer: Non byte aligned SPI transfer\n");
321 debug("spi_xfer: QSPI cannot have data in and data out set\n");
325 if (!dout && (flags & SPI_XFER_BEGIN)) {
326 debug("spi_xfer: QSPI transfer must begin with command\n");
331 if (flags & SPI_XFER_BEGIN) {
332 /* data is command */
333 priv->command = dout[0] | CMD_HAS_DATA;
335 /* address is here too */
336 priv->address = (dout[1] << 16) |
337 (dout[2] << 8) | dout[3];
338 priv->command |= CMD_HAS_ADR;
342 /* rest is dummy bytes */
343 priv->dummycycles = (words - 4) * 8;
344 priv->command |= CMD_HAS_DUMMY;
347 if (flags & SPI_XFER_END) {
348 /* command without data */
349 priv->command &= ~(CMD_HAS_DATA);
353 if (flags & SPI_XFER_END) {
354 ccr_reg = _stm32_qspi_gen_ccr(priv);
355 ccr_reg |= STM32_QSPI_CCR_IND_WRITE
356 << STM32_QSPI_CCR_FMODE_SHIFT;
358 _stm32_qspi_wait_for_not_busy(priv);
360 if (priv->command & CMD_HAS_DATA)
361 _stm32_qspi_set_xfer_length(priv, words);
363 _stm32_qspi_start_xfer(priv, ccr_reg);
365 debug("%s: write: ccr:0x%08x adr:0x%08x\n",
366 __func__, priv->regs->ccr, priv->regs->ar);
368 if (priv->command & CMD_HAS_DATA) {
369 _stm32_qspi_wait_for_ftf(priv);
371 debug("%s: words:%d data:", __func__, words);
375 writeb(dout[i], &priv->regs->dr);
376 debug("%02x ", dout[i]);
381 _stm32_qspi_wait_for_complete(priv);
383 _stm32_qspi_wait_for_not_busy(priv);
387 ccr_reg = _stm32_qspi_gen_ccr(priv);
388 ccr_reg |= STM32_QSPI_CCR_IND_READ
389 << STM32_QSPI_CCR_FMODE_SHIFT;
391 _stm32_qspi_wait_for_not_busy(priv);
393 _stm32_qspi_set_xfer_length(priv, words);
395 _stm32_qspi_start_xfer(priv, ccr_reg);
397 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
398 priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
400 debug("%s: data:", __func__);
404 din[i] = readb(&priv->regs->dr);
405 debug("%02x ", din[i]);
414 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
416 struct fdt_resource res_regs, res_mem;
417 struct stm32_qspi_platdata *plat = bus->platdata;
418 const void *blob = gd->fdt_blob;
419 int node = dev_of_offset(bus);
422 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
425 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
428 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
429 "qspi_mm", &res_mem);
431 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
435 plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
436 STM32_QSPI_DEFAULT_SCK_FREQ);
438 plat->base = res_regs.start;
439 plat->memory_map = res_mem.start;
441 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
451 static int stm32_qspi_probe(struct udevice *bus)
453 struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
454 struct stm32_qspi_priv *priv = dev_get_priv(bus);
455 struct dm_spi_bus *dm_spi_bus;
459 dm_spi_bus = bus->uclass_priv;
461 dm_spi_bus->max_hz = plat->max_hz;
463 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
465 priv->max_hz = plat->max_hz;
467 ret = clk_get_by_index(bus, 0, &clk);
471 ret = clk_enable(&clk);
474 dev_err(bus, "failed to enable clock\n");
478 priv->clock_rate = clk_get_rate(&clk);
479 if (priv->clock_rate < 0) {
481 return priv->clock_rate;
485 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
490 static int stm32_qspi_remove(struct udevice *bus)
495 static int stm32_qspi_claim_bus(struct udevice *dev)
497 struct stm32_qspi_priv *priv;
499 struct spi_flash *flash;
502 priv = dev_get_priv(bus);
503 flash = dev_get_uclass_priv(dev);
505 _stm32_qspi_set_flash_size(priv, flash->size);
507 _stm32_qspi_enable(priv);
512 static int stm32_qspi_release_bus(struct udevice *dev)
514 struct stm32_qspi_priv *priv;
518 priv = dev_get_priv(bus);
520 _stm32_qspi_disable(priv);
525 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
526 const void *dout, void *din, unsigned long flags)
528 struct stm32_qspi_priv *priv;
530 struct spi_flash *flash;
533 priv = dev_get_priv(bus);
534 flash = dev_get_uclass_priv(dev);
536 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
540 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
542 struct stm32_qspi_platdata *plat = bus->platdata;
543 struct stm32_qspi_priv *priv = dev_get_priv(bus);
544 u32 qspi_clk = priv->clock_rate;
548 if (speed > plat->max_hz)
549 speed = plat->max_hz;
552 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
555 else if (prescaler < 0)
559 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
560 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
562 _stm32_qspi_wait_for_not_busy(priv);
564 clrsetbits_le32(&priv->regs->cr,
565 STM32_QSPI_CR_PRESCALER_MASK <<
566 STM32_QSPI_CR_PRESCALER_SHIFT,
567 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
569 clrsetbits_le32(&priv->regs->dcr,
570 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
571 csht << STM32_QSPI_DCR_CSHT_SHIFT);
573 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
574 (qspi_clk / (prescaler + 1)));
579 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
581 struct stm32_qspi_priv *priv = dev_get_priv(bus);
583 _stm32_qspi_wait_for_not_busy(priv);
585 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
586 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
587 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
588 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
592 if (mode & SPI_CS_HIGH)
595 if (mode & SPI_RX_QUAD)
596 priv->mode |= SPI_RX_QUAD;
597 else if (mode & SPI_RX_DUAL)
598 priv->mode |= SPI_RX_DUAL;
600 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
602 if (mode & SPI_TX_QUAD)
603 priv->mode |= SPI_TX_QUAD;
604 else if (mode & SPI_TX_DUAL)
605 priv->mode |= SPI_TX_DUAL;
607 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
609 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
611 if (mode & SPI_RX_QUAD)
613 else if (mode & SPI_RX_DUAL)
616 debug("single, tx: ");
618 if (mode & SPI_TX_QUAD)
620 else if (mode & SPI_TX_DUAL)
628 static const struct dm_spi_ops stm32_qspi_ops = {
629 .claim_bus = stm32_qspi_claim_bus,
630 .release_bus = stm32_qspi_release_bus,
631 .xfer = stm32_qspi_xfer,
632 .set_speed = stm32_qspi_set_speed,
633 .set_mode = stm32_qspi_set_mode,
636 static const struct udevice_id stm32_qspi_ids[] = {
637 { .compatible = "st,stm32-qspi" },
638 { .compatible = "st,stm32f469-qspi" },
642 U_BOOT_DRIVER(stm32_qspi) = {
643 .name = "stm32_qspi",
645 .of_match = stm32_qspi_ids,
646 .ops = &stm32_qspi_ops,
647 .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
648 .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
649 .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
650 .probe = stm32_qspi_probe,
651 .remove = stm32_qspi_remove,