1 // SPDX-License-Identifier: GPL-2.0+
5 * Michael Kurz, <michi.kurz@gmail.com>
10 #define LOG_CATEGORY UCLASS_SPI
20 #include <dm/device_compat.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/iopoll.h>
24 #include <linux/ioport.h>
25 #include <linux/sizes.h>
27 struct stm32_qspi_regs {
44 * QUADSPI control register
46 #define STM32_QSPI_CR_EN BIT(0)
47 #define STM32_QSPI_CR_ABORT BIT(1)
48 #define STM32_QSPI_CR_DMAEN BIT(2)
49 #define STM32_QSPI_CR_TCEN BIT(3)
50 #define STM32_QSPI_CR_SSHIFT BIT(4)
51 #define STM32_QSPI_CR_DFM BIT(6)
52 #define STM32_QSPI_CR_FSEL BIT(7)
53 #define STM32_QSPI_CR_FTHRES_SHIFT 8
54 #define STM32_QSPI_CR_TEIE BIT(16)
55 #define STM32_QSPI_CR_TCIE BIT(17)
56 #define STM32_QSPI_CR_FTIE BIT(18)
57 #define STM32_QSPI_CR_SMIE BIT(19)
58 #define STM32_QSPI_CR_TOIE BIT(20)
59 #define STM32_QSPI_CR_APMS BIT(22)
60 #define STM32_QSPI_CR_PMM BIT(23)
61 #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
62 #define STM32_QSPI_CR_PRESCALER_SHIFT 24
65 * QUADSPI device configuration register
67 #define STM32_QSPI_DCR_CKMODE BIT(0)
68 #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
69 #define STM32_QSPI_DCR_CSHT_SHIFT 8
70 #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
71 #define STM32_QSPI_DCR_FSIZE_SHIFT 16
74 * QUADSPI status register
76 #define STM32_QSPI_SR_TEF BIT(0)
77 #define STM32_QSPI_SR_TCF BIT(1)
78 #define STM32_QSPI_SR_FTF BIT(2)
79 #define STM32_QSPI_SR_SMF BIT(3)
80 #define STM32_QSPI_SR_TOF BIT(4)
81 #define STM32_QSPI_SR_BUSY BIT(5)
84 * QUADSPI flag clear register
86 #define STM32_QSPI_FCR_CTEF BIT(0)
87 #define STM32_QSPI_FCR_CTCF BIT(1)
88 #define STM32_QSPI_FCR_CSMF BIT(3)
89 #define STM32_QSPI_FCR_CTOF BIT(4)
92 * QUADSPI communication configuration register
94 #define STM32_QSPI_CCR_DDRM BIT(31)
95 #define STM32_QSPI_CCR_DHHC BIT(30)
96 #define STM32_QSPI_CCR_SIOO BIT(28)
97 #define STM32_QSPI_CCR_FMODE_SHIFT 26
98 #define STM32_QSPI_CCR_DMODE_SHIFT 24
99 #define STM32_QSPI_CCR_DCYC_SHIFT 18
100 #define STM32_QSPI_CCR_ABSIZE_SHIFT 16
101 #define STM32_QSPI_CCR_ABMODE_SHIFT 14
102 #define STM32_QSPI_CCR_ADSIZE_SHIFT 12
103 #define STM32_QSPI_CCR_ADMODE_SHIFT 10
104 #define STM32_QSPI_CCR_IMODE_SHIFT 8
106 #define STM32_QSPI_CCR_IND_WRITE 0
107 #define STM32_QSPI_CCR_IND_READ 1
108 #define STM32_QSPI_CCR_MEM_MAP 3
110 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
111 #define STM32_QSPI_MAX_CHIP 2
113 #define STM32_QSPI_FIFO_TIMEOUT_US 30000
114 #define STM32_QSPI_CMD_TIMEOUT_US 1000000
115 #define STM32_BUSY_TIMEOUT_US 100000
116 #define STM32_ABT_TIMEOUT_US 100000
118 struct stm32_qspi_flash {
124 struct stm32_qspi_priv {
125 struct stm32_qspi_regs *regs;
126 struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
127 void __iomem *mm_base;
128 resource_size_t mm_size;
133 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
138 ret = readl_poll_timeout(&priv->regs->sr, sr,
139 !(sr & STM32_QSPI_SR_BUSY),
140 STM32_BUSY_TIMEOUT_US);
142 log_err("busy timeout (stat:%#x)\n", sr);
147 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
148 const struct spi_mem_op *op)
153 ret = readl_poll_timeout(&priv->regs->sr, sr,
154 sr & STM32_QSPI_SR_TCF,
155 STM32_QSPI_CMD_TIMEOUT_US);
157 log_err("cmd timeout (stat:%#x)\n", sr);
158 } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
159 log_err("transfer error (stat:%#x)\n", sr);
164 writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
167 ret = _stm32_qspi_wait_for_not_busy(priv);
172 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
178 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
183 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
184 const struct spi_mem_op *op)
186 void (*fifo)(u8 *val, void __iomem *addr);
187 u32 len = op->data.nbytes, sr;
191 if (op->data.dir == SPI_MEM_DATA_IN) {
192 fifo = _stm32_qspi_read_fifo;
193 buf = op->data.buf.in;
196 fifo = _stm32_qspi_write_fifo;
197 buf = (u8 *)op->data.buf.out;
201 ret = readl_poll_timeout(&priv->regs->sr, sr,
202 sr & STM32_QSPI_SR_FTF,
203 STM32_QSPI_FIFO_TIMEOUT_US);
205 log_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
209 fifo(buf++, &priv->regs->dr);
215 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
216 const struct spi_mem_op *op)
218 memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
224 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
225 const struct spi_mem_op *op,
228 if (!op->data.nbytes)
231 if (mode == STM32_QSPI_CCR_MEM_MAP)
232 return stm32_qspi_mm(priv, op);
234 return _stm32_qspi_poll(priv, op);
237 static int _stm32_qspi_get_mode(u8 buswidth)
245 static int stm32_qspi_exec_op(struct spi_slave *slave,
246 const struct spi_mem_op *op)
248 struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
249 u32 cr, ccr, addr_max;
250 u8 mode = STM32_QSPI_CCR_IND_WRITE;
253 dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
254 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
255 op->dummy.buswidth, op->data.buswidth,
256 op->addr.val, op->data.nbytes);
258 addr_max = op->addr.val + op->data.nbytes + 1;
260 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
261 if (addr_max < priv->mm_size && op->addr.buswidth)
262 mode = STM32_QSPI_CCR_MEM_MAP;
264 mode = STM32_QSPI_CCR_IND_READ;
268 writel(op->data.nbytes - 1, &priv->regs->dlr);
270 ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
271 ccr |= op->cmd.opcode;
272 ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
273 << STM32_QSPI_CCR_IMODE_SHIFT);
275 if (op->addr.nbytes) {
276 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
277 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
278 << STM32_QSPI_CCR_ADMODE_SHIFT);
281 if (op->dummy.buswidth && op->dummy.nbytes)
282 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
283 << STM32_QSPI_CCR_DCYC_SHIFT);
286 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
287 << STM32_QSPI_CCR_DMODE_SHIFT);
289 writel(ccr, &priv->regs->ccr);
291 if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
292 writel(op->addr.val, &priv->regs->ar);
294 ret = _stm32_qspi_tx(priv, op, mode);
298 * -read memory map: prefetching must be stopped if we read the last
299 * byte of device (device size - fifo size). like device size is not
300 * knows, the prefetching is always stop.
302 if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
305 /* Wait end of tx in indirect mode */
306 ret = _stm32_qspi_wait_cmd(priv, op);
313 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
315 /* Wait clear of abort bit by hw */
316 timeout = readl_poll_timeout(&priv->regs->cr, cr,
317 !(cr & STM32_QSPI_CR_ABORT),
318 STM32_ABT_TIMEOUT_US);
320 writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
323 dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout);
328 static int stm32_qspi_probe(struct udevice *bus)
330 struct stm32_qspi_priv *priv = dev_get_priv(bus);
333 struct reset_ctl reset_ctl;
336 ret = dev_read_resource_byname(bus, "qspi", &res);
338 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
342 priv->regs = (struct stm32_qspi_regs *)res.start;
344 ret = dev_read_resource_byname(bus, "qspi_mm", &res);
346 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
350 priv->mm_base = (void __iomem *)res.start;
352 priv->mm_size = resource_size(&res);
353 if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
356 dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
357 priv->regs, priv->mm_base, priv->mm_size);
359 ret = clk_get_by_index(bus, 0, &clk);
363 ret = clk_enable(&clk);
365 dev_err(bus, "failed to enable clock\n");
369 priv->clock_rate = clk_get_rate(&clk);
370 if (!priv->clock_rate) {
375 ret = reset_get_by_index(bus, 0, &reset_ctl);
377 if (ret != -ENOENT) {
378 dev_err(bus, "failed to get reset\n");
383 /* Reset QSPI controller */
384 reset_assert(&reset_ctl);
386 reset_deassert(&reset_ctl);
391 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
393 /* Set dcr fsize to max address */
394 setbits_le32(&priv->regs->dcr,
395 STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
400 static int stm32_qspi_claim_bus(struct udevice *dev)
402 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
403 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
404 int slave_cs = slave_plat->cs;
406 if (slave_cs >= STM32_QSPI_MAX_CHIP)
409 if (priv->cs_used != slave_cs) {
410 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
412 priv->cs_used = slave_cs;
414 if (flash->initialized) {
415 /* Set the configuration: speed + cs */
416 writel(flash->cr, &priv->regs->cr);
417 writel(flash->dcr, &priv->regs->dcr);
419 /* Set chip select */
420 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
421 priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
423 /* Save the configuration: speed + cs */
424 flash->cr = readl(&priv->regs->cr);
425 flash->dcr = readl(&priv->regs->dcr);
427 flash->initialized = true;
431 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
436 static int stm32_qspi_release_bus(struct udevice *dev)
438 struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
440 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
445 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
447 struct stm32_qspi_priv *priv = dev_get_priv(bus);
448 u32 qspi_clk = priv->clock_rate;
456 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
462 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
463 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
465 ret = _stm32_qspi_wait_for_not_busy(priv);
469 clrsetbits_le32(&priv->regs->cr,
470 STM32_QSPI_CR_PRESCALER_MASK <<
471 STM32_QSPI_CR_PRESCALER_SHIFT,
472 prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
474 clrsetbits_le32(&priv->regs->dcr,
475 STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
476 csht << STM32_QSPI_DCR_CSHT_SHIFT);
478 dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs,
479 (qspi_clk / (prescaler + 1)));
484 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
486 struct stm32_qspi_priv *priv = dev_get_priv(bus);
488 const char *str_rx, *str_tx;
490 ret = _stm32_qspi_wait_for_not_busy(priv);
494 if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
495 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
496 else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
497 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
501 if (mode & SPI_CS_HIGH)
504 if (mode & SPI_RX_QUAD)
506 else if (mode & SPI_RX_DUAL)
511 if (mode & SPI_TX_QUAD)
513 else if (mode & SPI_TX_DUAL)
518 dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n",
519 priv->regs, mode, str_rx, str_tx);
524 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
525 .exec_op = stm32_qspi_exec_op,
528 static const struct dm_spi_ops stm32_qspi_ops = {
529 .claim_bus = stm32_qspi_claim_bus,
530 .release_bus = stm32_qspi_release_bus,
531 .set_speed = stm32_qspi_set_speed,
532 .set_mode = stm32_qspi_set_mode,
533 .mem_ops = &stm32_qspi_mem_ops,
536 static const struct udevice_id stm32_qspi_ids[] = {
537 { .compatible = "st,stm32f469-qspi" },
541 U_BOOT_DRIVER(stm32_qspi) = {
542 .name = "stm32_qspi",
544 .of_match = stm32_qspi_ids,
545 .ops = &stm32_qspi_ops,
546 .priv_auto = sizeof(struct stm32_qspi_priv),
547 .probe = stm32_qspi_probe,