drivers/spi/sprd_spi_r4p0.c

   1 /*
   2  * Copyright (C) 2013 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/err.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/sched.h>
  24 #include <linux/kthread.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <soc/sprd/sci_glb_regs.h>
  29 #include <soc/sprd/sci.h>
  30 #include "sprd_spi_r4p0.h"
  31
  32 unsigned long REGS_SPI0_BASE = 0;
  33 unsigned long REGS_SPI1_BASE = 0;
  34 unsigned long REGS_SPI2_BASE = 0;
  35
  36 #define SPI_BASE(id) \
  37                 ((id == 0) ? REGS_SPI0_BASE : ((id == 1) ? REGS_SPI1_BASE : REGS_SPI2_BASE ))
  38
  39 #define ALIGN_UP(a, b)\
  40         (((a) + ((b) - 1)) & ~((b) - 1))
  41
  42 #define MHz(inte, dec) ((inte) * 1000 * 1000 + (dec) * 1000 * 100)
  43
  44 struct clk_src {
  45         u32 freq;
  46         const char *name;
  47 };
  48
  49 static struct clk_src spi_src_tab[] = {
  50         {
  51                 .freq = MHz(26, 0),
  52                 .name = "ext_26m",
  53         },
  54         {
  55                 .freq = MHz(96, 0),
  56                 .name = "clk_96m",
  57         },
  58         {
  59                 .freq = MHz(153, 6),
  60                 .name = "clk_153m6",
  61         },
  62         {
  63                 .freq = MHz(192, 0),
  64                 .name = "clk_192m",
  65         },
  66 };
  67
  68 struct sprd_spi_devdata {
  69         void __iomem *reg_base;
  70         int irq_num;
  71         struct clk *clk;
  72         spinlock_t lock;
  73         struct list_head msg_queue;
  74         struct work_struct work;
  75         struct workqueue_struct *work_queue;
  76         /* backup list
  77          *0  clk_div
  78          *1  ctl0
  79          *2  ctl1
  80          *3  ctl2
  81          *4  ctl3
  82          *5  ctl4
  83          *6  ctl5
  84          *7  int_en
  85          *8  dsp_wait
  86          *9  ctl6
  87          *10 ctl7
  88          */
  89         u32 reg_backup[11];
  90         bool is_active;
  91 };
  92
  93 enum spi_transfer_mode {
  94         tx_mode,
  95         rx_mode,
  96         rt_mode,
  97 };
  98
  99 //extern void clk_force_disable(struct clk *);
 100
 101 static void sprd_spi_dump_regs(unsigned long reg_base)
 102 {
 103         printk("SPI_CLKD:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CLKD)));
 104         printk("SPI_CTL0:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL0)));
 105         printk("SPI_CTL1:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL1)));
 106         printk("SPI_CTL2:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL2)));
 107         printk("SPI_CTL3:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL3)));
 108         printk("SPI_CTL4:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL4)));
 109         printk("SPI_CTL5:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL5)));
 110         printk("SPI_INT_EN:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_INT_EN)));
 111         printk("SPI_DSP_WAIT:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_DSP_WAIT)));
 112         printk("SPI_CTL6:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL6)));
 113         printk("SPI_CTL7:0x%x \n", __raw_readl((void __iomem *)(reg_base + SPI_CTL7)));
 114 }
 115
 116 static void sprd_spi_wait_for_send_complete(unsigned long reg_base)
 117 {
 118         u32 timeout = 0;
 119         while (!(__raw_readl((void __iomem *)(reg_base + SPI_STS2)) & SPI_TX_FIFO_REALLY_EMPTY))
 120         {
 121                 if (++timeout > SPI_TIME_OUT) {
 122                         /*fixme, set timeout*/
 123                         printk("spi send timeout!\n");
 124                         sprd_spi_dump_regs(reg_base);
 125                         BUG_ON(1);
 126                 }
 127         }
 128
 129         while (__raw_readl((void __iomem *)(reg_base + SPI_STS2)) & SPI_TX_BUSY)
 130         {
 131                 if (++timeout > SPI_TIME_OUT) {
 132                         /*fixme, set timeout*/
 133                         printk("spi send timeout!\n");
 134                         sprd_spi_dump_regs(reg_base);
 135                         BUG_ON(1);
 136                 }
 137         }
 138 }
 139
 140 static int sprd_spi_transfer_full_duplex(struct spi_device *spi_dev,
 141         struct spi_transfer *trans_node)
 142 {
 143         int i;
 144         u32 reg_val;
 145         u32 bits_per_word, block_num;
 146         u32 send_data_msk;
 147         u8 *tx_u8_p, *rx_u8_p;
 148         u16 *tx_u16_p, *rx_u16_p;
 149         u32 *tx_u32_p, *rx_u32_p;
 150         const void *src_buf;
 151         void *dst_buf;
 152         u32 transfer_mode;
 153         unsigned long reg_base;
 154         struct sprd_spi_devdata *spi_chip;
 155
 156         spi_chip = spi_master_get_devdata(spi_dev->master);
 157         reg_base = (unsigned long)spi_chip->reg_base;
 158 #if 0
 159         /* We config the bits_per_word in function spi_new_device()
 160          * but you can reconfig thi option in spi_transfer
 161          */
 162         if (unlikely(trans_node->bits_per_word != spi_dev->bits_per_word)) {
 163                 printk("%s %d\n", __func__, __LINE__);
 164                 reg_val = __raw_readl(spi_chip->reg_base + SPI_CTL0);
 165                 reg_val &= ~(0x1f << 2);
 166                 if (trans_node->bits_per_word != MAX_BITS_PER_WORD) {
 167                         reg_val |= trans_node->bits_per_word << 2;
 168                         printk("%s %d\n", __func__, __LINE__);
 169                 }
 170                 __raw_writel(reg_val, spi_chip->reg_base + SPI_CTL0);
 171         }
 172         /*fixme!the bits_per_word alaign up with 8*/
 173         bytes_per_word = ALIGN_UP(trans_node->bits_per_word, 8) >> 3;
 174 #else
 175         bits_per_word = ALIGN_UP(spi_dev->bits_per_word, 8);
 176
 177         reg_val = __raw_readl((void __iomem *)(reg_base + SPI_CTL0));
 178         reg_val &= ~(0x1f << 2);
 179         if (32 != bits_per_word) {
 180                 reg_val |= bits_per_word << 2;
 181         }
 182         writel(reg_val, (void __iomem *)(reg_base + SPI_CTL0));
 183
 184 #endif
 185         /*send data buf*/
 186         src_buf = trans_node->tx_buf;
 187
 188         /*recv data buf*/
 189         dst_buf = trans_node->rx_buf;
 190
 191         send_data_msk = 0xffffffff;
 192
 193         if (src_buf && dst_buf) {
 194                 transfer_mode = rt_mode;
 195         } else {
 196                 if (dst_buf) {
 197                         transfer_mode = rx_mode;
 198                         /*in rx mode, we always send 0 to slave*/
 199                         send_data_msk = 0x0;
 200                         src_buf = trans_node->rx_buf;
 201                 } else {
 202                         transfer_mode = tx_mode;
 203                 }
 204         }
 205
 206         reg_val = __raw_readl((void __iomem *)(reg_base + SPI_CTL1));
 207
 208         reg_val &= ~(0x3 << 12);
 209
 210         if (transfer_mode == tx_mode) {
 211                 reg_val |= SPI_TX_MODE;
 212         } else {
 213                 reg_val |= SPI_RX_MODE |SPI_TX_MODE;
 214         }
 215
 216         writel(reg_val, (void __iomem *)(reg_base + SPI_CTL1));
 217
 218         /*reset the fifo*/
 219         writel(0x1, (void __iomem *)(reg_base + SPI_FIFO_RST));
 220         writel(0x0, (void __iomem *)(reg_base + SPI_FIFO_RST));
 221
 222         /*alaway set cs pin to low level when transfer */
 223         if (spi_dev->chip_select < SPRD_SPI_CHIP_CS_NUM) {
 224                 reg_val = __raw_readl((void __iomem *)(reg_base + SPI_CTL0));
 225                 reg_val &= ~(0x1 << (spi_dev->chip_select + 8));
 226                 writel(reg_val, (void __iomem *)(reg_base + SPI_CTL0));
 227         } else {
 228                 /*fixme, need to support gpio cs*/
 229         }
 230
 231         switch (bits_per_word) {
 232         case 8:
 233                 tx_u8_p = (u8 *)src_buf;
 234                 rx_u8_p = (u8 *)dst_buf;
 235                 block_num = trans_node->len;
 236                 for (; block_num >= SPRD_SPI_FIFO_SIZE; block_num -= SPRD_SPI_FIFO_SIZE)
 237                 {
 238                         for (i = 0; i < SPRD_SPI_FIFO_SIZE; i++, tx_u8_p++)
 239                         {
 240                                 __raw_writeb(*tx_u8_p & send_data_msk,
 241                                         (void __iomem *)(reg_base + SPI_TXD));
 242                         }
 243
 244                         sprd_spi_wait_for_send_complete(reg_base);
 245
 246                         if (transfer_mode == tx_mode)
 247                                 continue;
 248
 249                         for (i = 0; i < SPRD_SPI_FIFO_SIZE; i++, rx_u8_p++)
 250                         {
 251                                 *rx_u8_p = __raw_readb((void __iomem *)(reg_base + SPI_TXD));
 252                         }
 253                 }
 254
 255                 for (i = 0; i < block_num; i++, tx_u8_p++)
 256                 {
 257                         __raw_writeb(*tx_u8_p & send_data_msk, (void __iomem *)(reg_base + SPI_TXD));
 258                 }
 259
 260                 sprd_spi_wait_for_send_complete(reg_base);
 261
 262                 if (transfer_mode == tx_mode)
 263                         break;
 264
 265                 for (i = 0; i < block_num; i++, rx_u8_p++)
 266                 {
 267                         *rx_u8_p = __raw_readb((void __iomem *)(reg_base + SPI_TXD));
 268                 }
 269                 break;
 270
 271         case 16:
 272                 tx_u16_p = (u16 *)src_buf;
 273                 rx_u16_p = (u16 *)dst_buf;
 274                 block_num = trans_node->len >> 1;
 275
 276                 for (;block_num >= SPRD_SPI_FIFO_SIZE; block_num -= SPRD_SPI_FIFO_SIZE)
 277                 {
 278                         for (i =0; i < SPRD_SPI_FIFO_SIZE; i++, tx_u16_p++)
 279                         {
 280                                 __raw_writew(*tx_u16_p & send_data_msk,
 281                                         (void __iomem *)(reg_base + SPI_TXD));
 282                         }
 283
 284                         sprd_spi_wait_for_send_complete(reg_base);
 285
 286                         if (transfer_mode == tx_mode)
 287                                 continue;
 288
 289                         for (i = 0; i < SPRD_SPI_FIFO_SIZE; i++, rx_u16_p++)
 290                         {
 291                                 *rx_u16_p = __raw_readw((void __iomem *)(reg_base + SPI_TXD));
 292                         }
 293                 }
 294
 295                 for (i = 0; i < block_num; i++, tx_u16_p++)
 296                 {
 297                         __raw_writew(*tx_u16_p & send_data_msk, (void __iomem *)(reg_base + SPI_TXD));
 298                 }
 299
 300                 sprd_spi_wait_for_send_complete(reg_base);
 301
 302                 if (transfer_mode == tx_mode)
 303                         break;
 304
 305                 for (i = 0; i < block_num; i++, rx_u16_p++)
 306                 {
 307                         *rx_u16_p = __raw_readw((void __iomem *)(reg_base + SPI_TXD));
 308                 }
 309                 break;
 310
 311         case 32:
 312                 tx_u32_p = (u32 *)src_buf;
 313                 rx_u32_p = (u32 *)dst_buf;
 314                 block_num = (trans_node->len + 3) >> 2;
 315
 316                 for (;block_num >= SPRD_SPI_FIFO_SIZE; block_num -= SPRD_SPI_FIFO_SIZE)
 317                 {
 318                         for (i = 0; i < SPRD_SPI_FIFO_SIZE; i++, tx_u32_p++)
 319                         {
 320                                 __raw_writel(*tx_u32_p & send_data_msk,
 321                                         (void __iomem *)(reg_base + SPI_TXD));
 322                         }
 323
 324                         sprd_spi_wait_for_send_complete(reg_base);
 325
 326                         if (transfer_mode == tx_mode)
 327                                 continue;
 328
 329                         for (i = 0; i < SPRD_SPI_FIFO_SIZE; i++, rx_u32_p++)
 330                         {
 331                                 *rx_u32_p = __raw_readl((void __iomem *)(reg_base + SPI_TXD));
 332                         }
 333                 }
 334
 335                 for (i = 0; i < block_num; i++, tx_u32_p++)
 336                 {
 337                         __raw_writel(*tx_u32_p & send_data_msk, (void __iomem *)(reg_base + SPI_TXD));
 338                 }
 339
 340                 sprd_spi_wait_for_send_complete(reg_base);
 341
 342                 if (transfer_mode == tx_mode)
 343                         break;
 344
 345                 for (i = 0; i < block_num; i++, rx_u32_p++)
 346                 {
 347                         *rx_u32_p = __raw_readl((void __iomem *)(reg_base + SPI_TXD));
 348                 }
 349
 350                 break;
 351         default:
 352                 /*fixme*/
 353                 break;
 354         }
 355
 356         if (spi_dev->chip_select < SPRD_SPI_CHIP_CS_NUM) {
 357                 reg_val = __raw_readl((void __iomem *)(reg_base + SPI_CTL0));
 358                 reg_val |= 0xf << 8;
 359                 __raw_writel(reg_val, (void __iomem *)(reg_base + SPI_CTL0));
 360         } else {
 361                 /*fixme, need to support gpio cs*/
 362         }
 363
 364         reg_val = __raw_readl((void __iomem *)(reg_base + SPI_CTL1));
 365         reg_val &= ~(0x3 << 12);
 366         writel(reg_val, (void __iomem *)(reg_base + SPI_CTL1));
 367
 368         return trans_node->len;
 369 }
 370
 371 static void  sprd_spi_transfer_work(struct work_struct *work)
 372 {
 373         int ret;
 374         struct sprd_spi_devdata *spi_chip;
 375         struct spi_message *spi_msg;
 376         struct spi_transfer *transfer_node;
 377         unsigned long flags;
 378
 379         spi_chip = container_of(work, struct sprd_spi_devdata, work);
 380
 381         clk_prepare_enable(spi_chip->clk);
 382
 383         /*fixme*/
 384         spin_lock_irqsave(&spi_chip->lock, flags);
 385
 386         while (!list_empty(&spi_chip->msg_queue))
 387         {
 388                 spi_msg = container_of(spi_chip->msg_queue.next,
 389                         struct spi_message, queue);
 390                 list_del_init(&spi_msg->queue);
 391                 spin_unlock_irqrestore(&spi_chip->lock, flags);
 392
 393                 list_for_each_entry(transfer_node,
 394                         &spi_msg->transfers, transfer_list)
 395                 {
 396                         if (transfer_node->tx_buf || transfer_node->rx_buf) {
 397                                 ret = sprd_spi_transfer_full_duplex(spi_msg->spi,
 398                                         transfer_node);
 399                         }
 400                 }
 401
 402                 if (spi_msg->complete) {
 403                         spi_msg->status = 0x0;
 404                         spi_msg->complete(spi_msg->context);
 405                 }
 406                 spin_lock_irqsave(&spi_chip->lock, flags);
 407         }
 408
 409         //clk_disable_unprepare(spi_chip->clk);
 410
 411         spin_unlock_irqrestore(&spi_chip->lock, flags);
 412
 413         clk_disable_unprepare(spi_chip->clk);
 414 }
 415
 416 static int sprd_spi_transfer(struct spi_device *spi_dev, struct spi_message *msg)
 417 {
 418         struct sprd_spi_devdata *spi_chip;
 419         unsigned long flags;
 420
 421         spi_chip = spi_master_get_devdata(spi_dev->master);
 422
 423         spin_lock_irqsave(&spi_chip->lock, flags);
 424
 425         list_add_tail(&msg->queue, &spi_chip->msg_queue);
 426
 427         queue_work(spi_chip->work_queue, &spi_chip->work);
 428
 429         spin_unlock_irqrestore(&spi_chip->lock, flags);
 430
 431         return 0;
 432 }
 433
 434 /*this function must be exectued in spi's clk is enable*/
 435 static void sprd_spi_backup_config(struct sprd_spi_devdata *spi_chip)
 436 {
 437         unsigned long reg_base;
 438
 439         reg_base = (unsigned long)spi_chip->reg_base;
 440
 441         spi_chip->reg_backup[0] = __raw_readl((void __iomem *)(reg_base + SPI_CLKD));
 442         spi_chip->reg_backup[1] = __raw_readl((void __iomem *)(reg_base + SPI_CTL0));
 443         spi_chip->reg_backup[2] = __raw_readl((void __iomem *)(reg_base + SPI_CTL1));
 444         spi_chip->reg_backup[3] = __raw_readl((void __iomem *)(reg_base + SPI_CTL2));
 445         spi_chip->reg_backup[4] = __raw_readl((void __iomem *)(reg_base + SPI_CTL3));
 446         spi_chip->reg_backup[5] = __raw_readl((void __iomem *)(reg_base + SPI_CTL4));
 447         spi_chip->reg_backup[6] = __raw_readl((void __iomem *)(reg_base + SPI_CTL5));
 448         spi_chip->reg_backup[7] = __raw_readl((void __iomem *)(reg_base + SPI_INT_EN));
 449         spi_chip->reg_backup[8] = __raw_readl((void __iomem *)(reg_base + SPI_DSP_WAIT));
 450         spi_chip->reg_backup[9] = __raw_readl((void __iomem *)(reg_base + SPI_CTL6));
 451         spi_chip->reg_backup[10] = __raw_readl((void __iomem *)(reg_base + SPI_CTL7));
 452 }
 453
 454 /*this function must be exectued in spi's clk is enable*/
 455 static void sprd_spi_restore_config(const struct sprd_spi_devdata *spi_chip)
 456 {
 457         unsigned long reg_base;
 458
 459         reg_base = (unsigned long)spi_chip->reg_base;
 460
 461         __raw_writel(spi_chip->reg_backup[0], (void __iomem *)(reg_base + SPI_CLKD));
 462         __raw_writel(spi_chip->reg_backup[1], (void __iomem *)(reg_base + SPI_CTL0));
 463         __raw_writel(spi_chip->reg_backup[2], (void __iomem *)(reg_base + SPI_CTL1));
 464         __raw_writel(spi_chip->reg_backup[3], (void __iomem *)(reg_base + SPI_CTL2));
 465         __raw_writel(spi_chip->reg_backup[4], (void __iomem *)(reg_base + SPI_CTL3));
 466         __raw_writel(spi_chip->reg_backup[5], (void __iomem *)(reg_base + SPI_CTL4));
 467         __raw_writel(spi_chip->reg_backup[6], (void __iomem *)(reg_base + SPI_CTL5));
 468         __raw_writel(spi_chip->reg_backup[7], (void __iomem *)(reg_base + SPI_INT_EN));
 469         __raw_writel(spi_chip->reg_backup[8], (void __iomem *)(reg_base + SPI_DSP_WAIT));
 470         __raw_writel(spi_chip->reg_backup[9], (void __iomem *)(reg_base + SPI_CTL6));
 471         __raw_writel(spi_chip->reg_backup[10], (void __iomem *)(reg_base + SPI_CTL7));
 472 }
 473
 474 static int sprd_spi_setup(struct spi_device *spi_dev)
 475 {
 476         int i;
 477         u32 reg_val;
 478         u32 spi_work_clk, spi_src_clk, spi_clk_div;
 479         const char *src_clk_name;
 480         struct clk *clk_parent;
 481         struct sprd_spi_devdata *spi_chip;
 482
 483         spi_chip = spi_master_get_devdata(spi_dev->master);
 484
 485         /*fixme, need to check the parmeter*/
 486
 487         /*if the spi_src_clk is 48MHz,the spi max working clk is 24MHz*/
 488         spi_work_clk = spi_dev->max_speed_hz << 1;
 489         if (spi_work_clk > MHz(192, 0))
 490                 return -EINVAL;
 491         for(i = 0; i < ARRAY_SIZE(spi_src_tab); i++)  {
 492                 if(!(spi_src_tab[i].freq % spi_work_clk))
 493                         break;
 494         }
 495         if(i == ARRAY_SIZE(spi_src_tab))
 496                 i--;
 497         src_clk_name = spi_src_tab[i].name;
 498         spi_src_clk = spi_src_tab[i].freq;
 499
 500         clk_parent = clk_get(&(spi_dev->master->dev), src_clk_name);
 501         if (IS_ERR(clk_parent)) {
 502                 printk("Can't get the clock source: %s\n", src_clk_name);
 503                 return -EINVAL;
 504         }
 505
 506         clk_set_parent(spi_chip->clk, clk_parent);
 507
 508         /*global enable*/
 509         clk_prepare_enable(spi_chip->clk);
 510
 511         /*spi config*/
 512         if (spi_dev->bits_per_word > MAX_BITS_PER_WORD) {
 513                 /*fixme*/
 514         }
 515
 516         /*the default bits_per_word is 8*/
 517         if (spi_dev->bits_per_word == MAX_BITS_PER_WORD) {
 518                 reg_val = 0x0 << 2;
 519         } else {
 520                 reg_val = spi_dev->bits_per_word << 2;
 521         }
 522
 523         /*set all cs to high level*/
 524         reg_val |= 0xf << 8;
 525
 526         /*spi mode config*/
 527         switch (spi_dev->mode & 0x3) {
 528         case SPI_MODE_0:
 529                 reg_val |= BIT(1);
 530                 break;
 531         case SPI_MODE_1:
 532                 reg_val |= BIT(0);
 533                 break;
 534         case SPI_MODE_2:
 535                 reg_val |= BIT(13) | BIT(1);
 536                 break;
 537         case SPI_MODE_3:
 538                 reg_val |= BIT(13) | BIT(0);
 539                 break;
 540         default:
 541                 /*fixme*/
 542                 break;
 543         }
 544         __raw_writel(reg_val, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_CTL0));
 545         __raw_writel(0x0, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_CTL1));
 546         /*spi master mode*/
 547         __raw_writel(0x0, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_CTL2));
 548         __raw_writel(0x0, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_CTL4));
 549         __raw_writel(0x9, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_CTL5));
 550         __raw_writel(0x0, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_INT_EN));
 551         /*reset fifo*/
 552         __raw_writel(0x1, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_FIFO_RST));
 553         for (i = 0; i < 0x20; i++);
 554         __raw_writel(0x0, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_FIFO_RST));
 555
 556         clk_set_rate(spi_chip->clk, spi_src_clk);
 557
 558         spi_clk_div = spi_src_clk / (spi_dev->max_speed_hz << 1) - 1;
 559
 560         __raw_writel(spi_clk_div, (void __iomem *)((unsigned long)spi_chip->reg_base + SPI_CLKD));
 561
 562         /*wait the clk config become effective*/
 563         msleep(5);
 564
 565         sprd_spi_backup_config(spi_chip);
 566         spi_chip->is_active = true;
 567
 568         /*disable the clk after config complete*/
 569         clk_disable_unprepare(spi_chip->clk);
 570
 571         return 0;
 572 }
 573
 574 static void sprd_spi_cleanup(struct spi_device *spi)
 575 {
 576         struct sprd_spi_devdata *spi_chip;
 577
 578         spi_chip = spi_master_get_devdata(spi->master);
 579
 580         clk_disable_unprepare(spi_chip->clk);
 581 }
 582
 583 static int sprd_spi_probe(struct platform_device *pdev)
 584 {
 585         int ret;
 586         int irq_num;
 587         struct resource *regs;
 588         struct spi_master *master;
 589         struct sprd_spi_devdata *spi_chip;
 590
 591         pdev->id = of_alias_get_id(pdev->dev.of_node, "spi");
 592
 593         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 594         if (!regs) {
 595                 dev_err(&pdev->dev, "spi_%d get io resource failed!\n", pdev->id);
 596                 return -ENODEV;
 597         }
 598
 599         if (0 == pdev->id) {
 600                 REGS_SPI0_BASE = (unsigned long)ioremap_nocache(regs->start,
 601                                 resource_size(regs));
 602                 if (!REGS_SPI0_BASE)
 603                         BUG();
 604         }
 605         else if (1 == pdev->id) {
 606                 REGS_SPI1_BASE = (unsigned long)ioremap_nocache(regs->start,
 607                                 resource_size(regs));
 608                 if (!REGS_SPI1_BASE)
 609                         BUG();
 610         }
 611         else if (2 == pdev->id) {
 612                 REGS_SPI2_BASE = (unsigned long)ioremap_nocache(regs->start,
 613                                 resource_size(regs));
 614                 if (!REGS_SPI2_BASE)
 615                         BUG();
 616         }
 617
 618         dev_info(&pdev->dev, "probe spi %d get regbase 0x%lx\n", pdev->id,
 619                         SPI_BASE(pdev->id));
 620
 621         irq_num = platform_get_irq(pdev, 0);
 622         if (irq_num < 0) {
 623                 dev_err(&pdev->dev, "spi_%d get irq resource failed!\n", pdev->id);
 624                 return irq_num;
 625         }
 626         dev_info(&pdev->dev, "probe spi %d get irq num %d\n", pdev->id, irq_num);
 627
 628         master = spi_alloc_master(&pdev->dev, sizeof (*spi_chip));
 629         if (!master) {
 630                 dev_err(&pdev->dev, "spi_%d spi_alloc_master failed!\n", pdev->id);
 631                 return -ENOMEM;
 632         }
 633
 634         spi_chip = spi_master_get_devdata(master);
 635
 636         /*get clk source*/
 637         switch (pdev->id) {
 638                 case sprd_spi_0:
 639                         spi_chip->clk = clk_get(NULL, "clk_spi0");
 640                         break;
 641                 case sprd_spi_1:
 642                         spi_chip->clk = clk_get(NULL, "clk_spi1");
 643                         break;
 644                 case sprd_spi_2:
 645                         spi_chip->clk = clk_get(NULL, "clk_spi2");
 646                         break;
 647                 default:
 648                         ret = -EINVAL;
 649                         goto err_exit;
 650         }
 651         if (IS_ERR(spi_chip->clk)) {
 652                 ret = -ENXIO;
 653                 goto err_exit;
 654         }
 655         spi_chip->reg_base = (void __iomem *)SPI_BASE(pdev->id);
 656         spi_chip->irq_num  = irq_num;
 657
 658         master->mode_bits = SPI_CPOL | SPI_CPHA;
 659         master->bus_num = pdev->id;
 660         master->num_chipselect = SPRD_SPI_CHIP_CS_NUM;
 661
 662         master->setup = sprd_spi_setup;
 663 #ifdef SPI_NEW_INTERFACE
 664         master->prepare_transfer_hardware = xxxxx;
 665         master->transfer_one_message = xxxx;
 666         master->unprepare_transfer_hardware = xxxx;
 667 #else
 668         master->transfer = sprd_spi_transfer;
 669         master->cleanup = sprd_spi_cleanup;
 670 #endif
 671
 672         INIT_LIST_HEAD(&spi_chip->msg_queue);
 673         spin_lock_init(&spi_chip->lock);
 674         /*on multi core system, use the create_workqueue() is better??*/
 675 //      spi_chip->work_queue = create_singlethread_workqueue(pdev->name);
 676         spi_chip->work_queue = create_workqueue(pdev->name);
 677         INIT_WORK(&spi_chip->work, sprd_spi_transfer_work);
 678
 679         platform_set_drvdata(pdev, master);
 680
 681         ret = spi_register_master(master);
 682         if (ret) {
 683                 printk("register spi master %d failed!\n", master->bus_num);
 684                 goto err_exit;
 685         }
 686
 687         return 0;
 688
 689 err_exit:
 690         spi_master_put(master);
 691         kfree(master);
 692
 693         return ret;
 694 }
 695
 696 static int __exit sprd_spi_remove(struct platform_device *pdev)
 697 {
 698         struct spi_master *master = platform_get_drvdata(pdev);
 699         struct sprd_spi_devdata *spi_chip = spi_master_get_devdata(master);
 700
 701         destroy_workqueue(spi_chip->work_queue);
 702
 703         clk_disable_unprepare(spi_chip->clk);
 704
 705         spi_unregister_master(master);
 706
 707         spi_master_put(master);
 708
 709         return 0;
 710 }
 711
 712 #ifdef CONFIG_PM
 713 static int sprd_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 714 {
 715         struct spi_master *master = platform_get_drvdata(pdev);
 716
 717         struct sprd_spi_devdata *spi_chip = spi_master_get_devdata(master);
 718         if (IS_ERR(spi_chip->clk)) {
 719                 pr_err("can't get spi_clk when suspend()\n");
 720                 return -1;
 721         }
 722
 723         if (spi_chip->is_active)
 724                 clk_disable_unprepare(spi_chip->clk);
 725
 726         return 0;
 727 }
 728
 729 static int sprd_spi_resume(struct platform_device *pdev)
 730 {
 731         struct spi_master *master = platform_get_drvdata(pdev);
 732
 733         struct sprd_spi_devdata *spi_chip = spi_master_get_devdata(master);
 734
 735         if (spi_chip->is_active) {
 736
 737                 clk_prepare_enable(spi_chip->clk);
 738
 739                 sprd_spi_restore_config(spi_chip);
 740
 741                 clk_disable_unprepare(spi_chip->clk);
 742         }
 743
 744         return 0;
 745 }
 746
 747 #else
 748 #define sprd_spi_suspend NULL
 749 #define sprd_spi_resume NULL
 750 #endif
 751
 752 static const struct of_device_id sprd_spi_of_match[] = {
 753         { .compatible = "sprd,sprd-spi", },
 754         { /* sentinel */ }
 755 };
 756
 757 static struct platform_driver sprd_spi_driver = {
 758         .driver = {
 759                 .name = "sprd spi",
 760                 .owner = THIS_MODULE,
 761                 .of_match_table = of_match_ptr(sprd_spi_of_match),
 762         },
 763         .suspend = sprd_spi_suspend,
 764         .resume  = sprd_spi_resume,
 765         .probe = sprd_spi_probe,
 766         .remove  = __exit_p(sprd_spi_remove),
 767 };
 768
 769 static int __init sprd_spi_init(void)
 770 {
 771         return platform_driver_register(&sprd_spi_driver);
 772 }
 773
 774 subsys_initcall(sprd_spi_init);
 775
 776 static void __exit sprd_spi_exit(void)
 777 {
 778         platform_driver_unregister(&sprd_spi_driver);
 779 }
 780
 781 module_exit(sprd_spi_exit);
 782
 783 MODULE_DESCRIPTION("SpreadTrum SPI(r4p0 version) Controller driver");
 784 MODULE_AUTHOR("Jack.Jiang <Jack.Jiang@spreadtrum.com>");
 785 MODULE_LICENSE("GPL");