2 * SPI_PPC4XX SPI controller driver.
4 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
5 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
8 * Based in part on drivers/spi/spi_s3c24xx.c
10 * Copyright (c) 2006 Ben Dooks
11 * Copyright (c) 2006 Simtec Electronics
12 * Ben Dooks <ben@simtec.co.uk>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
20 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
21 * generate an interrupt to the CPU. This can cause high CPU utilization.
22 * This driver allows platforms to reduce the interrupt load on the CPU
23 * during SPI transfers by setting max_speed_hz via the device tree.
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/errno.h>
31 #include <linux/wait.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_spi.h>
34 #include <linux/of_gpio.h>
35 #include <linux/interrupt.h>
36 #include <linux/delay.h>
38 #include <linux/gpio.h>
39 #include <linux/spi/spi.h>
40 #include <linux/spi/spi_bitbang.h>
44 #include <asm/dcr-regs.h>
46 /* bits in mode register - bit 0 is MSb */
49 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
50 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
51 * Note: This is the inverse of CPHA.
53 #define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
55 /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
56 #define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
59 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
60 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
61 * Note: This is identical to SPI_LSB_FIRST.
63 #define SPI_PPC4XX_MODE_RD (0x80 >> 5)
66 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
67 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
68 * Note: This is identical to CPOL.
70 #define SPI_PPC4XX_MODE_CI (0x80 >> 6)
73 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
74 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
76 #define SPI_PPC4XX_MODE_IL (0x80 >> 7)
78 /* bits in control register */
79 /* starts a transfer when set */
80 #define SPI_PPC4XX_CR_STR (0x80 >> 7)
82 /* bits in status register */
83 /* port is busy with a transfer */
84 #define SPI_PPC4XX_SR_BSY (0x80 >> 6)
86 #define SPI_PPC4XX_SR_RBR (0x80 >> 7)
88 /* clock settings (SCP and CI) for various SPI modes */
89 #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
90 #define SPI_CLK_MODE1 (0 | 0)
91 #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
92 #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
94 #define DRIVER_NAME "spi_ppc4xx_of"
96 struct spi_ppc4xx_regs {
104 * Clock divisor modulus register
105 * This uses the follwing formula:
106 * SCPClkOut = OPBCLK/(4(CDM + 1))
108 * CDM = (OPBCLK/4*SCPClkOut) - 1
114 /* SPI Controller driver's private data. */
116 /* bitbang has to be first */
117 struct spi_bitbang bitbang;
118 struct completion done;
123 /* need this to set the SPI clock */
124 unsigned int opb_freq;
130 const unsigned char *tx;
135 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
136 struct spi_master *master;
140 /* need this so we can set the clock in the chipselect routine */
141 struct spi_ppc4xx_cs {
145 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
147 struct ppc4xx_spi *hw;
150 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
151 t->tx_buf, t->rx_buf, t->len);
153 hw = spi_master_get_devdata(spi->master);
160 /* send the first byte */
161 data = hw->tx ? hw->tx[0] : 0;
162 out_8(&hw->regs->txd, data);
163 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
164 wait_for_completion(&hw->done);
169 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
171 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
172 struct spi_ppc4xx_cs *cs = spi->controller_state;
178 /* Start with the generic configuration for this device. */
179 bits_per_word = spi->bits_per_word;
180 speed = spi->max_speed_hz;
183 * Modify the configuration if the transfer overrides it. Do not allow
184 * the transfer to overwrite the generic configuration with zeros.
187 if (t->bits_per_word)
188 bits_per_word = t->bits_per_word;
191 speed = min(t->speed_hz, spi->max_speed_hz);
194 if (bits_per_word != 8) {
195 dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
200 if (!speed || (speed > spi->max_speed_hz)) {
201 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
205 /* Write new configration */
206 out_8(&hw->regs->mode, cs->mode);
209 /* opb_freq was already divided by 4 */
210 scr = (hw->opb_freq / speed) - 1;
212 cdm = min(scr, 0xff);
214 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
216 if (in_8(&hw->regs->cdm) != cdm)
217 out_8(&hw->regs->cdm, cdm);
219 spin_lock(&hw->bitbang.lock);
220 if (!hw->bitbang.busy) {
221 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
222 /* Need to ndelay here? */
224 spin_unlock(&hw->bitbang.lock);
229 static int spi_ppc4xx_setup(struct spi_device *spi)
231 struct spi_ppc4xx_cs *cs = spi->controller_state;
233 if (spi->bits_per_word != 8) {
234 dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
239 if (!spi->max_speed_hz) {
240 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
245 cs = kzalloc(sizeof *cs, GFP_KERNEL);
248 spi->controller_state = cs;
252 * We set all bits of the SPI0_MODE register, so,
253 * no need to read-modify-write
255 cs->mode = SPI_PPC4XX_MODE_SPE;
257 switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
259 cs->mode |= SPI_CLK_MODE0;
262 cs->mode |= SPI_CLK_MODE1;
265 cs->mode |= SPI_CLK_MODE2;
268 cs->mode |= SPI_CLK_MODE3;
272 if (spi->mode & SPI_LSB_FIRST)
273 cs->mode |= SPI_PPC4XX_MODE_RD;
278 static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
280 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
281 unsigned int cs = spi->chip_select;
285 * If there are no chip selects at all, or if this is the special
286 * case of a non-existent (dummy) chip select, do nothing.
289 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
292 cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
293 if (value == BITBANG_CS_INACTIVE)
296 gpio_set_value(hw->gpios[cs], cspol);
299 static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
301 struct ppc4xx_spi *hw;
306 hw = (struct ppc4xx_spi *)dev_id;
308 status = in_8(&hw->regs->sr);
313 * BSY de-asserts one cycle after the transfer is complete. The
314 * interrupt is asserted after the transfer is complete. The exact
315 * relationship is not documented, hence this code.
318 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
322 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
325 lstatus = in_8(&hw->regs->sr);
326 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
329 dev_err(hw->dev, "busywait: too many loops!\n");
333 /* status is always 1 (RBR) here */
334 status = in_8(&hw->regs->sr);
335 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
342 /* RBR triggered this interrupt. Therefore, data must be ready. */
343 data = in_8(&hw->regs->rxd);
345 hw->rx[count] = data;
349 if (count < hw->len) {
350 data = hw->tx ? hw->tx[count] : 0;
351 out_8(&hw->regs->txd, data);
352 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
360 static void spi_ppc4xx_cleanup(struct spi_device *spi)
362 kfree(spi->controller_state);
365 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
368 * On all 4xx PPC's the SPI bus is shared/multiplexed with
369 * the 2nd I2C bus. We need to enable the the SPI bus before
373 /* need to clear bit 14 to enable SPC */
374 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
377 static void free_gpios(struct ppc4xx_spi *hw)
379 if (hw->master->num_chipselect) {
381 for (i = 0; i < hw->master->num_chipselect; i++)
382 if (gpio_is_valid(hw->gpios[i]))
383 gpio_free(hw->gpios[i]);
391 * platform_device layer stuff...
393 static int __init spi_ppc4xx_of_probe(struct platform_device *op,
394 const struct of_device_id *match)
396 struct ppc4xx_spi *hw;
397 struct spi_master *master;
398 struct spi_bitbang *bbp;
399 struct resource resource;
400 struct device_node *np = op->dev.of_node;
401 struct device *dev = &op->dev;
402 struct device_node *opbnp;
405 const unsigned int *clk;
407 master = spi_alloc_master(dev, sizeof *hw);
410 master->dev.of_node = np;
411 dev_set_drvdata(dev, master);
412 hw = spi_master_get_devdata(master);
413 hw->master = spi_master_get(master);
416 init_completion(&hw->done);
419 * A count of zero implies a single SPI device without any chip-select.
420 * Note that of_gpio_count counts all gpios assigned to this spi master.
421 * This includes both "null" gpio's and real ones.
423 num_gpios = of_gpio_count(np);
427 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
433 for (i = 0; i < num_gpios; i++) {
435 enum of_gpio_flags flags;
437 gpio = of_get_gpio_flags(np, i, &flags);
440 if (gpio_is_valid(gpio)) {
441 /* Real CS - set the initial state. */
442 ret = gpio_request(gpio, np->name);
444 dev_err(dev, "can't request gpio "
445 "#%d: %d\n", i, ret);
449 gpio_direction_output(gpio,
450 !!(flags & OF_GPIO_ACTIVE_LOW));
451 } else if (gpio == -EEXIST) {
452 ; /* No CS, but that's OK. */
454 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
461 /* Setup the state for the bitbang driver */
463 bbp->master = hw->master;
464 bbp->setup_transfer = spi_ppc4xx_setupxfer;
465 bbp->chipselect = spi_ppc4xx_chipsel;
466 bbp->txrx_bufs = spi_ppc4xx_txrx;
468 bbp->master->setup = spi_ppc4xx_setup;
469 bbp->master->cleanup = spi_ppc4xx_cleanup;
471 /* Allocate bus num dynamically. */
472 bbp->master->bus_num = -1;
474 /* the spi->mode bits understood by this driver: */
475 bbp->master->mode_bits =
476 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
478 /* this many pins in all GPIO controllers */
479 bbp->master->num_chipselect = num_gpios;
481 /* Get the clock for the OPB */
482 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
484 dev_err(dev, "OPB: cannot find node\n");
488 /* Get the clock (Hz) for the OPB */
489 clk = of_get_property(opbnp, "clock-frequency", NULL);
491 dev_err(dev, "OPB: no clock-frequency property set\n");
500 ret = of_address_to_resource(np, 0, &resource);
502 dev_err(dev, "error while parsing device node resource\n");
505 hw->mapbase = resource.start;
506 hw->mapsize = resource.end - resource.start + 1;
509 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
510 dev_err(dev, "too small to map registers\n");
516 hw->irqnum = irq_of_parse_and_map(np, 0);
517 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
518 IRQF_DISABLED, "spi_ppc4xx_of", (void *)hw);
520 dev_err(dev, "unable to allocate interrupt\n");
524 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
525 dev_err(dev, "resource unavailable\n");
527 goto request_mem_error;
530 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
533 dev_err(dev, "unable to memory map registers\n");
538 spi_ppc4xx_enable(hw);
540 /* Finally register our spi controller */
542 ret = spi_bitbang_start(bbp);
544 dev_err(dev, "failed to register SPI master\n");
548 dev_info(dev, "driver initialized\n");
555 release_mem_region(hw->mapbase, hw->mapsize);
557 free_irq(hw->irqnum, hw);
561 dev_set_drvdata(dev, NULL);
562 spi_master_put(master);
564 dev_err(dev, "initialization failed\n");
568 static int __exit spi_ppc4xx_of_remove(struct platform_device *op)
570 struct spi_master *master = dev_get_drvdata(&op->dev);
571 struct ppc4xx_spi *hw = spi_master_get_devdata(master);
573 spi_bitbang_stop(&hw->bitbang);
574 dev_set_drvdata(&op->dev, NULL);
575 release_mem_region(hw->mapbase, hw->mapsize);
576 free_irq(hw->irqnum, hw);
582 static const struct of_device_id spi_ppc4xx_of_match[] = {
583 { .compatible = "ibm,ppc4xx-spi", },
587 MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
589 static struct of_platform_driver spi_ppc4xx_of_driver = {
590 .probe = spi_ppc4xx_of_probe,
591 .remove = __exit_p(spi_ppc4xx_of_remove),
594 .owner = THIS_MODULE,
595 .of_match_table = spi_ppc4xx_of_match,
599 static int __init spi_ppc4xx_init(void)
601 return of_register_platform_driver(&spi_ppc4xx_of_driver);
603 module_init(spi_ppc4xx_init);
605 static void __exit spi_ppc4xx_exit(void)
607 of_unregister_platform_driver(&spi_ppc4xx_of_driver);
609 module_exit(spi_ppc4xx_exit);
611 MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
612 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
613 MODULE_LICENSE("GPL");