drivers/spi/spi-zynqmp-gqspi.c

   1 /*
   2  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
   3  * (master mode only)
   4  *
   5  * Copyright (C) 2009 - 2015 Xilinx, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_address.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27
  28 /* Generic QSPI register offsets */
  29 #define GQSPI_CONFIG_OFST               0x00000100
  30 #define GQSPI_ISR_OFST                  0x00000104
  31 #define GQSPI_IDR_OFST                  0x0000010C
  32 #define GQSPI_IER_OFST                  0x00000108
  33 #define GQSPI_IMASK_OFST                0x00000110
  34 #define GQSPI_EN_OFST                   0x00000114
  35 #define GQSPI_TXD_OFST                  0x0000011C
  36 #define GQSPI_RXD_OFST                  0x00000120
  37 #define GQSPI_TX_THRESHOLD_OFST         0x00000128
  38 #define GQSPI_RX_THRESHOLD_OFST         0x0000012C
  39 #define GQSPI_LPBK_DLY_ADJ_OFST         0x00000138
  40 #define GQSPI_GEN_FIFO_OFST             0x00000140
  41 #define GQSPI_SEL_OFST                  0x00000144
  42 #define GQSPI_GF_THRESHOLD_OFST         0x00000150
  43 #define GQSPI_FIFO_CTRL_OFST            0x0000014C
  44 #define GQSPI_QSPIDMA_DST_CTRL_OFST     0x0000080C
  45 #define GQSPI_QSPIDMA_DST_SIZE_OFST     0x00000804
  46 #define GQSPI_QSPIDMA_DST_STS_OFST      0x00000808
  47 #define GQSPI_QSPIDMA_DST_I_STS_OFST    0x00000814
  48 #define GQSPI_QSPIDMA_DST_I_EN_OFST     0x00000818
  49 #define GQSPI_QSPIDMA_DST_I_DIS_OFST    0x0000081C
  50 #define GQSPI_QSPIDMA_DST_I_MASK_OFST   0x00000820
  51 #define GQSPI_QSPIDMA_DST_ADDR_OFST     0x00000800
  52 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
  53
  54 /* GQSPI register bit masks */
  55 #define GQSPI_SEL_MASK                          0x00000001
  56 #define GQSPI_EN_MASK                           0x00000001
  57 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK        0x00000020
  58 #define GQSPI_ISR_WR_TO_CLR_MASK                0x00000002
  59 #define GQSPI_IDR_ALL_MASK                      0x00000FBE
  60 #define GQSPI_CFG_MODE_EN_MASK                  0xC0000000
  61 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK      0x20000000
  62 #define GQSPI_CFG_ENDIAN_MASK                   0x04000000
  63 #define GQSPI_CFG_EN_POLL_TO_MASK               0x00100000
  64 #define GQSPI_CFG_WP_HOLD_MASK                  0x00080000
  65 #define GQSPI_CFG_BAUD_RATE_DIV_MASK            0x00000038
  66 #define GQSPI_CFG_CLK_PHA_MASK                  0x00000004
  67 #define GQSPI_CFG_CLK_POL_MASK                  0x00000002
  68 #define GQSPI_CFG_START_GEN_FIFO_MASK           0x10000000
  69 #define GQSPI_GENFIFO_IMM_DATA_MASK             0x000000FF
  70 #define GQSPI_GENFIFO_DATA_XFER                 0x00000100
  71 #define GQSPI_GENFIFO_EXP                       0x00000200
  72 #define GQSPI_GENFIFO_MODE_SPI                  0x00000400
  73 #define GQSPI_GENFIFO_MODE_DUALSPI              0x00000800
  74 #define GQSPI_GENFIFO_MODE_QUADSPI              0x00000C00
  75 #define GQSPI_GENFIFO_MODE_MASK                 0x00000C00
  76 #define GQSPI_GENFIFO_CS_LOWER                  0x00001000
  77 #define GQSPI_GENFIFO_CS_UPPER                  0x00002000
  78 #define GQSPI_GENFIFO_BUS_LOWER                 0x00004000
  79 #define GQSPI_GENFIFO_BUS_UPPER                 0x00008000
  80 #define GQSPI_GENFIFO_BUS_BOTH                  0x0000C000
  81 #define GQSPI_GENFIFO_BUS_MASK                  0x0000C000
  82 #define GQSPI_GENFIFO_TX                        0x00010000
  83 #define GQSPI_GENFIFO_RX                        0x00020000
  84 #define GQSPI_GENFIFO_STRIPE                    0x00040000
  85 #define GQSPI_GENFIFO_POLL                      0x00080000
  86 #define GQSPI_GENFIFO_EXP_START                 0x00000100
  87 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK        0x00000004
  88 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK        0x00000002
  89 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK       0x00000001
  90 #define GQSPI_ISR_RXEMPTY_MASK                  0x00000800
  91 #define GQSPI_ISR_GENFIFOFULL_MASK              0x00000400
  92 #define GQSPI_ISR_GENFIFONOT_FULL_MASK          0x00000200
  93 #define GQSPI_ISR_TXEMPTY_MASK                  0x00000100
  94 #define GQSPI_ISR_GENFIFOEMPTY_MASK             0x00000080
  95 #define GQSPI_ISR_RXFULL_MASK                   0x00000020
  96 #define GQSPI_ISR_RXNEMPTY_MASK                 0x00000010
  97 #define GQSPI_ISR_TXFULL_MASK                   0x00000008
  98 #define GQSPI_ISR_TXNOT_FULL_MASK               0x00000004
  99 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK         0x00000002
 100 #define GQSPI_IER_TXNOT_FULL_MASK               0x00000004
 101 #define GQSPI_IER_RXEMPTY_MASK                  0x00000800
 102 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK         0x00000002
 103 #define GQSPI_IER_RXNEMPTY_MASK                 0x00000010
 104 #define GQSPI_IER_GENFIFOEMPTY_MASK             0x00000080
 105 #define GQSPI_IER_TXEMPTY_MASK                  0x00000100
 106 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK         0x000000FE
 107 #define GQSPI_QSPIDMA_DST_STS_WTC               0x0000E000
 108 #define GQSPI_CFG_MODE_EN_DMA_MASK              0x80000000
 109 #define GQSPI_ISR_IDR_MASK                      0x00000994
 110 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK        0x00000002
 111 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK       0x00000002
 112 #define GQSPI_IRQ_MASK                          0x00000980
 113
 114 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT           3
 115 #define GQSPI_GENFIFO_CS_SETUP                  0x4
 116 #define GQSPI_GENFIFO_CS_HOLD                   0x3
 117 #define GQSPI_TXD_DEPTH                         64
 118 #define GQSPI_RX_FIFO_THRESHOLD                 32
 119 #define GQSPI_RX_FIFO_FILL      (GQSPI_RX_FIFO_THRESHOLD * 4)
 120 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL       32
 121 #define GQSPI_TX_FIFO_FILL      (GQSPI_TXD_DEPTH -\
 122                                 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
 123 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL      0X10
 124 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL        0x803FFA00
 125 #define GQSPI_SELECT_FLASH_CS_LOWER             0x1
 126 #define GQSPI_SELECT_FLASH_CS_UPPER             0x2
 127 #define GQSPI_SELECT_FLASH_CS_BOTH              0x3
 128 #define GQSPI_SELECT_FLASH_BUS_LOWER            0x1
 129 #define GQSPI_SELECT_FLASH_BUS_UPPER            0x2
 130 #define GQSPI_SELECT_FLASH_BUS_BOTH             0x3
 131 #define GQSPI_BAUD_DIV_MAX      7       /* Baud rate divisor maximum */
 132 #define GQSPI_BAUD_DIV_SHIFT    2       /* Baud rate divisor shift */
 133 #define GQSPI_SELECT_MODE_SPI           0x1
 134 #define GQSPI_SELECT_MODE_DUALSPI       0x2
 135 #define GQSPI_SELECT_MODE_QUADSPI       0x4
 136 #define GQSPI_DMA_UNALIGN               0x3
 137 #define GQSPI_DEFAULT_NUM_CS    1       /* Default number of chip selects */
 138
 139 #define SPI_AUTOSUSPEND_TIMEOUT         3000
 140 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
 141 static const struct zynqmp_eemi_ops *eemi_ops;
 142
 143 /**
 144  * struct zynqmp_qspi - Defines qspi driver instance
 145  * @regs:               Virtual address of the QSPI controller registers
 146  * @refclk:             Pointer to the peripheral clock
 147  * @pclk:               Pointer to the APB clock
 148  * @irq:                IRQ number
 149  * @dev:                Pointer to struct device
 150  * @txbuf:              Pointer to the TX buffer
 151  * @rxbuf:              Pointer to the RX buffer
 152  * @bytes_to_transfer:  Number of bytes left to transfer
 153  * @bytes_to_receive:   Number of bytes left to receive
 154  * @genfifocs:          Used for chip select
 155  * @genfifobus:         Used to select the upper or lower bus
 156  * @dma_rx_bytes:       Remaining bytes to receive by DMA mode
 157  * @dma_addr:           DMA address after mapping the kernel buffer
 158  * @genfifoentry:       Used for storing the genfifoentry instruction.
 159  * @mode:               Defines the mode in which QSPI is operating
 160  */
 161 struct zynqmp_qspi {
 162         void __iomem *regs;
 163         struct clk *refclk;
 164         struct clk *pclk;
 165         int irq;
 166         struct device *dev;
 167         const void *txbuf;
 168         void *rxbuf;
 169         int bytes_to_transfer;
 170         int bytes_to_receive;
 171         u32 genfifocs;
 172         u32 genfifobus;
 173         u32 dma_rx_bytes;
 174         dma_addr_t dma_addr;
 175         u32 genfifoentry;
 176         enum mode_type mode;
 177 };
 178
 179 /**
 180  * zynqmp_gqspi_read:   For GQSPI controller read operation
 181  * @xqspi:      Pointer to the zynqmp_qspi structure
 182  * @offset:     Offset from where to read
 183  */
 184 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
 185 {
 186         return readl_relaxed(xqspi->regs + offset);
 187 }
 188
 189 /**
 190  * zynqmp_gqspi_write:  For GQSPI controller write operation
 191  * @xqspi:      Pointer to the zynqmp_qspi structure
 192  * @offset:     Offset where to write
 193  * @val:        Value to be written
 194  */
 195 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
 196                                       u32 val)
 197 {
 198         writel_relaxed(val, (xqspi->regs + offset));
 199 }
 200
 201 /**
 202  * zynqmp_gqspi_selectslave:    For selection of slave device
 203  * @instanceptr:        Pointer to the zynqmp_qspi structure
 204  * @flashcs:    For chip select
 205  * @flashbus:   To check which bus is selected- upper or lower
 206  */
 207 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
 208                                      u8 slavecs, u8 slavebus)
 209 {
 210         /*
 211          * Bus and CS lines selected here will be updated in the instance and
 212          * used for subsequent GENFIFO entries during transfer.
 213          */
 214
 215         /* Choose slave select line */
 216         switch (slavecs) {
 217         case GQSPI_SELECT_FLASH_CS_BOTH:
 218                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
 219                         GQSPI_GENFIFO_CS_UPPER;
 220                 break;
 221         case GQSPI_SELECT_FLASH_CS_UPPER:
 222                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
 223                 break;
 224         case GQSPI_SELECT_FLASH_CS_LOWER:
 225                 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 226                 break;
 227         default:
 228                 dev_warn(instanceptr->dev, "Invalid slave select\n");
 229         }
 230
 231         /* Choose the bus */
 232         switch (slavebus) {
 233         case GQSPI_SELECT_FLASH_BUS_BOTH:
 234                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
 235                         GQSPI_GENFIFO_BUS_UPPER;
 236                 break;
 237         case GQSPI_SELECT_FLASH_BUS_UPPER:
 238                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
 239                 break;
 240         case GQSPI_SELECT_FLASH_BUS_LOWER:
 241                 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 242                 break;
 243         default:
 244                 dev_warn(instanceptr->dev, "Invalid slave bus\n");
 245         }
 246 }
 247
 248 /**
 249  * zynqmp_qspi_init_hw: Initialize the hardware
 250  * @xqspi:      Pointer to the zynqmp_qspi structure
 251  *
 252  * The default settings of the QSPI controller's configurable parameters on
 253  * reset are
 254  *      - Master mode
 255  *      - TX threshold set to 1
 256  *      - RX threshold set to 1
 257  *      - Flash memory interface mode enabled
 258  * This function performs the following actions
 259  *      - Disable and clear all the interrupts
 260  *      - Enable manual slave select
 261  *      - Enable manual start
 262  *      - Deselect all the chip select lines
 263  *      - Set the little endian mode of TX FIFO and
 264  *      - Enable the QSPI controller
 265  */
 266 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 267 {
 268         u32 config_reg;
 269
 270         /* Select the GQSPI mode */
 271         zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
 272         /* Clear and disable interrupts */
 273         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
 274                            zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
 275                            GQSPI_ISR_WR_TO_CLR_MASK);
 276         /* Clear the DMA STS */
 277         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 278                            zynqmp_gqspi_read(xqspi,
 279                                              GQSPI_QSPIDMA_DST_I_STS_OFST));
 280         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
 281                            zynqmp_gqspi_read(xqspi,
 282                                              GQSPI_QSPIDMA_DST_STS_OFST) |
 283                                              GQSPI_QSPIDMA_DST_STS_WTC);
 284         zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
 285         zynqmp_gqspi_write(xqspi,
 286                            GQSPI_QSPIDMA_DST_I_DIS_OFST,
 287                            GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
 288         /* Disable the GQSPI */
 289         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 290         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 291         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 292         /* Manual start */
 293         config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
 294         /* Little endian by default */
 295         config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
 296         /* Disable poll time out */
 297         config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
 298         /* Set hold bit */
 299         config_reg |= GQSPI_CFG_WP_HOLD_MASK;
 300         /* Clear pre-scalar by default */
 301         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 302         /* CPHA 0 */
 303         config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
 304         /* CPOL 0 */
 305         config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
 306         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 307
 308         /* Clear the TX and RX FIFO */
 309         zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
 310                            GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
 311                            GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
 312                            GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
 313         /* Set by default to allow for high frequencies */
 314         zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
 315                            zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
 316                            GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 317         /* Reset thresholds */
 318         zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
 319                            GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
 320         zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
 321                            GQSPI_RX_FIFO_THRESHOLD);
 322         zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
 323                            GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
 324         zynqmp_gqspi_selectslave(xqspi,
 325                                  GQSPI_SELECT_FLASH_CS_LOWER,
 326                                  GQSPI_SELECT_FLASH_BUS_LOWER);
 327         /* Initialize DMA */
 328         zynqmp_gqspi_write(xqspi,
 329                         GQSPI_QSPIDMA_DST_CTRL_OFST,
 330                         GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
 331
 332         /* Enable the GQSPI */
 333         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 334 }
 335
 336 /**
 337  * zynqmp_qspi_copy_read_data:  Copy data to RX buffer
 338  * @xqspi:      Pointer to the zynqmp_qspi structure
 339  * @data:       The variable where data is stored
 340  * @size:       Number of bytes to be copied from data to RX buffer
 341  */
 342 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
 343                                        ulong data, u8 size)
 344 {
 345         memcpy(xqspi->rxbuf, &data, size);
 346         xqspi->rxbuf += size;
 347         xqspi->bytes_to_receive -= size;
 348 }
 349
 350 /**
 351  * zynqmp_prepare_transfer_hardware:    Prepares hardware for transfer.
 352  * @master:     Pointer to the spi_master structure which provides
 353  *              information about the controller.
 354  *
 355  * This function enables SPI master controller.
 356  *
 357  * Return:      0 on success; error value otherwise
 358  */
 359 static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
 360 {
 361         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 362
 363         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 364         return 0;
 365 }
 366
 367 /**
 368  * zynqmp_unprepare_transfer_hardware:  Relaxes hardware after transfer
 369  * @master:     Pointer to the spi_master structure which provides
 370  *              information about the controller.
 371  *
 372  * This function disables the SPI master controller.
 373  *
 374  * Return:      Always 0
 375  */
 376 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
 377 {
 378         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 379
 380         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 381         return 0;
 382 }
 383
 384 /**
 385  * zynqmp_qspi_chipselect:      Select or deselect the chip select line
 386  * @qspi:       Pointer to the spi_device structure
 387  * @is_high:    Select(0) or deselect (1) the chip select line
 388  */
 389 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
 390 {
 391         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 392         ulong timeout;
 393         u32 genfifoentry = 0x0, statusreg;
 394
 395         genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 396         genfifoentry |= xqspi->genfifobus;
 397
 398         if (!is_high) {
 399                 genfifoentry |= xqspi->genfifocs;
 400                 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
 401         } else {
 402                 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
 403         }
 404
 405         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 406
 407         /* Dummy generic FIFO entry */
 408         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 409
 410         /* Manually start the generic FIFO command */
 411         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 412                         zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 413                         GQSPI_CFG_START_GEN_FIFO_MASK);
 414
 415         timeout = jiffies + msecs_to_jiffies(1000);
 416
 417         /* Wait until the generic FIFO command is empty */
 418         do {
 419                 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 420
 421                 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
 422                         (statusreg & GQSPI_ISR_TXEMPTY_MASK))
 423                         break;
 424                 else
 425                         cpu_relax();
 426         } while (!time_after_eq(jiffies, timeout));
 427
 428         if (time_after_eq(jiffies, timeout))
 429                 dev_err(xqspi->dev, "Chip select timed out\n");
 430 }
 431
 432 /**
 433  * zynqmp_qspi_setup_transfer:  Configure QSPI controller for specified
 434  *                              transfer
 435  * @qspi:       Pointer to the spi_device structure
 436  * @transfer:   Pointer to the spi_transfer structure which provides
 437  *              information about next transfer setup parameters
 438  *
 439  * Sets the operational mode of QSPI controller for the next QSPI transfer and
 440  * sets the requested clock frequency.
 441  *
 442  * Return:      Always 0
 443  *
 444  * Note:
 445  *      If the requested frequency is not an exact match with what can be
 446  *      obtained using the pre-scalar value, the driver sets the clock
 447  *      frequency which is lower than the requested frequency (maximum lower)
 448  *      for the transfer.
 449  *
 450  *      If the requested frequency is higher or lower than that is supported
 451  *      by the QSPI controller the driver will set the highest or lowest
 452  *      frequency supported by controller.
 453  */
 454 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
 455                                       struct spi_transfer *transfer)
 456 {
 457         struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
 458         ulong clk_rate;
 459         u32 config_reg, req_hz, baud_rate_val = 0;
 460
 461         if (transfer)
 462                 req_hz = transfer->speed_hz;
 463         else
 464                 req_hz = qspi->max_speed_hz;
 465
 466         /* Set the clock frequency */
 467         /* If req_hz == 0, default to lowest speed */
 468         clk_rate = clk_get_rate(xqspi->refclk);
 469
 470         while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
 471                (clk_rate /
 472                 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
 473                 baud_rate_val++;
 474
 475         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 476
 477         /* Set the QSPI clock phase and clock polarity */
 478         config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
 479
 480         if (qspi->mode & SPI_CPHA)
 481                 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
 482         if (qspi->mode & SPI_CPOL)
 483                 config_reg |= GQSPI_CFG_CLK_POL_MASK;
 484
 485         config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 486         config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
 487         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 488         return 0;
 489 }
 490
 491 /**
 492  * zynqmp_qspi_setup:   Configure the QSPI controller
 493  * @qspi:       Pointer to the spi_device structure
 494  *
 495  * Sets the operational mode of QSPI controller for the next QSPI transfer,
 496  * baud rate and divisor value to setup the requested qspi clock.
 497  *
 498  * Return:      0 on success; error value otherwise.
 499  */
 500 static int zynqmp_qspi_setup(struct spi_device *qspi)
 501 {
 502         if (qspi->master->busy)
 503                 return -EBUSY;
 504         return 0;
 505 }
 506
 507 /**
 508  * zynqmp_qspi_filltxfifo:      Fills the TX FIFO as long as there is room in
 509  *                              the FIFO or the bytes required to be
 510  *                              transmitted.
 511  * @xqspi:      Pointer to the zynqmp_qspi structure
 512  * @size:       Number of bytes to be copied from TX buffer to TX FIFO
 513  */
 514 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
 515 {
 516         u32 count = 0, intermediate;
 517
 518         while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
 519                 memcpy(&intermediate, xqspi->txbuf, 4);
 520                 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
 521
 522                 if (xqspi->bytes_to_transfer >= 4) {
 523                         xqspi->txbuf += 4;
 524                         xqspi->bytes_to_transfer -= 4;
 525                 } else {
 526                         xqspi->txbuf += xqspi->bytes_to_transfer;
 527                         xqspi->bytes_to_transfer = 0;
 528                 }
 529                 count++;
 530         }
 531 }
 532
 533 /**
 534  * zynqmp_qspi_readrxfifo:      Fills the RX FIFO as long as there is room in
 535  *                              the FIFO.
 536  * @xqspi:      Pointer to the zynqmp_qspi structure
 537  * @size:       Number of bytes to be copied from RX buffer to RX FIFO
 538  */
 539 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
 540 {
 541         ulong data;
 542         int count = 0;
 543
 544         while ((count < size) && (xqspi->bytes_to_receive > 0)) {
 545                 if (xqspi->bytes_to_receive >= 4) {
 546                         (*(u32 *) xqspi->rxbuf) =
 547                         zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 548                         xqspi->rxbuf += 4;
 549                         xqspi->bytes_to_receive -= 4;
 550                         count += 4;
 551                 } else {
 552                         data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 553                         count += xqspi->bytes_to_receive;
 554                         zynqmp_qspi_copy_read_data(xqspi, data,
 555                                                    xqspi->bytes_to_receive);
 556                         xqspi->bytes_to_receive = 0;
 557                 }
 558         }
 559 }
 560
 561 /**
 562  * zynqmp_process_dma_irq:      Handler for DMA done interrupt of QSPI
 563  *                              controller
 564  * @xqspi:      zynqmp_qspi instance pointer
 565  *
 566  * This function handles DMA interrupt only.
 567  */
 568 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
 569 {
 570         u32 config_reg, genfifoentry;
 571
 572         dma_unmap_single(xqspi->dev, xqspi->dma_addr,
 573                                 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
 574         xqspi->rxbuf += xqspi->dma_rx_bytes;
 575         xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
 576         xqspi->dma_rx_bytes = 0;
 577
 578         /* Disabling the DMA interrupts */
 579         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
 580                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 581
 582         if (xqspi->bytes_to_receive > 0) {
 583                 /* Switch to IO mode,for remaining bytes to receive */
 584                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 585                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 586                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 587
 588                 /* Initiate the transfer of remaining bytes */
 589                 genfifoentry = xqspi->genfifoentry;
 590                 genfifoentry |= xqspi->bytes_to_receive;
 591                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 592
 593                 /* Dummy generic FIFO entry */
 594                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 595
 596                 /* Manual start */
 597                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 598                         (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 599                         GQSPI_CFG_START_GEN_FIFO_MASK));
 600
 601                 /* Enable the RX interrupts for IO mode */
 602                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 603                                 GQSPI_IER_GENFIFOEMPTY_MASK |
 604                                 GQSPI_IER_RXNEMPTY_MASK |
 605                                 GQSPI_IER_RXEMPTY_MASK);
 606         }
 607 }
 608
 609 /**
 610  * zynqmp_qspi_irq:     Interrupt service routine of the QSPI controller
 611  * @irq:        IRQ number
 612  * @dev_id:     Pointer to the xqspi structure
 613  *
 614  * This function handles TX empty only.
 615  * On TX empty interrupt this function reads the received data from RX FIFO
 616  * and fills the TX FIFO if there is any data remaining to be transferred.
 617  *
 618  * Return:      IRQ_HANDLED when interrupt is handled
 619  *              IRQ_NONE otherwise.
 620  */
 621 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
 622 {
 623         struct spi_master *master = dev_id;
 624         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 625         int ret = IRQ_NONE;
 626         u32 status, mask, dma_status = 0;
 627
 628         status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 629         zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
 630         mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
 631
 632         /* Read and clear DMA status */
 633         if (xqspi->mode == GQSPI_MODE_DMA) {
 634                 dma_status =
 635                         zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
 636                 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 637                                                                 dma_status);
 638         }
 639
 640         if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
 641                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
 642                 ret = IRQ_HANDLED;
 643         }
 644
 645         if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
 646                 zynqmp_process_dma_irq(xqspi);
 647                 ret = IRQ_HANDLED;
 648         } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
 649                         (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
 650                 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
 651                 ret = IRQ_HANDLED;
 652         }
 653
 654         if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
 655                         && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
 656                 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
 657                 spi_finalize_current_transfer(master);
 658                 ret = IRQ_HANDLED;
 659         }
 660         return ret;
 661 }
 662
 663 /**
 664  * zynqmp_qspi_selectspimode:   Selects SPI mode - x1 or x2 or x4.
 665  * @xqspi:      xqspi is a pointer to the GQSPI instance
 666  * @spimode:    spimode - SPI or DUAL or QUAD.
 667  * Return:      Mask to set desired SPI mode in GENFIFO entry.
 668  */
 669 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
 670                                                 u8 spimode)
 671 {
 672         u32 mask = 0;
 673
 674         switch (spimode) {
 675         case GQSPI_SELECT_MODE_DUALSPI:
 676                 mask = GQSPI_GENFIFO_MODE_DUALSPI;
 677                 break;
 678         case GQSPI_SELECT_MODE_QUADSPI:
 679                 mask = GQSPI_GENFIFO_MODE_QUADSPI;
 680                 break;
 681         case GQSPI_SELECT_MODE_SPI:
 682                 mask = GQSPI_GENFIFO_MODE_SPI;
 683                 break;
 684         default:
 685                 dev_warn(xqspi->dev, "Invalid SPI mode\n");
 686         }
 687
 688         return mask;
 689 }
 690
 691 /**
 692  * zynq_qspi_setuprxdma:        This function sets up the RX DMA operation
 693  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 694  */
 695 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
 696 {
 697         u32 rx_bytes, rx_rem, config_reg;
 698         dma_addr_t addr;
 699         u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
 700
 701         if ((xqspi->bytes_to_receive < 8) ||
 702                 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
 703                 /* Setting to IO mode */
 704                 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 705                 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 706                 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 707                 xqspi->mode = GQSPI_MODE_IO;
 708                 xqspi->dma_rx_bytes = 0;
 709                 return;
 710         }
 711
 712         rx_rem = xqspi->bytes_to_receive % 4;
 713         rx_bytes = (xqspi->bytes_to_receive - rx_rem);
 714
 715         addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
 716                                                 rx_bytes, DMA_FROM_DEVICE);
 717         if (dma_mapping_error(xqspi->dev, addr))
 718                 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
 719
 720         xqspi->dma_rx_bytes = rx_bytes;
 721         xqspi->dma_addr = addr;
 722         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
 723                                 (u32)(addr & 0xffffffff));
 724         addr = ((addr >> 16) >> 16);
 725         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
 726                                 ((u32)addr) & 0xfff);
 727
 728         /* Enabling the DMA mode */
 729         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 730         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 731         config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
 732         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 733
 734         /* Switch to DMA mode */
 735         xqspi->mode = GQSPI_MODE_DMA;
 736
 737         /* Write the number of bytes to transfer */
 738         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
 739 }
 740
 741 /**
 742  * zynqmp_qspi_txrxsetup:       This function checks the TX/RX buffers in
 743  *                              the transfer and sets up the GENFIFO entries,
 744  *                              TX FIFO as required.
 745  * @xqspi:      xqspi is a pointer to the GQSPI instance.
 746  * @transfer:   It is a pointer to the structure containing transfer data.
 747  * @genfifoentry:       genfifoentry is pointer to the variable in which
 748  *                      GENFIFO mask is returned to calling function
 749  */
 750 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
 751                                   struct spi_transfer *transfer,
 752                                   u32 *genfifoentry)
 753 {
 754         u32 config_reg;
 755
 756         /* Transmit */
 757         if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
 758                 /* Setup data to be TXed */
 759                 *genfifoentry &= ~GQSPI_GENFIFO_RX;
 760                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 761                 *genfifoentry |= GQSPI_GENFIFO_TX;
 762                 *genfifoentry |=
 763                         zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
 764                 xqspi->bytes_to_transfer = transfer->len;
 765                 if (xqspi->mode == GQSPI_MODE_DMA) {
 766                         config_reg = zynqmp_gqspi_read(xqspi,
 767                                                         GQSPI_CONFIG_OFST);
 768                         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 769                         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 770                                                                 config_reg);
 771                         xqspi->mode = GQSPI_MODE_IO;
 772                 }
 773                 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
 774                 /* Discard RX data */
 775                 xqspi->bytes_to_receive = 0;
 776         } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
 777                 /* Receive */
 778
 779                 /* TX auto fill */
 780                 *genfifoentry &= ~GQSPI_GENFIFO_TX;
 781                 /* Setup RX */
 782                 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 783                 *genfifoentry |= GQSPI_GENFIFO_RX;
 784                 *genfifoentry |=
 785                         zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
 786                 xqspi->bytes_to_transfer = 0;
 787                 xqspi->bytes_to_receive = transfer->len;
 788                 zynq_qspi_setuprxdma(xqspi);
 789         }
 790 }
 791
 792 /**
 793  * zynqmp_qspi_start_transfer:  Initiates the QSPI transfer
 794  * @master:     Pointer to the spi_master structure which provides
 795  *              information about the controller.
 796  * @qspi:       Pointer to the spi_device structure
 797  * @transfer:   Pointer to the spi_transfer structure which provide information
 798  *              about next transfer parameters
 799  *
 800  * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 801  * transfer to be completed.
 802  *
 803  * Return:      Number of bytes transferred in the last transfer
 804  */
 805 static int zynqmp_qspi_start_transfer(struct spi_master *master,
 806                                       struct spi_device *qspi,
 807                                       struct spi_transfer *transfer)
 808 {
 809         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 810         u32 genfifoentry = 0x0, transfer_len;
 811
 812         xqspi->txbuf = transfer->tx_buf;
 813         xqspi->rxbuf = transfer->rx_buf;
 814
 815         zynqmp_qspi_setup_transfer(qspi, transfer);
 816
 817         genfifoentry |= xqspi->genfifocs;
 818         genfifoentry |= xqspi->genfifobus;
 819
 820         zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
 821
 822         if (xqspi->mode == GQSPI_MODE_DMA)
 823                 transfer_len = xqspi->dma_rx_bytes;
 824         else
 825                 transfer_len = transfer->len;
 826
 827         xqspi->genfifoentry = genfifoentry;
 828         if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
 829                 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 830                 genfifoentry |= transfer_len;
 831                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 832         } else {
 833                 int tempcount = transfer_len;
 834                 u32 exponent = 8;       /* 2^8 = 256 */
 835                 u8 imm_data = tempcount & 0xFF;
 836
 837                 tempcount &= ~(tempcount & 0xFF);
 838                 /* Immediate entry */
 839                 if (tempcount != 0) {
 840                         /* Exponent entries */
 841                         genfifoentry |= GQSPI_GENFIFO_EXP;
 842                         while (tempcount != 0) {
 843                                 if (tempcount & GQSPI_GENFIFO_EXP_START) {
 844                                         genfifoentry &=
 845                                             ~GQSPI_GENFIFO_IMM_DATA_MASK;
 846                                         genfifoentry |= exponent;
 847                                         zynqmp_gqspi_write(xqspi,
 848                                                            GQSPI_GEN_FIFO_OFST,
 849                                                            genfifoentry);
 850                                 }
 851                                 tempcount = tempcount >> 1;
 852                                 exponent++;
 853                         }
 854                 }
 855                 if (imm_data != 0) {
 856                         genfifoentry &= ~GQSPI_GENFIFO_EXP;
 857                         genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
 858                         genfifoentry |= (u8) (imm_data & 0xFF);
 859                         zynqmp_gqspi_write(xqspi,
 860                                            GQSPI_GEN_FIFO_OFST, genfifoentry);
 861                 }
 862         }
 863
 864         if ((xqspi->mode == GQSPI_MODE_IO) &&
 865                         (xqspi->rxbuf != NULL)) {
 866                 /* Dummy generic FIFO entry */
 867                 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 868         }
 869
 870         /* Since we are using manual mode */
 871         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 872                            zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 873                            GQSPI_CFG_START_GEN_FIFO_MASK);
 874
 875         if (xqspi->txbuf != NULL)
 876                 /* Enable interrupts for TX */
 877                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 878                                    GQSPI_IER_TXEMPTY_MASK |
 879                                         GQSPI_IER_GENFIFOEMPTY_MASK |
 880                                         GQSPI_IER_TXNOT_FULL_MASK);
 881
 882         if (xqspi->rxbuf != NULL) {
 883                 /* Enable interrupts for RX */
 884                 if (xqspi->mode == GQSPI_MODE_DMA) {
 885                         /* Enable DMA interrupts */
 886                         zynqmp_gqspi_write(xqspi,
 887                                         GQSPI_QSPIDMA_DST_I_EN_OFST,
 888                                         GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 889                 } else {
 890                         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 891                                         GQSPI_IER_GENFIFOEMPTY_MASK |
 892                                         GQSPI_IER_RXNEMPTY_MASK |
 893                                         GQSPI_IER_RXEMPTY_MASK);
 894                 }
 895         }
 896
 897         return transfer->len;
 898 }
 899
 900 /**
 901  * zynqmp_qspi_suspend: Suspend method for the QSPI driver
 902  * @_dev:       Address of the platform_device structure
 903  *
 904  * This function stops the QSPI driver queue and disables the QSPI controller
 905  *
 906  * Return:      Always 0
 907  */
 908 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
 909 {
 910         struct spi_master *master = dev_get_drvdata(dev);
 911
 912         spi_master_suspend(master);
 913
 914         zynqmp_unprepare_transfer_hardware(master);
 915
 916         return 0;
 917 }
 918
 919 /**
 920  * zynqmp_qspi_resume:  Resume method for the QSPI driver
 921  * @dev:        Address of the platform_device structure
 922  *
 923  * The function starts the QSPI driver queue and initializes the QSPI
 924  * controller
 925  *
 926  * Return:      0 on success; error value otherwise
 927  */
 928 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
 929 {
 930         struct spi_master *master = dev_get_drvdata(dev);
 931         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 932         int ret = 0;
 933
 934         ret = clk_enable(xqspi->pclk);
 935         if (ret) {
 936                 dev_err(dev, "Cannot enable APB clock.\n");
 937                 return ret;
 938         }
 939
 940         ret = clk_enable(xqspi->refclk);
 941         if (ret) {
 942                 dev_err(dev, "Cannot enable device clock.\n");
 943                 clk_disable(xqspi->pclk);
 944                 return ret;
 945         }
 946
 947         spi_master_resume(master);
 948
 949         clk_disable(xqspi->refclk);
 950         clk_disable(xqspi->pclk);
 951         return 0;
 952 }
 953
 954 /**
 955  * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
 956  * @dev:        Address of the platform_device structure
 957  *
 958  * This function disables the clocks
 959  *
 960  * Return:      Always 0
 961  */
 962 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
 963 {
 964         struct spi_master *master = dev_get_drvdata(dev);
 965         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 966
 967         clk_disable(xqspi->refclk);
 968         clk_disable(xqspi->pclk);
 969
 970         return 0;
 971 }
 972
 973 /**
 974  * zynqmp_runtime_resume - Runtime resume method for the SPI driver
 975  * @dev:        Address of the platform_device structure
 976  *
 977  * This function enables the clocks
 978  *
 979  * Return:      0 on success and error value on error
 980  */
 981 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
 982 {
 983         struct spi_master *master = dev_get_drvdata(dev);
 984         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
 985         int ret;
 986
 987         ret = clk_enable(xqspi->pclk);
 988         if (ret) {
 989                 dev_err(dev, "Cannot enable APB clock.\n");
 990                 return ret;
 991         }
 992
 993         ret = clk_enable(xqspi->refclk);
 994         if (ret) {
 995                 dev_err(dev, "Cannot enable device clock.\n");
 996                 clk_disable(xqspi->pclk);
 997                 return ret;
 998         }
 999
1000         return 0;
1001 }
1002
1003 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1004         SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1005                            zynqmp_runtime_resume, NULL)
1006         SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1007 };
1008
1009 /**
1010  * zynqmp_qspi_probe:   Probe method for the QSPI driver
1011  * @pdev:       Pointer to the platform_device structure
1012  *
1013  * This function initializes the driver data structures and the hardware.
1014  *
1015  * Return:      0 on success; error value otherwise
1016  */
1017 static int zynqmp_qspi_probe(struct platform_device *pdev)
1018 {
1019         int ret = 0;
1020         struct spi_master *master;
1021         struct zynqmp_qspi *xqspi;
1022         struct resource *res;
1023         struct device *dev = &pdev->dev;
1024
1025         eemi_ops = zynqmp_pm_get_eemi_ops();
1026         if (IS_ERR(eemi_ops))
1027                 return PTR_ERR(eemi_ops);
1028
1029         master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1030         if (!master)
1031                 return -ENOMEM;
1032
1033         xqspi = spi_master_get_devdata(master);
1034         master->dev.of_node = pdev->dev.of_node;
1035         platform_set_drvdata(pdev, master);
1036
1037         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1038         xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1039         if (IS_ERR(xqspi->regs)) {
1040                 ret = PTR_ERR(xqspi->regs);
1041                 goto remove_master;
1042         }
1043
1044         xqspi->dev = dev;
1045         xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1046         if (IS_ERR(xqspi->pclk)) {
1047                 dev_err(dev, "pclk clock not found.\n");
1048                 ret = PTR_ERR(xqspi->pclk);
1049                 goto remove_master;
1050         }
1051
1052         ret = clk_prepare_enable(xqspi->pclk);
1053         if (ret) {
1054                 dev_err(dev, "Unable to enable APB clock.\n");
1055                 goto remove_master;
1056         }
1057
1058         xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1059         if (IS_ERR(xqspi->refclk)) {
1060                 dev_err(dev, "ref_clk clock not found.\n");
1061                 ret = PTR_ERR(xqspi->refclk);
1062                 goto clk_dis_pclk;
1063         }
1064
1065         ret = clk_prepare_enable(xqspi->refclk);
1066         if (ret) {
1067                 dev_err(dev, "Unable to enable device clock.\n");
1068                 goto clk_dis_pclk;
1069         }
1070
1071         pm_runtime_use_autosuspend(&pdev->dev);
1072         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1073         pm_runtime_set_active(&pdev->dev);
1074         pm_runtime_enable(&pdev->dev);
1075         /* QSPI controller initializations */
1076         zynqmp_qspi_init_hw(xqspi);
1077
1078         pm_runtime_mark_last_busy(&pdev->dev);
1079         pm_runtime_put_autosuspend(&pdev->dev);
1080         xqspi->irq = platform_get_irq(pdev, 0);
1081         if (xqspi->irq <= 0) {
1082                 ret = -ENXIO;
1083                 dev_err(dev, "irq resource not found\n");
1084                 goto clk_dis_all;
1085         }
1086         ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1087                                0, pdev->name, master);
1088         if (ret != 0) {
1089                 ret = -ENXIO;
1090                 dev_err(dev, "request_irq failed\n");
1091                 goto clk_dis_all;
1092         }
1093
1094         master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1095
1096         master->setup = zynqmp_qspi_setup;
1097         master->set_cs = zynqmp_qspi_chipselect;
1098         master->transfer_one = zynqmp_qspi_start_transfer;
1099         master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1100         master->unprepare_transfer_hardware =
1101                                         zynqmp_unprepare_transfer_hardware;
1102         master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1103         master->bits_per_word_mask = SPI_BPW_MASK(8);
1104         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1105                             SPI_TX_DUAL | SPI_TX_QUAD;
1106
1107         if (master->dev.parent == NULL)
1108                 master->dev.parent = &master->dev;
1109
1110         ret = spi_register_master(master);
1111         if (ret)
1112                 goto clk_dis_all;
1113
1114         return 0;
1115
1116 clk_dis_all:
1117         pm_runtime_set_suspended(&pdev->dev);
1118         pm_runtime_disable(&pdev->dev);
1119         clk_disable_unprepare(xqspi->refclk);
1120 clk_dis_pclk:
1121         clk_disable_unprepare(xqspi->pclk);
1122 remove_master:
1123         spi_master_put(master);
1124
1125         return ret;
1126 }
1127
1128 /**
1129  * zynqmp_qspi_remove:  Remove method for the QSPI driver
1130  * @pdev:       Pointer to the platform_device structure
1131  *
1132  * This function is called if a device is physically removed from the system or
1133  * if the driver module is being unloaded. It frees all resources allocated to
1134  * the device.
1135  *
1136  * Return:      0 Always
1137  */
1138 static int zynqmp_qspi_remove(struct platform_device *pdev)
1139 {
1140         struct spi_master *master = platform_get_drvdata(pdev);
1141         struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1142
1143         zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1144         clk_disable_unprepare(xqspi->refclk);
1145         clk_disable_unprepare(xqspi->pclk);
1146         pm_runtime_set_suspended(&pdev->dev);
1147         pm_runtime_disable(&pdev->dev);
1148
1149         spi_unregister_master(master);
1150
1151         return 0;
1152 }
1153
1154 static const struct of_device_id zynqmp_qspi_of_match[] = {
1155         { .compatible = "xlnx,zynqmp-qspi-1.0", },
1156         { /* End of table */ }
1157 };
1158
1159 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1160
1161 static struct platform_driver zynqmp_qspi_driver = {
1162         .probe = zynqmp_qspi_probe,
1163         .remove = zynqmp_qspi_remove,
1164         .driver = {
1165                 .name = "zynqmp-qspi",
1166                 .of_match_table = zynqmp_qspi_of_match,
1167                 .pm = &zynqmp_qspi_dev_pm_ops,
1168         },
1169 };
1170
1171 module_platform_driver(zynqmp_qspi_driver);
1172
1173 MODULE_AUTHOR("Xilinx, Inc.");
1174 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1175 MODULE_LICENSE("GPL");