1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmapool.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/kthread.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
23 #include <linux/of_device.h>
24 #include <linux/reset.h>
25 #include <linux/spi/spi.h>
27 #define SLINK_COMMAND 0x000
28 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
29 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
30 #define SLINK_BOTH_EN (1 << 10)
31 #define SLINK_CS_SW (1 << 11)
32 #define SLINK_CS_VALUE (1 << 12)
33 #define SLINK_CS_POLARITY (1 << 13)
34 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
35 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
36 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
37 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
38 #define SLINK_IDLE_SDA_MASK (3 << 16)
39 #define SLINK_CS_POLARITY1 (1 << 20)
40 #define SLINK_CK_SDA (1 << 21)
41 #define SLINK_CS_POLARITY2 (1 << 22)
42 #define SLINK_CS_POLARITY3 (1 << 23)
43 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
44 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
45 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
46 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
47 #define SLINK_IDLE_SCLK_MASK (3 << 24)
48 #define SLINK_M_S (1 << 28)
49 #define SLINK_WAIT (1 << 29)
50 #define SLINK_GO (1 << 30)
51 #define SLINK_ENB (1 << 31)
53 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
55 #define SLINK_COMMAND2 0x004
56 #define SLINK_LSBFE (1 << 0)
57 #define SLINK_SSOE (1 << 1)
58 #define SLINK_SPIE (1 << 4)
59 #define SLINK_BIDIROE (1 << 6)
60 #define SLINK_MODFEN (1 << 7)
61 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
62 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
63 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
64 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
65 #define SLINK_FIFO_REFILLS_0 (0 << 22)
66 #define SLINK_FIFO_REFILLS_1 (1 << 22)
67 #define SLINK_FIFO_REFILLS_2 (2 << 22)
68 #define SLINK_FIFO_REFILLS_3 (3 << 22)
69 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
70 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
71 #define SLINK_SPC0 (1 << 29)
72 #define SLINK_TXEN (1 << 30)
73 #define SLINK_RXEN (1 << 31)
75 #define SLINK_STATUS 0x008
76 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
77 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
78 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
79 #define SLINK_MODF (1 << 16)
80 #define SLINK_RX_UNF (1 << 18)
81 #define SLINK_TX_OVF (1 << 19)
82 #define SLINK_TX_FULL (1 << 20)
83 #define SLINK_TX_EMPTY (1 << 21)
84 #define SLINK_RX_FULL (1 << 22)
85 #define SLINK_RX_EMPTY (1 << 23)
86 #define SLINK_TX_UNF (1 << 24)
87 #define SLINK_RX_OVF (1 << 25)
88 #define SLINK_TX_FLUSH (1 << 26)
89 #define SLINK_RX_FLUSH (1 << 27)
90 #define SLINK_SCLK (1 << 28)
91 #define SLINK_ERR (1 << 29)
92 #define SLINK_RDY (1 << 30)
93 #define SLINK_BSY (1 << 31)
94 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
95 SLINK_TX_UNF | SLINK_RX_OVF)
97 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
99 #define SLINK_MAS_DATA 0x010
100 #define SLINK_SLAVE_DATA 0x014
102 #define SLINK_DMA_CTL 0x018
103 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
104 #define SLINK_TX_TRIG_1 (0 << 16)
105 #define SLINK_TX_TRIG_4 (1 << 16)
106 #define SLINK_TX_TRIG_8 (2 << 16)
107 #define SLINK_TX_TRIG_16 (3 << 16)
108 #define SLINK_TX_TRIG_MASK (3 << 16)
109 #define SLINK_RX_TRIG_1 (0 << 18)
110 #define SLINK_RX_TRIG_4 (1 << 18)
111 #define SLINK_RX_TRIG_8 (2 << 18)
112 #define SLINK_RX_TRIG_16 (3 << 18)
113 #define SLINK_RX_TRIG_MASK (3 << 18)
114 #define SLINK_PACKED (1 << 20)
115 #define SLINK_PACK_SIZE_4 (0 << 21)
116 #define SLINK_PACK_SIZE_8 (1 << 21)
117 #define SLINK_PACK_SIZE_16 (2 << 21)
118 #define SLINK_PACK_SIZE_32 (3 << 21)
119 #define SLINK_PACK_SIZE_MASK (3 << 21)
120 #define SLINK_IE_TXC (1 << 26)
121 #define SLINK_IE_RXC (1 << 27)
122 #define SLINK_DMA_EN (1 << 31)
124 #define SLINK_STATUS2 0x01c
125 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
126 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
127 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
129 #define SLINK_TX_FIFO 0x100
130 #define SLINK_RX_FIFO 0x180
132 #define DATA_DIR_TX (1 << 0)
133 #define DATA_DIR_RX (1 << 1)
135 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
137 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
138 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
139 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
141 #define SLINK_STATUS2_RESET \
142 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
144 #define MAX_CHIP_SELECT 4
145 #define SLINK_FIFO_DEPTH 32
147 struct tegra_slink_chip_data {
151 struct tegra_slink_data {
153 struct spi_master *master;
154 const struct tegra_slink_chip_data *chip_data;
158 struct reset_control *rst;
164 struct spi_device *cur_spi;
167 unsigned words_per_32bit;
168 unsigned bytes_per_word;
169 unsigned curr_dma_words;
170 unsigned cur_direction;
175 unsigned dma_buf_size;
176 unsigned max_buf_size;
177 bool is_curr_dma_xfer;
179 struct completion rx_dma_complete;
180 struct completion tx_dma_complete;
192 u32 def_command2_reg;
194 struct completion xfer_completion;
195 struct spi_transfer *curr_xfer;
196 struct dma_chan *rx_dma_chan;
198 dma_addr_t rx_dma_phys;
199 struct dma_async_tx_descriptor *rx_dma_desc;
201 struct dma_chan *tx_dma_chan;
203 dma_addr_t tx_dma_phys;
204 struct dma_async_tx_descriptor *tx_dma_desc;
207 static int tegra_slink_runtime_suspend(struct device *dev);
208 static int tegra_slink_runtime_resume(struct device *dev);
210 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
213 return readl(tspi->base + reg);
216 static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
217 u32 val, unsigned long reg)
219 writel(val, tspi->base + reg);
221 /* Read back register to make sure that register writes completed */
222 if (reg != SLINK_TX_FIFO)
223 readl(tspi->base + SLINK_MAS_DATA);
226 static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
230 tegra_slink_readl(tspi, SLINK_STATUS);
232 /* Write 1 to clear status register */
233 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
234 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
237 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
238 struct spi_transfer *t)
240 switch (tspi->bytes_per_word) {
242 return SLINK_PACK_SIZE_4;
244 return SLINK_PACK_SIZE_8;
246 return SLINK_PACK_SIZE_16;
248 return SLINK_PACK_SIZE_32;
254 static unsigned tegra_slink_calculate_curr_xfer_param(
255 struct spi_device *spi, struct tegra_slink_data *tspi,
256 struct spi_transfer *t)
258 unsigned remain_len = t->len - tspi->cur_pos;
260 unsigned bits_per_word;
262 unsigned total_fifo_words;
264 bits_per_word = t->bits_per_word;
265 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
267 if (bits_per_word == 8 || bits_per_word == 16) {
268 tspi->is_packed = true;
269 tspi->words_per_32bit = 32/bits_per_word;
271 tspi->is_packed = false;
272 tspi->words_per_32bit = 1;
274 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
276 if (tspi->is_packed) {
277 max_len = min(remain_len, tspi->max_buf_size);
278 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
279 total_fifo_words = max_len/4;
281 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
282 max_word = min(max_word, tspi->max_buf_size/4);
283 tspi->curr_dma_words = max_word;
284 total_fifo_words = max_word;
286 return total_fifo_words;
289 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
290 struct tegra_slink_data *tspi, struct spi_transfer *t)
293 unsigned tx_empty_count;
295 unsigned max_n_32bit;
297 unsigned int written_words;
298 unsigned fifo_words_left;
299 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
301 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
302 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
304 if (tspi->is_packed) {
305 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
306 written_words = min(fifo_words_left, tspi->curr_dma_words);
307 nbytes = written_words * tspi->bytes_per_word;
308 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
309 for (count = 0; count < max_n_32bit; count++) {
311 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
312 x |= (u32)(*tx_buf++) << (i * 8);
313 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
316 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
317 written_words = max_n_32bit;
318 nbytes = written_words * tspi->bytes_per_word;
319 for (count = 0; count < max_n_32bit; count++) {
321 for (i = 0; nbytes && (i < tspi->bytes_per_word);
323 x |= (u32)(*tx_buf++) << (i * 8);
324 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
327 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
328 return written_words;
331 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
332 struct tegra_slink_data *tspi, struct spi_transfer *t)
334 unsigned rx_full_count;
337 unsigned int read_words = 0;
339 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
341 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
342 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
343 if (tspi->is_packed) {
344 len = tspi->curr_dma_words * tspi->bytes_per_word;
345 for (count = 0; count < rx_full_count; count++) {
346 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
347 for (i = 0; len && (i < 4); i++, len--)
348 *rx_buf++ = (x >> i*8) & 0xFF;
350 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
351 read_words += tspi->curr_dma_words;
353 for (count = 0; count < rx_full_count; count++) {
354 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
355 for (i = 0; (i < tspi->bytes_per_word); i++)
356 *rx_buf++ = (x >> (i*8)) & 0xFF;
358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
359 read_words += rx_full_count;
364 static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
365 struct tegra_slink_data *tspi, struct spi_transfer *t)
367 /* Make the dma buffer to read by cpu */
368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
369 tspi->dma_buf_size, DMA_TO_DEVICE);
371 if (tspi->is_packed) {
372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
373 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
377 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
378 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
380 for (count = 0; count < tspi->curr_dma_words; count++) {
382 for (i = 0; consume && (i < tspi->bytes_per_word);
384 x |= (u32)(*tx_buf++) << (i * 8);
385 tspi->tx_dma_buf[count] = x;
388 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
390 /* Make the dma buffer to read by dma */
391 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
392 tspi->dma_buf_size, DMA_TO_DEVICE);
395 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
396 struct tegra_slink_data *tspi, struct spi_transfer *t)
400 /* Make the dma buffer to read by cpu */
401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
402 tspi->dma_buf_size, DMA_FROM_DEVICE);
404 if (tspi->is_packed) {
405 len = tspi->curr_dma_words * tspi->bytes_per_word;
406 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
410 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
411 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
413 for (count = 0; count < tspi->curr_dma_words; count++) {
414 u32 x = tspi->rx_dma_buf[count] & rx_mask;
415 for (i = 0; (i < tspi->bytes_per_word); i++)
416 *rx_buf++ = (x >> (i*8)) & 0xFF;
419 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
421 /* Make the dma buffer to read by dma */
422 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
423 tspi->dma_buf_size, DMA_FROM_DEVICE);
426 static void tegra_slink_dma_complete(void *args)
428 struct completion *dma_complete = args;
430 complete(dma_complete);
433 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
435 reinit_completion(&tspi->tx_dma_complete);
436 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
437 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
438 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
439 if (!tspi->tx_dma_desc) {
440 dev_err(tspi->dev, "Not able to get desc for Tx\n");
444 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
445 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
447 dmaengine_submit(tspi->tx_dma_desc);
448 dma_async_issue_pending(tspi->tx_dma_chan);
452 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
454 reinit_completion(&tspi->rx_dma_complete);
455 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
456 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
458 if (!tspi->rx_dma_desc) {
459 dev_err(tspi->dev, "Not able to get desc for Rx\n");
463 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
464 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
466 dmaengine_submit(tspi->rx_dma_desc);
467 dma_async_issue_pending(tspi->rx_dma_chan);
471 static int tegra_slink_start_dma_based_transfer(
472 struct tegra_slink_data *tspi, struct spi_transfer *t)
479 /* Make sure that Rx and Tx fifo are empty */
480 status = tegra_slink_readl(tspi, SLINK_STATUS);
481 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
482 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
487 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
488 val |= tspi->packed_size;
490 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
493 len = tspi->curr_dma_words * 4;
495 /* Set attention level based on length of transfer */
497 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
498 else if (((len) >> 4) & 0x1)
499 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
501 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
503 if (tspi->cur_direction & DATA_DIR_TX)
506 if (tspi->cur_direction & DATA_DIR_RX)
509 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
510 tspi->dma_control_reg = val;
512 if (tspi->cur_direction & DATA_DIR_TX) {
513 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
515 ret = tegra_slink_start_tx_dma(tspi, len);
518 "Starting tx dma failed, err %d\n", ret);
522 /* Wait for tx fifo to be fill before starting slink */
523 status = tegra_slink_readl(tspi, SLINK_STATUS);
524 while (!(status & SLINK_TX_FULL))
525 status = tegra_slink_readl(tspi, SLINK_STATUS);
528 if (tspi->cur_direction & DATA_DIR_RX) {
529 /* Make the dma buffer to read by dma */
530 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
531 tspi->dma_buf_size, DMA_FROM_DEVICE);
533 ret = tegra_slink_start_rx_dma(tspi, len);
536 "Starting rx dma failed, err %d\n", ret);
537 if (tspi->cur_direction & DATA_DIR_TX)
538 dmaengine_terminate_all(tspi->tx_dma_chan);
542 tspi->is_curr_dma_xfer = true;
543 if (tspi->is_packed) {
545 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
546 /* HW need small delay after settign Packed mode */
549 tspi->dma_control_reg = val;
552 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
556 static int tegra_slink_start_cpu_based_transfer(
557 struct tegra_slink_data *tspi, struct spi_transfer *t)
562 val = tspi->packed_size;
563 if (tspi->cur_direction & DATA_DIR_TX)
566 if (tspi->cur_direction & DATA_DIR_RX)
569 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
570 tspi->dma_control_reg = val;
572 if (tspi->cur_direction & DATA_DIR_TX)
573 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
575 cur_words = tspi->curr_dma_words;
576 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
577 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
578 tspi->dma_control_reg = val;
580 tspi->is_curr_dma_xfer = false;
581 if (tspi->is_packed) {
583 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
587 tspi->dma_control_reg = val;
589 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
593 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
596 struct dma_chan *dma_chan;
600 struct dma_slave_config dma_sconfig;
602 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
603 if (IS_ERR(dma_chan)) {
604 ret = PTR_ERR(dma_chan);
605 if (ret != -EPROBE_DEFER)
607 "Dma channel is not available: %d\n", ret);
611 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
612 &dma_phys, GFP_KERNEL);
614 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
615 dma_release_channel(dma_chan);
620 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
621 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
622 dma_sconfig.src_maxburst = 0;
624 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
625 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
626 dma_sconfig.dst_maxburst = 0;
629 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
633 tspi->rx_dma_chan = dma_chan;
634 tspi->rx_dma_buf = dma_buf;
635 tspi->rx_dma_phys = dma_phys;
637 tspi->tx_dma_chan = dma_chan;
638 tspi->tx_dma_buf = dma_buf;
639 tspi->tx_dma_phys = dma_phys;
644 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
645 dma_release_channel(dma_chan);
649 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
654 struct dma_chan *dma_chan;
657 dma_buf = tspi->rx_dma_buf;
658 dma_chan = tspi->rx_dma_chan;
659 dma_phys = tspi->rx_dma_phys;
660 tspi->rx_dma_chan = NULL;
661 tspi->rx_dma_buf = NULL;
663 dma_buf = tspi->tx_dma_buf;
664 dma_chan = tspi->tx_dma_chan;
665 dma_phys = tspi->tx_dma_phys;
666 tspi->tx_dma_buf = NULL;
667 tspi->tx_dma_chan = NULL;
672 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
673 dma_release_channel(dma_chan);
676 static int tegra_slink_start_transfer_one(struct spi_device *spi,
677 struct spi_transfer *t)
679 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
682 unsigned total_fifo_words;
687 bits_per_word = t->bits_per_word;
689 if (speed != tspi->cur_speed) {
690 clk_set_rate(tspi->clk, speed * 4);
691 tspi->cur_speed = speed;
696 tspi->cur_rx_pos = 0;
697 tspi->cur_tx_pos = 0;
699 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
701 command = tspi->command_reg;
702 command &= ~SLINK_BIT_LENGTH(~0);
703 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
705 command2 = tspi->command2_reg;
706 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
708 tspi->cur_direction = 0;
710 command2 |= SLINK_RXEN;
711 tspi->cur_direction |= DATA_DIR_RX;
714 command2 |= SLINK_TXEN;
715 tspi->cur_direction |= DATA_DIR_TX;
719 * Writing to the command2 register bevore the command register prevents
720 * a spike in chip_select line 0. This selects the chip_select line
721 * before changing the chip_select value.
723 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
724 tspi->command2_reg = command2;
726 tegra_slink_writel(tspi, command, SLINK_COMMAND);
727 tspi->command_reg = command;
729 if (total_fifo_words > SLINK_FIFO_DEPTH)
730 ret = tegra_slink_start_dma_based_transfer(tspi, t);
732 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
736 static int tegra_slink_setup(struct spi_device *spi)
738 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
745 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
750 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
752 spi->mode & SPI_CPOL ? "" : "~",
753 spi->mode & SPI_CPHA ? "" : "~",
756 ret = pm_runtime_get_sync(tspi->dev);
758 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
762 spin_lock_irqsave(&tspi->lock, flags);
763 val = tspi->def_command_reg;
764 if (spi->mode & SPI_CS_HIGH)
765 val |= cs_pol_bit[spi->chip_select];
767 val &= ~cs_pol_bit[spi->chip_select];
768 tspi->def_command_reg = val;
769 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
770 spin_unlock_irqrestore(&tspi->lock, flags);
772 pm_runtime_put(tspi->dev);
776 static int tegra_slink_prepare_message(struct spi_master *master,
777 struct spi_message *msg)
779 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
780 struct spi_device *spi = msg->spi;
782 tegra_slink_clear_status(tspi);
784 tspi->command_reg = tspi->def_command_reg;
785 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
787 tspi->command2_reg = tspi->def_command2_reg;
788 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
790 tspi->command_reg &= ~SLINK_MODES;
791 if (spi->mode & SPI_CPHA)
792 tspi->command_reg |= SLINK_CK_SDA;
794 if (spi->mode & SPI_CPOL)
795 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
797 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
802 static int tegra_slink_transfer_one(struct spi_master *master,
803 struct spi_device *spi,
804 struct spi_transfer *xfer)
806 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
809 reinit_completion(&tspi->xfer_completion);
810 ret = tegra_slink_start_transfer_one(spi, xfer);
813 "spi can not start transfer, err %d\n", ret);
817 ret = wait_for_completion_timeout(&tspi->xfer_completion,
819 if (WARN_ON(ret == 0)) {
821 "spi transfer timeout, err %d\n", ret);
826 return tspi->tx_status;
828 return tspi->rx_status;
833 static int tegra_slink_unprepare_message(struct spi_master *master,
834 struct spi_message *msg)
836 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
838 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
839 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
844 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
846 struct spi_transfer *t = tspi->curr_xfer;
849 spin_lock_irqsave(&tspi->lock, flags);
850 if (tspi->tx_status || tspi->rx_status ||
851 (tspi->status_reg & SLINK_BSY)) {
853 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
855 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
856 tspi->command2_reg, tspi->dma_control_reg);
857 reset_control_assert(tspi->rst);
859 reset_control_deassert(tspi->rst);
860 complete(&tspi->xfer_completion);
864 if (tspi->cur_direction & DATA_DIR_RX)
865 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
867 if (tspi->cur_direction & DATA_DIR_TX)
868 tspi->cur_pos = tspi->cur_tx_pos;
870 tspi->cur_pos = tspi->cur_rx_pos;
872 if (tspi->cur_pos == t->len) {
873 complete(&tspi->xfer_completion);
877 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
878 tegra_slink_start_cpu_based_transfer(tspi, t);
880 spin_unlock_irqrestore(&tspi->lock, flags);
884 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
886 struct spi_transfer *t = tspi->curr_xfer;
889 unsigned total_fifo_words;
892 /* Abort dmas if any error */
893 if (tspi->cur_direction & DATA_DIR_TX) {
894 if (tspi->tx_status) {
895 dmaengine_terminate_all(tspi->tx_dma_chan);
898 wait_status = wait_for_completion_interruptible_timeout(
899 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
900 if (wait_status <= 0) {
901 dmaengine_terminate_all(tspi->tx_dma_chan);
902 dev_err(tspi->dev, "TxDma Xfer failed\n");
908 if (tspi->cur_direction & DATA_DIR_RX) {
909 if (tspi->rx_status) {
910 dmaengine_terminate_all(tspi->rx_dma_chan);
913 wait_status = wait_for_completion_interruptible_timeout(
914 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
915 if (wait_status <= 0) {
916 dmaengine_terminate_all(tspi->rx_dma_chan);
917 dev_err(tspi->dev, "RxDma Xfer failed\n");
923 spin_lock_irqsave(&tspi->lock, flags);
926 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
928 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
929 tspi->command2_reg, tspi->dma_control_reg);
930 reset_control_assert(tspi->rst);
932 reset_control_assert(tspi->rst);
933 complete(&tspi->xfer_completion);
934 spin_unlock_irqrestore(&tspi->lock, flags);
938 if (tspi->cur_direction & DATA_DIR_RX)
939 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
941 if (tspi->cur_direction & DATA_DIR_TX)
942 tspi->cur_pos = tspi->cur_tx_pos;
944 tspi->cur_pos = tspi->cur_rx_pos;
946 if (tspi->cur_pos == t->len) {
947 complete(&tspi->xfer_completion);
951 /* Continue transfer in current message */
952 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
954 if (total_fifo_words > SLINK_FIFO_DEPTH)
955 err = tegra_slink_start_dma_based_transfer(tspi, t);
957 err = tegra_slink_start_cpu_based_transfer(tspi, t);
960 spin_unlock_irqrestore(&tspi->lock, flags);
964 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
966 struct tegra_slink_data *tspi = context_data;
968 if (!tspi->is_curr_dma_xfer)
969 return handle_cpu_based_xfer(tspi);
970 return handle_dma_based_xfer(tspi);
973 static irqreturn_t tegra_slink_isr(int irq, void *context_data)
975 struct tegra_slink_data *tspi = context_data;
977 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
978 if (tspi->cur_direction & DATA_DIR_TX)
979 tspi->tx_status = tspi->status_reg &
980 (SLINK_TX_OVF | SLINK_TX_UNF);
982 if (tspi->cur_direction & DATA_DIR_RX)
983 tspi->rx_status = tspi->status_reg &
984 (SLINK_RX_OVF | SLINK_RX_UNF);
985 tegra_slink_clear_status(tspi);
987 return IRQ_WAKE_THREAD;
990 static const struct tegra_slink_chip_data tegra30_spi_cdata = {
991 .cs_hold_time = true,
994 static const struct tegra_slink_chip_data tegra20_spi_cdata = {
995 .cs_hold_time = false,
998 static const struct of_device_id tegra_slink_of_match[] = {
999 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
1000 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1003 MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1005 static int tegra_slink_probe(struct platform_device *pdev)
1007 struct spi_master *master;
1008 struct tegra_slink_data *tspi;
1011 const struct tegra_slink_chip_data *cdata = NULL;
1012 const struct of_device_id *match;
1014 match = of_match_device(tegra_slink_of_match, &pdev->dev);
1016 dev_err(&pdev->dev, "Error: No device match found\n");
1019 cdata = match->data;
1021 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1023 dev_err(&pdev->dev, "master allocation failed\n");
1027 /* the spi->mode bits understood by this driver: */
1028 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1029 master->setup = tegra_slink_setup;
1030 master->prepare_message = tegra_slink_prepare_message;
1031 master->transfer_one = tegra_slink_transfer_one;
1032 master->unprepare_message = tegra_slink_unprepare_message;
1033 master->auto_runtime_pm = true;
1034 master->num_chipselect = MAX_CHIP_SELECT;
1036 platform_set_drvdata(pdev, master);
1037 tspi = spi_master_get_devdata(master);
1038 tspi->master = master;
1039 tspi->dev = &pdev->dev;
1040 tspi->chip_data = cdata;
1041 spin_lock_init(&tspi->lock);
1043 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1044 &master->max_speed_hz))
1045 master->max_speed_hz = 25000000; /* 25MHz */
1047 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1049 dev_err(&pdev->dev, "No IO memory resource\n");
1051 goto exit_free_master;
1053 tspi->phys = r->start;
1054 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1055 if (IS_ERR(tspi->base)) {
1056 ret = PTR_ERR(tspi->base);
1057 goto exit_free_master;
1060 /* disabled clock may cause interrupt storm upon request */
1061 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1062 if (IS_ERR(tspi->clk)) {
1063 ret = PTR_ERR(tspi->clk);
1064 dev_err(&pdev->dev, "Can not get clock %d\n", ret);
1065 goto exit_free_master;
1067 ret = clk_prepare(tspi->clk);
1069 dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
1070 goto exit_free_master;
1072 ret = clk_enable(tspi->clk);
1074 dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
1075 goto exit_clk_unprepare;
1078 spi_irq = platform_get_irq(pdev, 0);
1079 tspi->irq = spi_irq;
1080 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1081 tegra_slink_isr_thread, IRQF_ONESHOT,
1082 dev_name(&pdev->dev), tspi);
1084 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1086 goto exit_clk_disable;
1089 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1090 if (IS_ERR(tspi->rst)) {
1091 dev_err(&pdev->dev, "can not get reset\n");
1092 ret = PTR_ERR(tspi->rst);
1096 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1097 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1099 ret = tegra_slink_init_dma_param(tspi, true);
1102 ret = tegra_slink_init_dma_param(tspi, false);
1104 goto exit_rx_dma_free;
1105 tspi->max_buf_size = tspi->dma_buf_size;
1106 init_completion(&tspi->tx_dma_complete);
1107 init_completion(&tspi->rx_dma_complete);
1109 init_completion(&tspi->xfer_completion);
1111 pm_runtime_enable(&pdev->dev);
1112 if (!pm_runtime_enabled(&pdev->dev)) {
1113 ret = tegra_slink_runtime_resume(&pdev->dev);
1115 goto exit_pm_disable;
1118 ret = pm_runtime_get_sync(&pdev->dev);
1120 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1121 pm_runtime_put_noidle(&pdev->dev);
1122 goto exit_pm_disable;
1124 tspi->def_command_reg = SLINK_M_S;
1125 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1126 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1127 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1128 pm_runtime_put(&pdev->dev);
1130 master->dev.of_node = pdev->dev.of_node;
1131 ret = devm_spi_register_master(&pdev->dev, master);
1133 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1134 goto exit_pm_disable;
1139 pm_runtime_disable(&pdev->dev);
1140 if (!pm_runtime_status_suspended(&pdev->dev))
1141 tegra_slink_runtime_suspend(&pdev->dev);
1142 tegra_slink_deinit_dma_param(tspi, false);
1144 tegra_slink_deinit_dma_param(tspi, true);
1146 free_irq(spi_irq, tspi);
1148 clk_disable(tspi->clk);
1150 clk_unprepare(tspi->clk);
1152 spi_master_put(master);
1156 static int tegra_slink_remove(struct platform_device *pdev)
1158 struct spi_master *master = platform_get_drvdata(pdev);
1159 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1161 free_irq(tspi->irq, tspi);
1163 clk_disable(tspi->clk);
1164 clk_unprepare(tspi->clk);
1166 if (tspi->tx_dma_chan)
1167 tegra_slink_deinit_dma_param(tspi, false);
1169 if (tspi->rx_dma_chan)
1170 tegra_slink_deinit_dma_param(tspi, true);
1172 pm_runtime_disable(&pdev->dev);
1173 if (!pm_runtime_status_suspended(&pdev->dev))
1174 tegra_slink_runtime_suspend(&pdev->dev);
1179 #ifdef CONFIG_PM_SLEEP
1180 static int tegra_slink_suspend(struct device *dev)
1182 struct spi_master *master = dev_get_drvdata(dev);
1184 return spi_master_suspend(master);
1187 static int tegra_slink_resume(struct device *dev)
1189 struct spi_master *master = dev_get_drvdata(dev);
1190 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1193 ret = pm_runtime_get_sync(dev);
1195 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1198 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1199 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1200 pm_runtime_put(dev);
1202 return spi_master_resume(master);
1206 static int tegra_slink_runtime_suspend(struct device *dev)
1208 struct spi_master *master = dev_get_drvdata(dev);
1209 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1211 /* Flush all write which are in PPSB queue by reading back */
1212 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1214 clk_disable_unprepare(tspi->clk);
1218 static int tegra_slink_runtime_resume(struct device *dev)
1220 struct spi_master *master = dev_get_drvdata(dev);
1221 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1224 ret = clk_prepare_enable(tspi->clk);
1226 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1232 static const struct dev_pm_ops slink_pm_ops = {
1233 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1234 tegra_slink_runtime_resume, NULL)
1235 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1237 static struct platform_driver tegra_slink_driver = {
1239 .name = "spi-tegra-slink",
1240 .pm = &slink_pm_ops,
1241 .of_match_table = tegra_slink_of_match,
1243 .probe = tegra_slink_probe,
1244 .remove = tegra_slink_remove,
1246 module_platform_driver(tegra_slink_driver);
1248 MODULE_ALIAS("platform:spi-tegra-slink");
1249 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1250 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1251 MODULE_LICENSE("GPL v2");