2 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
38 #define SLINK_COMMAND 0x000
39 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
41 #define SLINK_BOTH_EN (1 << 10)
42 #define SLINK_CS_SW (1 << 11)
43 #define SLINK_CS_VALUE (1 << 12)
44 #define SLINK_CS_POLARITY (1 << 13)
45 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
46 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
47 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
48 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
49 #define SLINK_IDLE_SDA_MASK (3 << 16)
50 #define SLINK_CS_POLARITY1 (1 << 20)
51 #define SLINK_CK_SDA (1 << 21)
52 #define SLINK_CS_POLARITY2 (1 << 22)
53 #define SLINK_CS_POLARITY3 (1 << 23)
54 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
55 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
56 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
57 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
58 #define SLINK_IDLE_SCLK_MASK (3 << 24)
59 #define SLINK_M_S (1 << 28)
60 #define SLINK_WAIT (1 << 29)
61 #define SLINK_GO (1 << 30)
62 #define SLINK_ENB (1 << 31)
64 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
66 #define SLINK_COMMAND2 0x004
67 #define SLINK_LSBFE (1 << 0)
68 #define SLINK_SSOE (1 << 1)
69 #define SLINK_SPIE (1 << 4)
70 #define SLINK_BIDIROE (1 << 6)
71 #define SLINK_MODFEN (1 << 7)
72 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
73 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
74 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
75 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
76 #define SLINK_FIFO_REFILLS_0 (0 << 22)
77 #define SLINK_FIFO_REFILLS_1 (1 << 22)
78 #define SLINK_FIFO_REFILLS_2 (2 << 22)
79 #define SLINK_FIFO_REFILLS_3 (3 << 22)
80 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
81 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
82 #define SLINK_SPC0 (1 << 29)
83 #define SLINK_TXEN (1 << 30)
84 #define SLINK_RXEN (1 << 31)
86 #define SLINK_STATUS 0x008
87 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
88 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
89 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
90 #define SLINK_MODF (1 << 16)
91 #define SLINK_RX_UNF (1 << 18)
92 #define SLINK_TX_OVF (1 << 19)
93 #define SLINK_TX_FULL (1 << 20)
94 #define SLINK_TX_EMPTY (1 << 21)
95 #define SLINK_RX_FULL (1 << 22)
96 #define SLINK_RX_EMPTY (1 << 23)
97 #define SLINK_TX_UNF (1 << 24)
98 #define SLINK_RX_OVF (1 << 25)
99 #define SLINK_TX_FLUSH (1 << 26)
100 #define SLINK_RX_FLUSH (1 << 27)
101 #define SLINK_SCLK (1 << 28)
102 #define SLINK_ERR (1 << 29)
103 #define SLINK_RDY (1 << 30)
104 #define SLINK_BSY (1 << 31)
105 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
106 SLINK_TX_UNF | SLINK_RX_OVF)
108 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
110 #define SLINK_MAS_DATA 0x010
111 #define SLINK_SLAVE_DATA 0x014
113 #define SLINK_DMA_CTL 0x018
114 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
115 #define SLINK_TX_TRIG_1 (0 << 16)
116 #define SLINK_TX_TRIG_4 (1 << 16)
117 #define SLINK_TX_TRIG_8 (2 << 16)
118 #define SLINK_TX_TRIG_16 (3 << 16)
119 #define SLINK_TX_TRIG_MASK (3 << 16)
120 #define SLINK_RX_TRIG_1 (0 << 18)
121 #define SLINK_RX_TRIG_4 (1 << 18)
122 #define SLINK_RX_TRIG_8 (2 << 18)
123 #define SLINK_RX_TRIG_16 (3 << 18)
124 #define SLINK_RX_TRIG_MASK (3 << 18)
125 #define SLINK_PACKED (1 << 20)
126 #define SLINK_PACK_SIZE_4 (0 << 21)
127 #define SLINK_PACK_SIZE_8 (1 << 21)
128 #define SLINK_PACK_SIZE_16 (2 << 21)
129 #define SLINK_PACK_SIZE_32 (3 << 21)
130 #define SLINK_PACK_SIZE_MASK (3 << 21)
131 #define SLINK_IE_TXC (1 << 26)
132 #define SLINK_IE_RXC (1 << 27)
133 #define SLINK_DMA_EN (1 << 31)
135 #define SLINK_STATUS2 0x01c
136 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
137 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
138 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
140 #define SLINK_TX_FIFO 0x100
141 #define SLINK_RX_FIFO 0x180
143 #define DATA_DIR_TX (1 << 0)
144 #define DATA_DIR_RX (1 << 1)
146 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
148 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
149 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
150 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
152 #define SLINK_STATUS2_RESET \
153 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
155 #define MAX_CHIP_SELECT 4
156 #define SLINK_FIFO_DEPTH 32
158 struct tegra_slink_chip_data {
162 struct tegra_slink_data {
164 struct spi_master *master;
165 const struct tegra_slink_chip_data *chip_data;
169 struct reset_control *rst;
173 u32 spi_max_frequency;
176 struct spi_device *cur_spi;
179 unsigned words_per_32bit;
180 unsigned bytes_per_word;
181 unsigned curr_dma_words;
182 unsigned cur_direction;
187 unsigned dma_buf_size;
188 unsigned max_buf_size;
189 bool is_curr_dma_xfer;
191 struct completion rx_dma_complete;
192 struct completion tx_dma_complete;
204 u32 def_command2_reg;
206 struct completion xfer_completion;
207 struct spi_transfer *curr_xfer;
208 struct dma_chan *rx_dma_chan;
210 dma_addr_t rx_dma_phys;
211 struct dma_async_tx_descriptor *rx_dma_desc;
213 struct dma_chan *tx_dma_chan;
215 dma_addr_t tx_dma_phys;
216 struct dma_async_tx_descriptor *tx_dma_desc;
219 static int tegra_slink_runtime_suspend(struct device *dev);
220 static int tegra_slink_runtime_resume(struct device *dev);
222 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
225 return readl(tspi->base + reg);
228 static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
229 u32 val, unsigned long reg)
231 writel(val, tspi->base + reg);
233 /* Read back register to make sure that register writes completed */
234 if (reg != SLINK_TX_FIFO)
235 readl(tspi->base + SLINK_MAS_DATA);
238 static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
242 tegra_slink_readl(tspi, SLINK_STATUS);
244 /* Write 1 to clear status register */
245 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
246 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
249 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
250 struct spi_transfer *t)
252 switch (tspi->bytes_per_word) {
254 return SLINK_PACK_SIZE_4;
256 return SLINK_PACK_SIZE_8;
258 return SLINK_PACK_SIZE_16;
260 return SLINK_PACK_SIZE_32;
266 static unsigned tegra_slink_calculate_curr_xfer_param(
267 struct spi_device *spi, struct tegra_slink_data *tspi,
268 struct spi_transfer *t)
270 unsigned remain_len = t->len - tspi->cur_pos;
272 unsigned bits_per_word;
274 unsigned total_fifo_words;
276 bits_per_word = t->bits_per_word;
277 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
279 if (bits_per_word == 8 || bits_per_word == 16) {
281 tspi->words_per_32bit = 32/bits_per_word;
284 tspi->words_per_32bit = 1;
286 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
288 if (tspi->is_packed) {
289 max_len = min(remain_len, tspi->max_buf_size);
290 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
291 total_fifo_words = max_len/4;
293 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
294 max_word = min(max_word, tspi->max_buf_size/4);
295 tspi->curr_dma_words = max_word;
296 total_fifo_words = max_word;
298 return total_fifo_words;
301 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
302 struct tegra_slink_data *tspi, struct spi_transfer *t)
305 unsigned tx_empty_count;
307 unsigned max_n_32bit;
309 unsigned int written_words;
310 unsigned fifo_words_left;
311 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
313 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
314 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
316 if (tspi->is_packed) {
317 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
318 written_words = min(fifo_words_left, tspi->curr_dma_words);
319 nbytes = written_words * tspi->bytes_per_word;
320 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
321 for (count = 0; count < max_n_32bit; count++) {
323 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
324 x |= (u32)(*tx_buf++) << (i * 8);
325 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
328 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
329 written_words = max_n_32bit;
330 nbytes = written_words * tspi->bytes_per_word;
331 for (count = 0; count < max_n_32bit; count++) {
333 for (i = 0; nbytes && (i < tspi->bytes_per_word);
335 x |= (u32)(*tx_buf++) << (i * 8);
336 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
339 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
340 return written_words;
343 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
344 struct tegra_slink_data *tspi, struct spi_transfer *t)
346 unsigned rx_full_count;
349 unsigned int read_words = 0;
351 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
353 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
354 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
355 if (tspi->is_packed) {
356 len = tspi->curr_dma_words * tspi->bytes_per_word;
357 for (count = 0; count < rx_full_count; count++) {
358 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
359 for (i = 0; len && (i < 4); i++, len--)
360 *rx_buf++ = (x >> i*8) & 0xFF;
362 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
363 read_words += tspi->curr_dma_words;
365 for (count = 0; count < rx_full_count; count++) {
366 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
367 for (i = 0; (i < tspi->bytes_per_word); i++)
368 *rx_buf++ = (x >> (i*8)) & 0xFF;
370 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
371 read_words += rx_full_count;
376 static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
377 struct tegra_slink_data *tspi, struct spi_transfer *t)
379 /* Make the dma buffer to read by cpu */
380 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
381 tspi->dma_buf_size, DMA_TO_DEVICE);
383 if (tspi->is_packed) {
384 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
385 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
389 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
390 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
392 for (count = 0; count < tspi->curr_dma_words; count++) {
394 for (i = 0; consume && (i < tspi->bytes_per_word);
396 x |= (u32)(*tx_buf++) << (i * 8);
397 tspi->tx_dma_buf[count] = x;
400 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
402 /* Make the dma buffer to read by dma */
403 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
404 tspi->dma_buf_size, DMA_TO_DEVICE);
407 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
408 struct tegra_slink_data *tspi, struct spi_transfer *t)
412 /* Make the dma buffer to read by cpu */
413 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
414 tspi->dma_buf_size, DMA_FROM_DEVICE);
416 if (tspi->is_packed) {
417 len = tspi->curr_dma_words * tspi->bytes_per_word;
418 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
422 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
423 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
425 for (count = 0; count < tspi->curr_dma_words; count++) {
426 u32 x = tspi->rx_dma_buf[count] & rx_mask;
427 for (i = 0; (i < tspi->bytes_per_word); i++)
428 *rx_buf++ = (x >> (i*8)) & 0xFF;
431 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
433 /* Make the dma buffer to read by dma */
434 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
435 tspi->dma_buf_size, DMA_FROM_DEVICE);
438 static void tegra_slink_dma_complete(void *args)
440 struct completion *dma_complete = args;
442 complete(dma_complete);
445 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
447 reinit_completion(&tspi->tx_dma_complete);
448 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
449 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
450 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
451 if (!tspi->tx_dma_desc) {
452 dev_err(tspi->dev, "Not able to get desc for Tx\n");
456 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
457 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
459 dmaengine_submit(tspi->tx_dma_desc);
460 dma_async_issue_pending(tspi->tx_dma_chan);
464 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
466 reinit_completion(&tspi->rx_dma_complete);
467 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
468 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
469 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
470 if (!tspi->rx_dma_desc) {
471 dev_err(tspi->dev, "Not able to get desc for Rx\n");
475 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
476 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
478 dmaengine_submit(tspi->rx_dma_desc);
479 dma_async_issue_pending(tspi->rx_dma_chan);
483 static int tegra_slink_start_dma_based_transfer(
484 struct tegra_slink_data *tspi, struct spi_transfer *t)
491 /* Make sure that Rx and Tx fifo are empty */
492 status = tegra_slink_readl(tspi, SLINK_STATUS);
493 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
494 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
499 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
500 val |= tspi->packed_size;
502 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
505 len = tspi->curr_dma_words * 4;
507 /* Set attention level based on length of transfer */
509 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
510 else if (((len) >> 4) & 0x1)
511 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
513 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
515 if (tspi->cur_direction & DATA_DIR_TX)
518 if (tspi->cur_direction & DATA_DIR_RX)
521 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
522 tspi->dma_control_reg = val;
524 if (tspi->cur_direction & DATA_DIR_TX) {
525 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
527 ret = tegra_slink_start_tx_dma(tspi, len);
530 "Starting tx dma failed, err %d\n", ret);
534 /* Wait for tx fifo to be fill before starting slink */
535 status = tegra_slink_readl(tspi, SLINK_STATUS);
536 while (!(status & SLINK_TX_FULL))
537 status = tegra_slink_readl(tspi, SLINK_STATUS);
540 if (tspi->cur_direction & DATA_DIR_RX) {
541 /* Make the dma buffer to read by dma */
542 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
543 tspi->dma_buf_size, DMA_FROM_DEVICE);
545 ret = tegra_slink_start_rx_dma(tspi, len);
548 "Starting rx dma failed, err %d\n", ret);
549 if (tspi->cur_direction & DATA_DIR_TX)
550 dmaengine_terminate_all(tspi->tx_dma_chan);
554 tspi->is_curr_dma_xfer = true;
555 if (tspi->is_packed) {
557 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
558 /* HW need small delay after settign Packed mode */
561 tspi->dma_control_reg = val;
564 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
568 static int tegra_slink_start_cpu_based_transfer(
569 struct tegra_slink_data *tspi, struct spi_transfer *t)
574 val = tspi->packed_size;
575 if (tspi->cur_direction & DATA_DIR_TX)
578 if (tspi->cur_direction & DATA_DIR_RX)
581 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
582 tspi->dma_control_reg = val;
584 if (tspi->cur_direction & DATA_DIR_TX)
585 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
587 cur_words = tspi->curr_dma_words;
588 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
589 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
590 tspi->dma_control_reg = val;
592 tspi->is_curr_dma_xfer = false;
593 if (tspi->is_packed) {
595 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
599 tspi->dma_control_reg = val;
601 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
605 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
608 struct dma_chan *dma_chan;
612 struct dma_slave_config dma_sconfig;
614 dma_chan = dma_request_slave_channel_reason(tspi->dev,
615 dma_to_memory ? "rx" : "tx");
616 if (IS_ERR(dma_chan)) {
617 ret = PTR_ERR(dma_chan);
618 if (ret != -EPROBE_DEFER)
620 "Dma channel is not available: %d\n", ret);
624 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
625 &dma_phys, GFP_KERNEL);
627 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
628 dma_release_channel(dma_chan);
633 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
634 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
635 dma_sconfig.src_maxburst = 0;
637 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
638 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
639 dma_sconfig.dst_maxburst = 0;
642 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
646 tspi->rx_dma_chan = dma_chan;
647 tspi->rx_dma_buf = dma_buf;
648 tspi->rx_dma_phys = dma_phys;
650 tspi->tx_dma_chan = dma_chan;
651 tspi->tx_dma_buf = dma_buf;
652 tspi->tx_dma_phys = dma_phys;
657 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
658 dma_release_channel(dma_chan);
662 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
667 struct dma_chan *dma_chan;
670 dma_buf = tspi->rx_dma_buf;
671 dma_chan = tspi->rx_dma_chan;
672 dma_phys = tspi->rx_dma_phys;
673 tspi->rx_dma_chan = NULL;
674 tspi->rx_dma_buf = NULL;
676 dma_buf = tspi->tx_dma_buf;
677 dma_chan = tspi->tx_dma_chan;
678 dma_phys = tspi->tx_dma_phys;
679 tspi->tx_dma_buf = NULL;
680 tspi->tx_dma_chan = NULL;
685 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
686 dma_release_channel(dma_chan);
689 static int tegra_slink_start_transfer_one(struct spi_device *spi,
690 struct spi_transfer *t)
692 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
695 unsigned total_fifo_words;
700 bits_per_word = t->bits_per_word;
702 if (speed != tspi->cur_speed) {
703 clk_set_rate(tspi->clk, speed * 4);
704 tspi->cur_speed = speed;
709 tspi->cur_rx_pos = 0;
710 tspi->cur_tx_pos = 0;
712 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
714 command = tspi->command_reg;
715 command &= ~SLINK_BIT_LENGTH(~0);
716 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
718 command2 = tspi->command2_reg;
719 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
721 tegra_slink_writel(tspi, command, SLINK_COMMAND);
722 tspi->command_reg = command;
724 tspi->cur_direction = 0;
726 command2 |= SLINK_RXEN;
727 tspi->cur_direction |= DATA_DIR_RX;
730 command2 |= SLINK_TXEN;
731 tspi->cur_direction |= DATA_DIR_TX;
733 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
734 tspi->command2_reg = command2;
736 if (total_fifo_words > SLINK_FIFO_DEPTH)
737 ret = tegra_slink_start_dma_based_transfer(tspi, t);
739 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
743 static int tegra_slink_setup(struct spi_device *spi)
745 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
752 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
757 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
759 spi->mode & SPI_CPOL ? "" : "~",
760 spi->mode & SPI_CPHA ? "" : "~",
763 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
765 /* Set speed to the spi max fequency if spi device has not set */
766 spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
767 ret = pm_runtime_get_sync(tspi->dev);
769 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
773 spin_lock_irqsave(&tspi->lock, flags);
774 val = tspi->def_command_reg;
775 if (spi->mode & SPI_CS_HIGH)
776 val |= cs_pol_bit[spi->chip_select];
778 val &= ~cs_pol_bit[spi->chip_select];
779 tspi->def_command_reg = val;
780 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
781 spin_unlock_irqrestore(&tspi->lock, flags);
783 pm_runtime_put(tspi->dev);
787 static int tegra_slink_prepare_message(struct spi_master *master,
788 struct spi_message *msg)
790 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
791 struct spi_device *spi = msg->spi;
793 tegra_slink_clear_status(tspi);
795 tspi->command_reg = tspi->def_command_reg;
796 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
798 tspi->command2_reg = tspi->def_command2_reg;
799 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
801 tspi->command_reg &= ~SLINK_MODES;
802 if (spi->mode & SPI_CPHA)
803 tspi->command_reg |= SLINK_CK_SDA;
805 if (spi->mode & SPI_CPOL)
806 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
808 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
813 static int tegra_slink_transfer_one(struct spi_master *master,
814 struct spi_device *spi,
815 struct spi_transfer *xfer)
817 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
820 reinit_completion(&tspi->xfer_completion);
821 ret = tegra_slink_start_transfer_one(spi, xfer);
824 "spi can not start transfer, err %d\n", ret);
828 ret = wait_for_completion_timeout(&tspi->xfer_completion,
830 if (WARN_ON(ret == 0)) {
832 "spi trasfer timeout, err %d\n", ret);
837 return tspi->tx_status;
839 return tspi->rx_status;
844 static int tegra_slink_unprepare_message(struct spi_master *master,
845 struct spi_message *msg)
847 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
849 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
850 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
855 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
857 struct spi_transfer *t = tspi->curr_xfer;
860 spin_lock_irqsave(&tspi->lock, flags);
861 if (tspi->tx_status || tspi->rx_status ||
862 (tspi->status_reg & SLINK_BSY)) {
864 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
866 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
867 tspi->command2_reg, tspi->dma_control_reg);
868 reset_control_assert(tspi->rst);
870 reset_control_deassert(tspi->rst);
871 complete(&tspi->xfer_completion);
875 if (tspi->cur_direction & DATA_DIR_RX)
876 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
878 if (tspi->cur_direction & DATA_DIR_TX)
879 tspi->cur_pos = tspi->cur_tx_pos;
881 tspi->cur_pos = tspi->cur_rx_pos;
883 if (tspi->cur_pos == t->len) {
884 complete(&tspi->xfer_completion);
888 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
889 tegra_slink_start_cpu_based_transfer(tspi, t);
891 spin_unlock_irqrestore(&tspi->lock, flags);
895 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
897 struct spi_transfer *t = tspi->curr_xfer;
900 unsigned total_fifo_words;
903 /* Abort dmas if any error */
904 if (tspi->cur_direction & DATA_DIR_TX) {
905 if (tspi->tx_status) {
906 dmaengine_terminate_all(tspi->tx_dma_chan);
909 wait_status = wait_for_completion_interruptible_timeout(
910 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
911 if (wait_status <= 0) {
912 dmaengine_terminate_all(tspi->tx_dma_chan);
913 dev_err(tspi->dev, "TxDma Xfer failed\n");
919 if (tspi->cur_direction & DATA_DIR_RX) {
920 if (tspi->rx_status) {
921 dmaengine_terminate_all(tspi->rx_dma_chan);
924 wait_status = wait_for_completion_interruptible_timeout(
925 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
926 if (wait_status <= 0) {
927 dmaengine_terminate_all(tspi->rx_dma_chan);
928 dev_err(tspi->dev, "RxDma Xfer failed\n");
934 spin_lock_irqsave(&tspi->lock, flags);
937 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
939 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
940 tspi->command2_reg, tspi->dma_control_reg);
941 reset_control_assert(tspi->rst);
943 reset_control_assert(tspi->rst);
944 complete(&tspi->xfer_completion);
945 spin_unlock_irqrestore(&tspi->lock, flags);
949 if (tspi->cur_direction & DATA_DIR_RX)
950 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
952 if (tspi->cur_direction & DATA_DIR_TX)
953 tspi->cur_pos = tspi->cur_tx_pos;
955 tspi->cur_pos = tspi->cur_rx_pos;
957 if (tspi->cur_pos == t->len) {
958 complete(&tspi->xfer_completion);
962 /* Continue transfer in current message */
963 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
965 if (total_fifo_words > SLINK_FIFO_DEPTH)
966 err = tegra_slink_start_dma_based_transfer(tspi, t);
968 err = tegra_slink_start_cpu_based_transfer(tspi, t);
971 spin_unlock_irqrestore(&tspi->lock, flags);
975 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
977 struct tegra_slink_data *tspi = context_data;
979 if (!tspi->is_curr_dma_xfer)
980 return handle_cpu_based_xfer(tspi);
981 return handle_dma_based_xfer(tspi);
984 static irqreturn_t tegra_slink_isr(int irq, void *context_data)
986 struct tegra_slink_data *tspi = context_data;
988 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
989 if (tspi->cur_direction & DATA_DIR_TX)
990 tspi->tx_status = tspi->status_reg &
991 (SLINK_TX_OVF | SLINK_TX_UNF);
993 if (tspi->cur_direction & DATA_DIR_RX)
994 tspi->rx_status = tspi->status_reg &
995 (SLINK_RX_OVF | SLINK_RX_UNF);
996 tegra_slink_clear_status(tspi);
998 return IRQ_WAKE_THREAD;
1001 static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
1003 struct device_node *np = tspi->dev->of_node;
1005 if (of_property_read_u32(np, "spi-max-frequency",
1006 &tspi->spi_max_frequency))
1007 tspi->spi_max_frequency = 25000000; /* 25MHz */
1010 static const struct tegra_slink_chip_data tegra30_spi_cdata = {
1011 .cs_hold_time = true,
1014 static const struct tegra_slink_chip_data tegra20_spi_cdata = {
1015 .cs_hold_time = false,
1018 static struct of_device_id tegra_slink_of_match[] = {
1019 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
1020 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1023 MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1025 static int tegra_slink_probe(struct platform_device *pdev)
1027 struct spi_master *master;
1028 struct tegra_slink_data *tspi;
1031 const struct tegra_slink_chip_data *cdata = NULL;
1032 const struct of_device_id *match;
1034 match = of_match_device(tegra_slink_of_match, &pdev->dev);
1036 dev_err(&pdev->dev, "Error: No device match found\n");
1039 cdata = match->data;
1041 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1043 dev_err(&pdev->dev, "master allocation failed\n");
1047 /* the spi->mode bits understood by this driver: */
1048 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1049 master->setup = tegra_slink_setup;
1050 master->prepare_message = tegra_slink_prepare_message;
1051 master->transfer_one = tegra_slink_transfer_one;
1052 master->unprepare_message = tegra_slink_unprepare_message;
1053 master->auto_runtime_pm = true;
1054 master->num_chipselect = MAX_CHIP_SELECT;
1055 master->bus_num = -1;
1057 platform_set_drvdata(pdev, master);
1058 tspi = spi_master_get_devdata(master);
1059 tspi->master = master;
1060 tspi->dev = &pdev->dev;
1061 tspi->chip_data = cdata;
1062 spin_lock_init(&tspi->lock);
1064 tegra_slink_parse_dt(tspi);
1066 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068 dev_err(&pdev->dev, "No IO memory resource\n");
1070 goto exit_free_master;
1072 tspi->phys = r->start;
1073 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1074 if (IS_ERR(tspi->base)) {
1075 ret = PTR_ERR(tspi->base);
1076 goto exit_free_master;
1079 spi_irq = platform_get_irq(pdev, 0);
1080 tspi->irq = spi_irq;
1081 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1082 tegra_slink_isr_thread, IRQF_ONESHOT,
1083 dev_name(&pdev->dev), tspi);
1085 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1087 goto exit_free_master;
1090 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1091 if (IS_ERR(tspi->clk)) {
1092 dev_err(&pdev->dev, "can not get clock\n");
1093 ret = PTR_ERR(tspi->clk);
1097 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1098 if (IS_ERR(tspi->rst)) {
1099 dev_err(&pdev->dev, "can not get reset\n");
1100 ret = PTR_ERR(tspi->rst);
1104 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1105 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1107 ret = tegra_slink_init_dma_param(tspi, true);
1110 ret = tegra_slink_init_dma_param(tspi, false);
1112 goto exit_rx_dma_free;
1113 tspi->max_buf_size = tspi->dma_buf_size;
1114 init_completion(&tspi->tx_dma_complete);
1115 init_completion(&tspi->rx_dma_complete);
1117 init_completion(&tspi->xfer_completion);
1119 pm_runtime_enable(&pdev->dev);
1120 if (!pm_runtime_enabled(&pdev->dev)) {
1121 ret = tegra_slink_runtime_resume(&pdev->dev);
1123 goto exit_pm_disable;
1126 ret = pm_runtime_get_sync(&pdev->dev);
1128 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1129 goto exit_pm_disable;
1131 tspi->def_command_reg = SLINK_M_S;
1132 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1133 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1134 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1135 pm_runtime_put(&pdev->dev);
1137 master->dev.of_node = pdev->dev.of_node;
1138 ret = devm_spi_register_master(&pdev->dev, master);
1140 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1141 goto exit_pm_disable;
1146 pm_runtime_disable(&pdev->dev);
1147 if (!pm_runtime_status_suspended(&pdev->dev))
1148 tegra_slink_runtime_suspend(&pdev->dev);
1149 tegra_slink_deinit_dma_param(tspi, false);
1151 tegra_slink_deinit_dma_param(tspi, true);
1153 free_irq(spi_irq, tspi);
1155 spi_master_put(master);
1159 static int tegra_slink_remove(struct platform_device *pdev)
1161 struct spi_master *master = platform_get_drvdata(pdev);
1162 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1164 free_irq(tspi->irq, tspi);
1166 if (tspi->tx_dma_chan)
1167 tegra_slink_deinit_dma_param(tspi, false);
1169 if (tspi->rx_dma_chan)
1170 tegra_slink_deinit_dma_param(tspi, true);
1172 pm_runtime_disable(&pdev->dev);
1173 if (!pm_runtime_status_suspended(&pdev->dev))
1174 tegra_slink_runtime_suspend(&pdev->dev);
1179 #ifdef CONFIG_PM_SLEEP
1180 static int tegra_slink_suspend(struct device *dev)
1182 struct spi_master *master = dev_get_drvdata(dev);
1184 return spi_master_suspend(master);
1187 static int tegra_slink_resume(struct device *dev)
1189 struct spi_master *master = dev_get_drvdata(dev);
1190 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1193 ret = pm_runtime_get_sync(dev);
1195 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1198 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1199 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1200 pm_runtime_put(dev);
1202 return spi_master_resume(master);
1206 static int tegra_slink_runtime_suspend(struct device *dev)
1208 struct spi_master *master = dev_get_drvdata(dev);
1209 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1211 /* Flush all write which are in PPSB queue by reading back */
1212 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1214 clk_disable_unprepare(tspi->clk);
1218 static int tegra_slink_runtime_resume(struct device *dev)
1220 struct spi_master *master = dev_get_drvdata(dev);
1221 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1224 ret = clk_prepare_enable(tspi->clk);
1226 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1232 static const struct dev_pm_ops slink_pm_ops = {
1233 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1234 tegra_slink_runtime_resume, NULL)
1235 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1237 static struct platform_driver tegra_slink_driver = {
1239 .name = "spi-tegra-slink",
1240 .owner = THIS_MODULE,
1241 .pm = &slink_pm_ops,
1242 .of_match_table = tegra_slink_of_match,
1244 .probe = tegra_slink_probe,
1245 .remove = tegra_slink_remove,
1247 module_platform_driver(tegra_slink_driver);
1249 MODULE_ALIAS("platform:spi-tegra-slink");
1250 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1251 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1252 MODULE_LICENSE("GPL v2");